Quadrature Divide-By-Three Frequency Divider and Low Voltage Muller C Element

Abstract

A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This frequency divider can be used in frequency synthesisers and as quadrature local oscillator generator.

Description

FIELD OF INVENTION

This invention relates in general to the fields of electronic circuits, microelectronics, and high/radio frequency integrated circuit design. More specifically, this invention relates to frequency division by a factor of three with quadrature input and quadrature output signals and high frequency, e.g. radio frequency, fully differential Muller C element operating at low supply voltage.

BACKGROUND OF THE INVENTION

Communication devices, including those intended for wireless applications, require a local oscillator (LO) for transmission or/and reception of radio frequency (RF) signals. For these devices, the ability to convert one single signal to different frequencies enables their compliance with regulatory requirements for different frequency bands in a cost effective manner.

Most frequency synthesizers based on phase-locked loop (PLL) include frequency dividers in order to compare the VCO frequency to a reference frequency in the PLL. Frequency dividers are also often included in the signal path from the frequency synthesizers to the LO input of the mixers. Examples are divide-by-two circuits to produce quadrature signals at half the VCO frequency and selectable frequency dividers for covering several frequency bands using the same frequency synthesizer.

In order to efficiently cover the largest possible number of different frequency bands using a minimum of signal sources, it can be necessary to reduce the frequency of an available signal by an odd factor of three.

In communication devices, quadrature representation is used for complex signals, which discern between positive and negative frequencies. The quadrature signals have a relative phase difference of 90 degrees; and are commonly referred to as in-phase “I” and quadrature “Q” signals. Usually, the “I” signal component leads the “Q” signal component by 90 degrees for positive frequencies. The quadrature representation is typically used for the local oscillator signal in frequency converters to achieve image rejection, in zero-IF circuitries and single-sideband generation, to distinguish between positive and negative frequency signal components. Signals of quadrature phases are for example required for the implementation of I/Q-up conversion (quadrature modulators in transmitters) and I/Q-down conversion (demodulators and image-rejection mixers in zero-IF, low-IF or super-heterodyne receivers). Quadrature LO signal generators are therefore important building blocks in communication devices incorporating I/Q frequency conversion.

The most frequently used techniques for generation of high frequency quadrature LO signals are based on passive complex polyphase networks, RC-CR networks and divide-by-two circuits using master-slave flip-flops.

For flexible frequency mapping to the various frequency bands, the available quadrature signals, which are generated by one of the methods above, need in some cases to be reduced in frequency by a factor of three without changing the quadrature phase relationship.

General low power requirement and battery operation of modern equipments dictate the use of low supply voltage circuits. For designs in deep-submicron CMOS technologies, low supply voltage is mandatory.

Divide-by-three frequency dividers of prior art typically consists of a chain master-slave D-type flip-flops connected in cascade, operating from a common clock signal, with a final signal being generated at a frequency which is equal to the clock signal frequency divided by three. Other divide-by-three frequency dividers require combinational logic between each flip-flop stage that is difficult to implement in high frequency applications due to the voltage headroom constraints and bandwidth limitations that can limit performance of the device.

Many prior art divide-by-three circuits are not capable of providing output signals with 50% duty cycle that can be critical for spurious response, timing and noise performance.

Divide-by-three implementation using digital circuitry is in general not trivial because three is not a power of two, and most digital logic involves power of two. In addition, implementation of a divide-by-three circuit for high/radio frequency operation using standard digital techniques requires highly advanced process technologies for adequate active device speed, a very high frequency clock and will result in unacceptable high power consumption.

Frequency division by a factor of three of quadrature signals using existing techniques results in twice or nearly twice the complexity and power-consumption of a single divide-by-three circuit.

Existing basic cells (such as standard flip-flops and threshold logic circuits) required for implementation of frequency dividers are not suitable for low voltage, high frequency operation because they suffer from one or several of the following weaknesses: lack of speed, too little voltage headroom and noise susceptibility.

U.S. Pat. No. 4,617,475 (1986) by Reinschmidt, describes a threshold logic voting circuit (majority gate) using bipolar differential pairs. The circuit is similar to the threshold circuit described here, but uses single-ended inputs and outputs. The circuit is not as suitable for high-speed RF applications as the threshold circuit in the present invention, as it is more susceptible to common mode noise at the inputs and output.

U.S. Pat. No. 5,838,166 (1998) by Nakamura, describes in some of the claims that a differential structure is used internally, but both inputs and outputs are single-ended digital signals with rail-to-rail swing. Thus, this circuit has noise disadvantage compared to the threshold circuit in the present invention. In this US patent, the circuit shown in FIG. 9 on sheet 8 most closely resembles the circuit presented in the present invention, but with the important, difference that all complementary input pairs share a single tail current source, whereas the threshold circuit presented in the present invention uses a separate tail current source for each differential input pair. The separate tail currents of the present invention make the circuit less sensitive to both static and dynamic variations in common mode voltage between each of the differential inputs.

U.S. Pat. No. 6,389,095 (2002) by Bo Sun, describes a divide-by-three frequency divider consisting of a chain master-slave D-type flip-flops connected in cascade requiring combinational logic between the flip-flop stages. Quadrature divide-by-three operation as shown in FIG. 8 is based on further cascading of flip-flops and combinational logic. This technique of implementing quadrature divide-by-three frequency dividers results in much higher complexity and higher power consumption thereof, and severely lower operation bandwidth compared to the divide-by-three frequency divider presented in the present invention.

Based on the preceding consideration, it is desirable to design a simple but robust, low-voltage and cost-effective frequency divider circuit which provides a divided-by-three signal frequency having quadrature phase relationship at both input and output, good amplitude and phase performance that does not require use of standard digital combinational logic.

SUMMARY OF THE INVENTION

A general method for synthesis of divide-by-three frequency division operating on quadrature inputs and quadrature outputs is disclosed together with a design of a low voltage low power wideband differential. Muller C element. Further, quadrature divide-by-three frequency divider circuits using SR-latches or Muller C elements, including the Muller C element of the present invention, are disclosed.

The disclosed divide-by-three implementations provide high-performance and cost optimal solutions to the task of dividing an available quadrature signal by an odd factor of three.

The disclosed differential Muller C element can be used in low-voltage applications, consumes little power and is capable of high frequency operation.

Further, the disclosed quadrature divide-by-three divider circuit using Muller C elements with three inputs according to the invention requires a minimum number of devices and thus promotes reliability, ease of implementation and low cost.

The present invention is achieved by means of the features as set forth in the appended set of claims, and is believed to obviate or mitigate at least one disadvantage of previous Muller C elements and quadrature divide-by-three frequency dividers in terms of cost effectiveness or/and low voltage and high frequency operation.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may best be understood by reference to the following description, taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and in which:

FIG. 1 shows a N-input Muller C element implemented in differential current steering threshold logic with unbuffered output and local feedback using MOSFET technology.

FIG. 2 shows the equivalent symbol of the N-input Muller C element with unbuffered output that is exemplified by, but not limited to, the MOSFET implementation in FIG. 1.

FIG. 3 shows a N-input Muller C element implemented in differential current steering threshold logic with buffered output and local feedback using MOSFET technology.

FIG. 4 shows the equivalent symbol of the N-input Muller C element with buffered output that is exemplified by, but not limited to, the MOSFET implementation in FIG. 3.

FIG. 5 shows a three-input Muller C element implemented in differential current steering threshold logic with unbuffered output and local feedback using MOSFET technology.

FIG. 6 shows the equivalent symbol of the three-input Muller C element with unbuffered output that is exemplified by, but not limited to, the MOSFET implementation in FIG. 5.

FIG. 7 shows a prior art implementation of a quadrature divide-by-three circuit using D flip-flops and combinational logic.

FIG. 8 shows another prior art implementation of a quadrature divide-by-three circuit using flip-flops and combinational logic.

FIG. 9 shows the Signal Transition Graph (STG) of a quadrature divide-by-three circuit.

FIG. 10 shows STG states, markings and enabled transitions of a quadrature divide-by-three circuit.

FIG. 11 shows timing diagram of a quadrature divide-by-three circuit together with the load resistor currents of the two three-input differential current steering Muller C elements M1 and M2 in FIG. 14.

FIG. 12 shows a general principle of a quadrature divide-by-three circuit implemented with SR-latches.

FIG. 13 shows a general principle of a quadrature divide-by-three circuit implemented with Muller C elements.

FIG. 14 shows a quadrature divide-by-three circuit implemented with two Muller C elements according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

While the claims define the features of the invention that are regarded as novel, it is, believed that the invention will be better understood from a consideration of the following description in conjunction with the figures.

The Muller C element is one of the basic building blocks of asynchronous circuits. It may have two or more inputs and one output. When all inputs are in the same state, the Muller C element switches state to the same state as the inputs. It will then keep this state until all inputs have switched to the other state.

In general, a Muller C element with N inputs can be implemented using a majority gate with 2N−1 inputs, where N−1 of the inputs are connected to the output. Alternatively, this can be seen as a majority gate with N input of weight 1 and one input (connected to the output) of weight N−1. The majority gate can be implemented with threshold logic, where the outputs are connected together in parallel. The output from a threshold logic gate with N inputs is given by the equation:

$q=\mathrm{sgn}\left(\sum _{i=1}^Nw_id_i\right),$

where q=−1 signifies that the output Q is binary ‘0’, and q=1 means that the output Q is binary ‘1’. Similarly, d_i=−1 signifies that the input D_i is binary ‘0’, and d_i=1 means that the input D_i is binary ‘1’. The value w_i gives the weight of input D_i.

In robust designs, differential signals with low voltage swing are often used to achieve high speed and good noise performance with relatively low energy consumption. High-speed frequency dividers are usually implemented in differential current steering logic, such as emitter-coupled logic with Bipolar Junction Transistors (BJT's) or source-coupled logic with Metal Oxide Semiconductor Field Effect Transistors (MOSFET's).

A high-speed threshold logic gate with N inputs using low voltage swing differential signals can be implemented using N differential pairs, each connected to one differential input and a tail current source/sink, and with the differential outputs (drains or collectors) connected to each other in parallel. Implementation-wise, the differential pairs should be saturated by the input voltage swing, so that the whole tail current is effectively steered to one of the two differential outputs. Two loads pull up/down the differential outputs towards the positive/negative (ground) supply voltage. The current summation caused by the parallel connection of the differential pairs implements the summation operation in the equation above. The input weight w_i is implemented by scaling the current from each current source/sink relative to the other current sources/sinks. For good device matching, the sizes of the input transistors can also by sized by the weight w_i. The differential output voltage takes on many values, proportional to the signed sum of the inputs. The sign operator sgn in the equation above is handled by decision operation of the succeeding circuitry, for instance by differential pair(s) with inputs connected to the outputs of the N-input threshold logic gate.

FIG. 1 shows a possible MOSFET design of a Muller C element with N inputs implemented as a differential current steering threshold logic gate with N+1 inputs and one unbuffered output. The first N inputs, which make up the inputs to the Muller C element, all have weight w=1. The last input have weight w=N−1 and is connected locally inside the Muller C element to the outputs QP, QN, causing the output to maintain the last binary value until all the N inputs switch to the opposite binary value.

FIG. 2 shows a generalised symbol of the Muller C element with N inputs, also valid for the specific implementation in FIG. 1.

For improved noise margins, at the expense of energy consumption and operating speed, a local buffer with voltage gain can be connected between the internal summing nodes and the outputs.

FIG. 3 shows a possible MOSFET design of a Muller C element with N inputs implemented as a differential current steering threshold logic gate with N+1 inputs and buffered output.

FIG. 4 shows a generalised symbol of the Muller C element with N inputs, also valid for the specific implementation in FIG. 3.

FIG. 5 shows a possible MOSFET implementation of a three-input Muller C element implemented as a differential current steering threshold logic gate with four inputs and one unbuffered output. The gates of the first three differential pairs (transistors Tr1 to Tr6) are connected to the three inputs D1P, D1N, D2P, D2N and D3P, D3N, while the sources are connected to the three tail current sources CS1, CS2 and CS3, respectively, each delivering current I₀. The gates of fourth differential pair (transistors Tr7 and Tr8) are connected to the output QP, QN, while the sources are connected to the tail current source CS4, delivering current 2×I₀. For matching, each the transistors Tr7 and Tr8 can be implemented as two transistors in parallel, each having the same physical dimensions as each of the transistors Tr1 to Tr6. The outputs QP, QN are connected to two load impedances Z1 and Z2, which pull the output up towards the positive supply voltage. The load impedances can be implemented as passive devices (e.g. polysilicon resistors), or as active devices (e.g. PMOS transistors operating in the linear region).

FIG. 6 shows a generalised symbol of the Muller C element with three inputs, also valid for the specific implementation in FIG. 5.

For all examples of MOSFET implementations of Muller C elements implemented as a differential current steering threshold logic gate in FIG. 1, FIG. 3, and FIG. 5, a complementary coupling can also be used, i.e. using PMOS instead of NMOS, and load impedances connected towards ground or negative supply voltage instead of positive supply voltage.

Frequency dividers by powers of two are well known in literature, and can be designed for high frequency operation. Frequency division at non-power-of-two ratios is not trivial to achieve. In this respect, the divide-by-three circuit according to the present invention advances state of the art.

A division circuit with 50% duty cycle must have the same number of input phases between each of the output phase transitions. In order to maintain the 90 degrees phase difference between I and Q, a division circuit with quadrature outputs must have the same number of input phases between each of the four output phase transitions in a cycle. Therefore, the number of input transitions in an output cycle must be a multiple of four with quadrature outputs. For example, this is achieved in a divide-by-two circuit without quadrature inputs (two input phases for each input period), since there are (2×2=4) input phases for each output period. For a divide-by-three circuit without quadrature inputs there are (2×3=6) input phases for each output period. Since this is not a multiple of four, such a circuit cannot be made with quadrature outputs. A divide-by-three circuit with quadrature inputs however, has (4×3=12) input phases for each output period. This can be implemented with three input phases between each output phase transition. This will be further described with reference to FIG. 11.

An asynchronous implementation of the divide-by-three circuit can be found by analysing the specification in form of a Signal Transition Graph (STG). This is a form of Petri-Net specially developed for asynchronous circuit synthesis.

As other Petri-Nets, Signal Transition Graphs (STGs) consist of a set of places, a set of transitions, and a marking, which is a set of places that are currently holding, tokens. There is also a mapping (arrows) from transitions to places and from places to transitions. Places in an STG can contain either zero or one token. In an STG, places with only one predecessor and one successor transition (one input arrow and one output arrow) are not drawn. Instead, arrows are drawn directly from one transition to another. Such an arrow contains an implicit place. When the implicit place contains a token (i.e. is part of the marking), the token is drawn directly on the arrow.

Transitions in an STG correspond to changes in binary signals in the circuit (inputs, outputs or internal signals). For a signal named X, X+ means that X goes from ‘0’ (LOW logic level) to ‘1’ (HIGH logic level), while X− means that X goes from ‘1’ to ‘0’. A transition with tokens on every input place (each arrow leading to the transition) is said to be enabled, and can fire at any time. Firing a transition corresponds to a change of the binary signal associated with the transition. If multiple signals are enabled at the same time, they can fire in any order. When firing a transition, tokens are removed from all the transition's input places (arrows leading to the transition) and inserted on all the transition's output places (arrows leading from the transition).

FIGS. 9 to 11 represent different presentations for the possible states of the quadrature divide-by-three circuit, and these will now be further explained.

FIG. 9 shows a Signal Transition Graph (STG) for the divide-by-three circuit. All places are of the implicit type, associated with the arrows going from one transition to another. There are 24 arrows, and hence implicit places, denoted with the letters A through X. Only the arrows marked A through P are necessary to describe the circuit. The other arrows are redundant because they are given by sequences of other arrows. For example, arrow Q is redundant because the sequence of the arrows B and C implies the transition ordering given by arrow Q. Without considering input-output interaction, the redundant arrows, however, completes the ordering of the input transitions (arrows Q-T) and the output transitions (arrows U-X).

The initial marking {A, U} in FIG. 9 corresponds to state A in the timing diagram in FIG. 11. As the STG shows, the only enabled transition is I_IN+. After this transition fires, the marking becomes {B, Q, U}. Now, I_OUT+ is the only enabled transition. FIG. 10 lists all the reachable states in sequence, with corresponding markings and enabled transitions. Note that exactly one transition is enabled in every state. This means that in each state, exactly one of the arrows A-P in FIG. 9 is contained in the marking. In the timing diagram of FIG. 11, the state labels A-P also correspond to which of the arrows A-P that is marked in the Signal Transition Graph in FIG. 9.

The stippled arrows (C, G, K and O) in FIG. 9 imply a timing relation (or feedback) between the outputs of the circuit and the inputs. They are necessary to avoid concurrently enabled transitions, which would increase the number of states and state holding signals. For a frequency divider, these arrows simply define a timing relation that limits the maximum division frequency. In practice, the frequency divider may be further optimised in the analogue domain for increased operation frequency or reduced energy consumption. Although the resulting circuit correctly divides by three, it may not necessarily adhere strictly to the output-input timing relation defined by the stippled arrows.

In order to find an asynchronous state machine implementation of the circuit, the state of the other signals can be analysed for each output transition. From FIG. 10, we find that the I_OUT+ transition is enabled when I_IN=‘1’, Q_IN=‘0’ and Q_OUT=‘0’, and the I_OUT− transition is enabled when I_IN=‘0’, Q_IN=‘1’ and Q_OUT=‘1’. This means that the I_OUT signal can be implemented with an asynchronous S/R-latch with

S=I_IN· Q_IN· Q_OUT, and

R= I_—IN·Q_—IN·Q_OUT.

Similarly, the Q_OUT signal can be,implemented with an asynchronous S/R-latch with

S= I_—IN· Q_—IN·I_OUT, and

R=I_IN·Q_IN· I_OUT.

FIG. 12 shows the implementation of the S and R relations above with standard asynchronous S/R-latches. The exact implementation of the logic can of course be optimised, for example to map to a set of available standard cells.

Because the minterm for the S input equals the minterm for the R input with all signals inverted, these S/R-latches correspond to three-input Muller C elements. When all inputs to a Muller C element are equal, its output is set to the input value. Otherwise, the output from the Muller C element keeps the previous output value.

FIG. 13 shows the quadrature divide-by-three circuit using Muller C elements in the general case. The divide-by-three circuit shown in FIG. 13 that uses two three-input Muller C elements can be implemented using two instances of the differential current steering threshold logic Muller C element in the present invention. The resulting circuit is shown in FIG. 14. Due to the differential implementation, the inversions shown on the Muller C element inputs in FIG. 13 are realised by simply swapping the complementary connections to the “_P” and the “_N” input terminals.

As mentioned above, FIG. 11 shows the timing diagram of a quadrature divide-by-three circuit together with the load resistor currents of the two three-input differential current steering Muller C according to the invention (elements M1 and M2 in FIG. 14). The letters A through P denotes the 16 different states. Seen from a divider implementation, there are four transitional states (B, F, J and N) in addition to the 12 input phases. In the transitional states, a change of the divider outputs will occur. One interesting property is that each of the 16 states corresponds to a unique combination of the four binary input/output signals I_IN, Q_IN, I_OUT and Q_OUT. This is necessary in order to implement the circuit as an asynchronous state machine without additional state holding elements. Since the number of states is the same as the number of possible combinations of the four binary signals, all combinations are part of the sequence. Therefore, no reset/initialisation circuitry is needed, because a correct implementation will always follow the correct sequence regardless of the start-up conditions.

The transient operation of the divide-by-three circuit using differential current steering threshold logic, as shown in FIG. 5, is explained below in connection with FIG. 11:

Starting at the state “A” in FIG. 11 (first line of FIG. 10), the signal values are I_IN=‘0’, Q_IN=‘0’, I_OUT=‘0’ and Q_OUT=‘0’. In the Muller C element M1 of FIG. 5, the differential pair connected to I_IN steers its tail current I₀ into the load impedance Z2 connected to the signal I_OUT_P when I_IN=‘0’. In the same Muller C element, the differential pair connected to Q_IN steers its tail current I₀ into the load impedance Z1 connected to the signal I_OUT_N when Q_IN=‘0’. Likewise, the differential pair connected to Q_OUT steers its tail current I₀ into the load impedance Z1 connected to the signal I_OUT_N when Q_IN=‘0’. Finally, the local feedback steers its tail current 2×I₀ into the load impedance Z2 connected to the signal I_OUT_P when Q_IN=‘0’. Thus, in the Muller C element M1, the sum of the current in the load impedance Z1 (connected to I_OUT_N) is 2×I₀, while the sum of the current in the load impedance Z2 (connected to I_OUT_P) is 3×I₀. This gives V(I_OUT_P)<V(I_OUT_N), which in differential logic is interpreted as I_OUT=‘0’. In the same way, it can be shown that in the Muller C element M2, the sum of the current in the load impedance Z1 (connected to Q_OUT_N) is 2×I₀, while the sum of the current in the load impedance Z2 (connected to Q_OUT_P) is 3×I₀. This gives V(Q_OUT_P)<V(Q_OUT_N), which in differential logic is interpreted as Q_OUT=‘0’. Thus, in state A, the circuit is stable, awaiting input changes.

A low-to-high transition on the input I_IN causes the circuit to change from state A to state B. The differential pair connected to I_IN in the Muller C element M1 now steers its tail current I₀ to flow through the load impedance Z1 connected to I_OUT_N instead of the load impedance Z2 connected to I_OUT_P. The net effect is that the sum of the current in the load impedance Z1 (connected to I_OUT_N) is 3×I₀, while the sum of the current in the load impedance Z2 (connected to I_OUT_P) is 2×I₀. This gives V(I_OUT_P)>V(I_OUT_N), which in differential logic is interpreted as I_OUT=‘1’. At the same time, the differential pair connected to I_IN in the Muller C element M2 now steers its tail current I₀ to flow through the load impedance Z2 connected to Q_OUT_P instead of the load impedance Z1 connected to Q_OUT_N. Here, the net effect is that the sum of the current in the load impedance Z1 (connected to Q_OUT_N) is 1×I₀, while the sum of the current in the load impedance Z2 (connected to Q_OUT_P) is 4×I₀. This gives V(Q_OUT_P)<V(Q_OUT_N), which in differential logic is interpreted as Q_OUT=‘0’.

The circuit is not stable in state B, as the output I_OUT goes to ‘1’ (while Q_OUT remains at ‘0’). The low-to-high transition of I_OUT switches the local feedback differential pair in the Muller C element M1 to steer its tail current 2×I₀ through the load impedance Z1 connected to I_OUT_N instead of the load impedance Z2 connected to I_OUT_P. The net effect is that the sum of the current in the load impedance Z1 (connected to I_OUT_N) is 5×I₀, while the sum of the current in the load impedance Z2 (connected to I_OUT_P) is 0. This gives V(I_OUT_P)>V(I_OUT_N), which in differential logic is interpreted as I_OUT=‘1’. At the same time, the differential pair connected to I_OUT in the Muller C element M2 now steers its tail current I₀ to flow through the load impedance Z1 connected to Q_OUT_N instead of the load impedance Z2 connected to Q_OUT_P. Here, the net effect is that the sum of the current in the load impedance Z1 (connected to Q_OUT_N) is 2×I₀, while the sum of the current in the load impedance Z2 (connected to Q_OUT_P) is 3×I₀. This gives V(Q_OUT_P)<V(Q_OUT_N), which in differential logic is interpreted as Q_OUT=‘0’. After this, the circuit is stable in state C, awaiting further input changes.

Each of the states A-P in the timing diagram of FIG. 11 can be analysed the same way. In FIG. 11, the timing diagram is also appended by the difference between the currents flowing in the loads Z1 and Z2 of each of the two three-input differential current steering Muller C elements M1 and M2 in FIG. 14. If linear loads are used, the differential output signals I_OUT and Q_OUT will be proportional to the current differences at the outputs. It can be seen that the I_OUT and Q_OUT output voltages has six stable differential values (three positive and three negative). The output signal transitions will be smoother when operating close to the maximum divider speed because the rise and fall times become a non-negligible portion of the cycle time.

Going through all possible states, the divide-by-three circuit shown in FIG. 14 provides differential quadrature signals with 50% duty cycle at one-third the input signal frequency.

The logical operation of an asynchronous divide-by-three circuit as detailed above is characterised by the following relationships of the input and output signals:

I_OUT=sgn(I_IN+ Q_—IN+ Q_OUT+2·I_OUT)

Q_OUT=sgn( I_—IN+ Q_—IN+I_OUT+2·Q_OUT)

where each of the signal variables I_IN, Q_IN, I_OUT, Q_OUT, and their corresponding inverted variables I_IN, Q_IN, I_OUT, Q_OUT in the above equations can take one of two numeric values, −1 and 1, at any time, with −1 as the equivalent of binary logic LOW ‘0’, and 1 as the equivalent of binary logic HIGH ‘1’. The appearance of the output signal variables on both sides of the equations implies that the asynchronous operation includes feedback from the outputs to the inputs.

Although the embodiment of the present invention is exemplified using MOSFET technology, alternate embodiments can be implemented in BJT or a suitable transistor technology. Persons skilled in the art will also understand that the loads (type and value) can be optimised to maximise circuit performance.

Claims

1. A quadrature divide-by-three frequency divider circuit with a plurality of asynchronous logic circuit elements and logic gate elements, said circuit comprising: a first input terminal for receiving a first input signal with an input signal frequency;a second input terminal for receiving a second input signal with said input signal frequency; wherein said first input signal and said second input signal have the same said input signal frequency and a relative phase difference of 90 degrees;a first output terminal for delivering a first output signal with an output signal frequency;a second output terminal for delivering a second output signal with said output signal frequency; wherein said first output signal and said second output signal have the same said output signal frequency and a relative phase difference of 90 degrees, and said output signal frequency is equal to one-third of said input signal frequency;circuitry to provide signal feedback;circuitry to provide said first output signal using said input and said output signals according to the relationship: I_OUT=sgn(I_IN+ Q_IN+Q_OUT+2·I_OUT); andcircuitry to provide said second output signal using said input and said output signals according to the relationship: Q_OUT=sgn(I_IN+ I_IN+Q_IN+I_OUT+2·Q_OUT);wherein each of said signal variables I_IN, Q_IN, I_OUT, Q_OUT, and their corresponding inverted variables I_IN, Q_IN, I_OUT, Q_OUT can take one of two numeric values, −1 and 1, at any time, with −1 as the equivalent of binary logic LOW ‘0’, and 1 as the equivalent of binary logic HIGH ‘1’.

2. A quadrature divide-by-three frequency divider circuit according to claim 1, wherein each of the quadrature input signals and each of the quadrature output signals has a substantially 50% duty cycle.

3. A quadrature divide-by-three frequency divider circuit according to claim 1, further comprising a plurality of threshold logic circuit elements and logic gate elements.

4. A quadrature divide-by-three frequency divider circuit according to claim 1, further comprising a plurality of Muller C elements and logic gate elements.

5. A quadrature divide-by-three frequency divider circuit according to claim 1, further comprising: a first and second Muller C element, each having three inputs and one output, and wherein each of the signals of said inputs and output can be single-ended or differential;circuitry to provide an inverted signal of an available signal;a first input of said first Muller C element connected to receive said first input signal having said input frequency;a second input of said first Muller C element connected to receive the inverted form of said second input signal having said input frequency;a third input of said first Muller C element connected to the inverted output of said second Muller C element;a first input of said second Muller C element connected to an output of said first Muller C element;a second input of said second Muller C element connected to receive the inverted form of said first input signal having said input frequency; anda third input of said second Muller C element connected to receive the inverted form of said second input signal having said input frequency.

6. A quadrature divide-by-three frequency divider circuit according to claim 1, further comprising a plurality of flip-flop elements and logic gate elements.

7. A quadrature divide-by-three frequency divider circuit according to claim 1, further comprising a plurality of SR-latches and logic gate elements.

8. A quadrature, divide-by-three frequency divider circuit according to claim 1, further comprising: said first input terminal being adapted for receiving said first input signal with said input signal frequency;said second input terminal being adapted for receiving said second input signal with said input signal frequency;said first output terminal being adapted for delivering said first output signal with said output signal frequency;said second output terminal being adapted for delivering said second output signal with said output signal frequency;a first and second SR-latch, each with a SET input, a RESET input, and an output;circuitry to provide a signal connected to the SET input of said first SR-latch according to the Boolean relationship: S=I_IN· Q_IN· Q_OUT;circuitry to provide a signal connected to the RESET input of said first SR-latch according to the Boolean relationship: R=I_IN·Q·IN·Q_OUT;circuitry to provide a signal connected to the SET input of said second SR-latch according to the Boolean relationship: S= I—IN· Q—IN·I_OUT; andcircuitry to provide a signal connected to the RESET input of said second SR-latch according to the Boolean relationship: R=I_IN·Q_IN· I_OUT.

9. A quadrature divide-by-three frequency divider circuit according to claim 1, further comprising: circuitry to provide an inverted signal of an available signal;a first and second SR-latch, each with a Set input, a Reset input, and an output;a first AND gates, with three inputs and one output, wherein said output of said first AND gate is connected to the S-input of said first SR-latch;a second AND gate with three inputs and one output, wherein said output of said second AND gate is connected to the R-input of said first SR-latch;a third AND gate with three inputs and one output, wherein said output of said third AND gate is connected to the S-input of said second SR-latch; anda fourth AND gate with three inputs and one output, wherein said output of said fourth AND gate is connected to the R-input of said second SR-latch;wherein:said first input signal has said input frequency connected to several inputs including a first input on said first AND gate and a second input on said fourth AND gate;the inverted form of said first input signal has said input frequency connected to several inputs including a first input on said second AND gate, and a second input on said third AND gate;said second input signal has said input frequency connected to several inputs including a second input on said second AND gate and a third input on said fourth AND gate;the inverted form of said quadrature-phase input signal has said input frequency connected to several inputs including a second input on said first AND gate and a third input on said third AND gate;an output of said first SR-latch is connected to a first input on said third AND gate;the inverted form of said output of said first SR-latch is connected to a first input on said fourth AND gate;an output of said second SR-latch is connected to a third input on said second AND gate;the inverted form of said output of said second SR-latch is connected to a third input on said first AND gate; andeach of said input and output signals can be single-ended or differential.

10. A differential Muller C element with N differential inputs, N being an integer[[,]] equal to or greater than two, and one differential output, adapted for comparing the weighted sum of said N input signals with a weighted threshold value by positive feedback of said output, and outputting a signal depending on the result of the comparison, comprising: N differential pairs, wherein a differential output current from each of said N differential pairs is controlled by said respective differential input signals, each of said differential pairs having a current supply for providing switching current, and each of said supply current supplies having unity relative current strength, I×IO;circuitry to provide positive feedback from said differential output of said differential Muller C element;circuitry to provide a differential feedback current of (N−1) times unity relative current strength, (N−1)×IO, wherein said differential feedback current is controlled by said positive feedback; andcircuitry for summing up said differential output currents from said N differential pairs and said differential feedback current.

11. A differential Muller C element according to claim 10, wherein said circuitry for summing up said currents comprises: a first load arrangement through which one of the complementary output current of each of said differential pair output currents and one of the complementary output current of said differential feedback current flow; anda second load arrangement through which the other of the complementary output current of each of said differential pair output currents and the other of the complementary output current of said differential feedback current flow.

12. A differential Muller C element according to claim 11, wherein said load arrangements are resistors.

13. A differential Muller C element according to claim 11, wherein said load arrangements are inductors.

14. A differential Muller C element according to claim 11, wherein said load arrangements are transistors biased to appropriate operation.

15. A differential Muller C element according to claim 11, wherein said load arrangements comprise combinations of resistors and transistors biased to appropriate operation.

16. A differential Muller C element according to claim 11, wherein said load arrangements are serial connections of inductors and transistors biased to appropriate operation,

17. A differential Muller C element according to claim 10 wherein said circuitry to provide said differential feedback current of (N−1) times unity relative current strength, (N−1)×IO, comprises a differential pair, wherein a differential output current is switched by said positive feedback circuitry, said differential pair having a current supply for providing switching current, and said supply current having (N−1 ) times unity relative current strength, (N−1)×IO.

18. A differential Muller C element according to claim 10, wherein each of said differential pairs comprises two transistors, the sources or emitters of which are connected together.

19. A differential Muller C element according to claim 10 characterized in that said circuitry to provide said differential feedback current of (N−1) times unity relative current strength, (N−1 )×IO, comprises a cross-coupled transistor pair having outputs connected to said outputs of said differential Muller C element, said cross-coupled transistor pair having a current supply for providing switching currents and said supply current having (N−1) times unity relative current strength, (N−1)×IO.

20. A differential Muller C element according to claim 19, wherein said cross-coupled transistor pair comprises a first transistor and a second transistor, wherein a gate or base of said first cross-coupled transistor is connected to a drain or collector of said second cross-coupled transistor, a gate or base of said second cross-coupled transistor is connected to a drain or collector of said first cross-coupled transistor, and the sources or emitters of said first and second cross-coupled transistors are connected to each other.

21. A differential Muller C element according to claim 17, wherein said circuitry to provide said positive feedback comprises a differential amplifier, with differential inputs and differential outputs, having signal gain equal to or larger than unity.

22. A differential Muller C element according to claim 10, wherein said current supply comprises a resistor or coupling of resistors through which said supply current flows.

23. A differential Muller C element according to claim 10, wherein said current supply comprises a transistor or coupling of transistors through which said supply current flows, and a bias control for changing a voltage of the gate or the base of said transistor or transistors.

24. A differential Muller C element according to claim 10, wherein said current supply comprises a serial connection of a transistor and a resistor through which said supply current flows, and a bias control for changing a voltage of the gate or the base of said transistor.

25. A differential Muller C element according to claim 23, wherein said bias control of said current supply is utilized to implement a power down function of said Muller C element.

26. A differential Muller C element according to claim 10, wherein N=3.

27. A quadrature divide-by-three frequency divider circuit according to claim 26, comprising two differential Muller C elements.