Claims
- 1. An apparatus for noise compensation, the apparatus comprising:
- a first adder configured to receive a control signal and add said control signal with an accumulated quantization error signal resulting in a combined signal;
- a masker configured to convert said combined signal to a plurality of voltage levels;
- a subtractor configured to subtract said plurality of voltage levels from said control signal resulting in a quantization error signal;
- a second adder configured to add said accumulated quantization error signal with said quantization error signal resulting in a new accumulated quantization error signal; and
- a memory device for storing said accumulated quantization error signal.
- 2. The apparatus as defined in claim 1, wherein said control signal is a 16 bit signal.
- 3. The apparatus as defined in claim 1, wherein said control signal is a 32 bit signal.
- 4. The apparatus as defined in claim 1, wherein said plurality of voltage levels are linear.
- 5. The apparatus as defined in claim 1, wherein said plurality of voltage levels are nonlinear.
- 6. The apparatus as defined in claim 1, wherein said memory device is n dimensional.
- 7. An apparatus for correcting bias in a feedback loop, the apparatus comprising:
- a subtractor configured to receive an error signal and subtract an accumulated quantization error signal from said error signal resulting in a combined signal;
- a Beta scalar configured to convert said combined signal to a bias free error signal;
- an adder configured to add said bias free error signal with said accumulated quantization error signal resulting in a new quantization error signal; and
- a memory device for storing said accumulated quantization error signal.
- 8. The apparatus as defined in claim 7, wherein said error signal is a 16 bit signal.
- 9. The apparatus as defined in claim 7, wherein said control signal is a 32 bit signal.
- 10. The apparatus as defined in claim 7, wherein said memory device is n dimensional.
- 11. A method for noise compensation, the method comprising the steps of:
- adding a control signal with an accumulated quantization error signal resulting in a combined signal;
- converting said combined signal to a plurality of voltage levels;
- subtracting said plurality of voltage levels from said control signal resulting in a quantization error signal;
- adding said accumulated quantization error signal with said quantization error signal resulting in a new accumulated quantization error signal;
- storing said accumulated quantization error signal; and
- using said plurality of voltage levels to control an integrator.
- 12. The method as defined in claim 11, wherein said control signal is a 16 bit signal.
- 13. The method as defined in claim 11, wherein said control signal is a 32 bit signal.
- 14. The method as defined in claim 11, wherein said plurality of voltage levels are linear.
- 15. The method as defined in claim 11, wherein said plurality of levels are nonlinear.
- 16. The method as defined in claim 11, wherein said accumulated quantization error signal is stored in an n dimensional memory device.
- 17. A method for correcting bias in a feedback loop, the method comprising the steps of:
- receiving an error signal in a subtractor, said subtractor configured to subtract an accumulated quantization error signal from said error signal resulting in a combined signal;
- converting said combined signal to a bias free error signal;
- adding said bias free error signal with said accumulated quantization error signal resulting in a new quantization error signal;
- storing said accumulated quantization error signal; and
- using said bias free error signal to correct bias in said feedback loop.
- 18. The method as defined in claim 17, wherein said error signal is a 16 bit signal.
- 19. The method as defined in claim 17, wherein said control signal is a 32 bit signal.
- 20. The method as defined in claim 17, wherein said accumulated quantization error signal is stored in an n dimensional memory device.
- 21. A computer readable medium having a program for noise compensation, the program containing logic configured to perform the steps of:
- adding a control signal with an accumulated quantization error signal resulting in a combined signal;
- converting said combined signal to a plurality of voltage levels;
- subtracting said plurality of voltage levels from said control signal resulting in a quantization error signal;
- adding said accumulated quantization error signal with said quantization error signal resulting in a new accumulated quantization error signal;
- storing said accumulated quantization error signal; and
- using said plurality of voltage levels to control an integrator.
- 22. The computer readable medium having a program as defined in claim 21, wherein said control signal is a 16 bit signal.
- 23. The computer readable medium having a program as defined in claim 21, wherein said control signal is a 32 bit signal.
- 24. The computer readable medium having a program as defined in claim 21, wherein said plurality of voltage levels are linear.
- 25. The computer readable medium having a program as defined in claim 21, wherein said plurality of levels are nonlinear.
- 26. The computer readable medium having a program as defined in claim 21, wherein said accumulated quantization error signal is stored in an n dimensional memory device.
- 27. A computer readable medium having a program for correcting bias in a feedback loop, the program containing logic configured to perform the steps of:
- receiving an error signal in a subtractor, said subtractor configured to subtract an accumulated quantization error signal from said error signal resulting in a combined signal;
- converting said combined signal to a bias free error signal;
- adding said bias free error signal with said accumulated quantization error signal resulting in a new quantization error signal;
- storing said accumulated quantization error signal; and
- using said bias free error signal to correct bias in said feedback loop.
- 28. The computer readable medium having a program as defined in claim 27, wherein said error signal is a 16 bit signal.
- 29. The computer readable medium having a program as defined in claim 27, wherein said control signal is a 32 bit signal.
- 30. The computer readable medium having a program as defined in claim 27, wherein said accumulated quantization error signal is stored in an n dimensional memory device.
CROSS REFERENCE TO RELATED APPLICATION
This document claims priority to and the benefit of the filing date of copending and commonly assigned U.S. Provisional Patent Application entitled QUANTIZATION NOISE COMPENSATOR, assigned Ser. No. 60/057,046, and filed Aug. 22, 1997 and is hereby incorporated by reference.
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