QUANTUM COMPUTER VERIFICATION APPARATUS AND METHOD

Abstract

A quantum computer verification apparatus includes: a division unit 1 that divides n qubits on which a quantum circuit U acts into m qubits and (n−m) qubits such that the number of CZ gates across the qubits becomes D=O(log n); a stabilizer operator calculation unit 2 that calculates a stabilizer operator {circumflex over ( )}sk for each k; an estimation unit 3 that randomly selects (i, j, i′, j′) T2 times for each k and calculates estimates of a real part of a value of the following expression to obtain T2 estimates;

Description

TECHNICAL FIELD

The present invention relates to a technique for verifying correctness of operation of a quantum computer.

BACKGROUND ART

A quantum computer having a size n is a computer that obtains a calculation result by preparing n qubits represented by a normalized two-dimensional complex vector, causing one arbitrary qubit gate and CZ gate to act on the qubits, and finally measuring some or all of the qubits with a Pauli Z basis also called a calculation basis.

In particular, in a case where a quantum computer is realized in a solid quantum system such as a superconducting circuit, an operation is performed on qubits prepared on a chip.

Such a chip is referred to as a quantum chip and is characterized by a graph representing qubits between which a 2-qubit gate can directly act. Each vertex of the graph represents the position of a qubit, which represents that a 2-qubit gate can directly act only between qubits connected by a side.

As a specific example, a graph characterizing a quantum chip with 53 qubits (refer to Non Patent Literature 1, for example) created by IBM Corporation is illustrated in FIG. 6. Numbers 0 to 52 are numbers of qubits, which represents that a 2-qubit gate can be directly applied between the 0th and the 1st, but cannot be directly applied between the 0th and the 2nd, for example.

In particular, by removing a constant number of sides independent of the value of n from a graph characterizing a quantum chip including n qubits, the graph can be separated into two partial graphs having O(n) vertices, and the quantum chip is said to be sparse.

In the case of FIG. 6, as indicated by a broken line, by removing two of the side between the 21st and 28th vertices and the side between the 25th and 29th vertices, it is possible to separate the graph into a partial graph including the 0th to 27th vertices and a partial graph including the 28th to 52nd vertices.

Verification of a quantum computer involves estimating how close a state ρ_out generated by repeating 1 and 2-qubit gates for qubits on an actually created quantum chip is to an ideal pure state |Ψ_t> expected from the theory. Specifically, the purpose of verification is to obtain a real number F_est satisfying |F−F_est|≤ε a with a probability of 1-δ or more for fidelity F=<Ψ_t|ρ_out|Ψ_t>, which is a quantity representing closeness.

Here, ρ_out is a 2ⁿ×2ⁿ semidefinite matrix with a trace value of 1, |Ψ_t> is a 2ⁿ-dimensional normalized complex vector, <Ψ_t| is conjugate transposition of |Ψ_t>, and ε and δ are real numbers satisfying 0<ε and δ<1.

As ε is closer to 0, it means that an actual fidelity and an obtained estimate are closer, and thus estimation accuracy is higher. In addition, as δ is closer to 0, an estimation failure probability decreases, and thus estimation with high reliability can be performed.

Usually, the size of a quantum device (referred to as B for clarity) available to obtain F_est is required to be less than the size of a quantum computer (referred to as A for clarity) to be verified. The efficiency of a verification method can be evaluated depending on how many copies of ρ_out are input to such a small-scale quantum device B to obtain F_est. Since copies of ρ_out are prepared by operating the quantum computer A to be verified as many times as a necessary number of copies, it can be said that the smaller the necessary number of copies is, the more efficient the verification method is. In particular, in a case where a required number of samples is a polynomial with respect to the size n of the quantum computer A to be verified, it is called efficient.

A method is known in which verification can be performed with a number of copies, which is less than or equal to

$\begin{array}{cc}O\left(\frac{1}{{ϵ}^2\delta }+\frac{2^n}{{ϵ}^2}\log \frac{1}{\delta }\right)& \left[\mathrm{Math}.1\right]\end{array}$

on average if the size of the quantum computer is denoted by n (refer to Non Patent Literature 2, for example). This method is highly versatile and can be used even when the quantum chip is not sparse.

First, for a natural number k satisfying 1≤k≤4ⁿ, W_k is set as n tensor products of a Pauli matrix.

$\begin{array}{cc}{\chi }_{p_{\mathrm{out}}}\left(k\right)\equiv \mathrm{Tr}\left[\frac{{\rho }_{out}{W}_k}{\sqrt{2^n}}\right]& \left[\mathrm{Math}.2\right]\end{array}$

• • is defined using this W_k. Using this definition, the fidelity F is written as the following expression.

$\begin{array}{cc}F=\sum _{k=1}^{4^n}{{\chi }_{{\rho }_{\mathrm{out}}}\left(k\right)}_{{\chi }_{❘{\psi }_t\rangle \langle {\psi }_t❘}}\left(k\right)& \left[\mathrm{Math}.3\right]\end{array}$

A procedure performed to estimate F is as follows.

1. First, the value of k is randomly selected according to the following probability distribution expressed as the following expression.

$\begin{array}{cc}{\left\{{{\chi }_{❘{\psi }_t\rangle \langle {\psi }_t❘}\left(k\right)}^2\right\}}_{k=1}^{4^n}& \left[\mathrm{Math}.4\right]\end{array}$

This is repeated L times, and the i-th selected k is written as k_i. Here, 1≤i≤L.

2. ρ_out is output m_i times from the quantum computer, and each is measured with the basis of W_ki corresponding to the selected value of k_i. As a result, A_ij∈{1, −1}(1≤j≤m_i) is obtained as a j-th measurement result.

By using this result, the value of

$\begin{array}{cc}{\tilde{X}}_i=\frac{{\sum }_{j=1}^{n{\iota }_i}{A}_{\mathrm{ij}}}{m_i\sqrt{2^n}{\chi }_{❘{\psi }_t\rangle \langle {\psi }_t❘}\left(k_i\right)}& \left[\mathrm{Math}.5\right]\end{array}$

is calculated. This operation is performed for all i.

3. The average

$\begin{array}{cc}\frac{{\sum }_{i=1}^L{\tilde{X}}_i}{L}& \left[\mathrm{Math}.6\right]\end{array}$

is calculated using {˜X_i}_i=1L obtained in step 2, and this is accepted as the estimate F_est of the fidelity F.

Since the value of k is selected according to the probability distribution expressed as the following expression,

$\begin{array}{cc}{\left\{{{\chi }_{❘{\psi }_t\rangle \langle {\psi }_t❘}\left(k\right)}^2\right\}}_{k=1}^{4^n}& \left[\mathrm{Math}.7\right]\end{array}$

the average

$\begin{array}{cc}\left(\sum _{i=1}^L{\tilde{X}}_i\right)/L& \left[\mathrm{Math}.8\right]\end{array}$

converges as expressed by the following expression.

$\begin{array}{cc}\sum _{k=1}^{4^n}{{\chi }_{❘{\psi }_t\rangle \langle {\psi }_t❘}\left(k\right)}^2\frac{\mathrm{Tr}\left[{\rho }_{out}{W}_k\right]}{\sqrt{2^n}{\chi }_{❘{\psi }_t\rangle \langle {\psi }_t❘}\left(k\right)}=\sum _{k=1}^{4^n}{\chi }_{{\rho }_{\mathrm{out}}}\left(k\right){\chi }_{❘{\psi }_t\rangle \langle {\psi }_t❘}\left(k\right)=F& \left[\mathrm{Math}.9\right]\end{array}$

Therefore, if

$\begin{array}{cc}L=\lceil \frac{8}{{ϵ}^2\delta }\rceil ,m_i=\lceil \frac{8\log 4/\delta }{2^n{{\chi }_{❘{\psi }_t\rangle \langle {\psi }_t❘}\left(k_i\right)}^{2}L{ϵ}^2}\rceil & \left[\mathrm{Math}.10\right]\end{array}$

is established using a ceiling function,

$\begin{array}{cc}\mathrm{Pr}\left[❘F_{\mathrm{est}}-F❘\ge ϵ\right]\le \delta & \left[\mathrm{Math}.11\right]\end{array}$

is derived according to Chebyshev's inequality and Heading's inequality. In the above-described method, Σ_i=1Lm_i copies are used in total, and the average value thereof becomes

$\begin{array}{cc}\sum _{i=1}^L\left[\sum _{k_i}{{\chi }_{❘{\psi }_t\rangle \langle {\psi }_t❘}\left(k_i\right)}^2{m}_i\right]\le \sum _{i=1}^L\left[1+\frac{2^{n+3}\log \left(4/\delta \right)}{L{ϵ}^2}\right]\le 1+\frac{8}{{ϵ}^2\delta }+\frac{2^{n+3}}{{ϵ}^2}\log \frac{4}{\delta }& \left[\mathrm{Math}.12\right]\end{array}$

at most.

CITATION LIST

Non Patent Literature

• Non Patent Literature 1: A. Kondratyev, Non-Differentiable Learning of Quantum Circuit Born Machine with Genetic Algorithm, SSRN 3569226, 2020
• Non Patent Literature 2: S. T. Flammia and Y.-K. Liu, Direct Fidelity Estimation from Few Pauli Measurements, Phys. Rev. Lett. 106, 230501, 2011

SUMMARY OF INVENTION

Technical Problem

Although the method proposed in Non Patent Literature 2 can be applied to verification of any quantum chip including n qubits, a number of copies, which is expressed as the following expression,

$\begin{array}{cc}O\left(\frac{1}{{ϵ}^2\delta }+\frac{2^n}{{ϵ}^2}\log \frac{1}{\delta }\right)& \left[\mathrm{Math}.13\right]\end{array}$

on average at most is required to perform the verification, and the number of copies increases exponentially with respect to n. In order for a quantum computer to exhibit practical superiority over a classical computer, n needs to be sufficiently large, but with such large n, it takes a huge amount of time to verify the quantum computer. Therefore, even if calculation itself can be performed at a high speed, it takes an exponentially long time to confirm whether the calculation is performed correctly, and the high speed in calculation is canceled by the time taken for verification. In particular, it is important to verify whether or not a correct quantum state can be output because small and medium-scale quantum computers currently being realized do not have an error correction function.

An object of the present invention is to provide a quantum computer verification apparatus and a quantum computer verification method capable of verifying a quantum computer more efficiently than before.

Solution to Problem

A quantum computer verification apparatus according to one aspect of the present invention includes: a division unit configured to divide n qubits on which a quantum circuit U acts into m qubits and (n−m) qubits such that the number of CZ gates across the qubits becomes D=O(log n), the quantum circuit U being able to be expressed by the following expression using an m-qubit gate V_i and an (n−m)−qubit gate W_j;

$\begin{array}{cc}U=\frac{1}{2^D}\sum _{i,j\in D,1^D}{\left(-1\right)}^{i,j}{V}_i\otimes W_j& \left[\mathrm{Math}.14\right]\end{array}$

a stabilizer operator calculation unit configured to randomly select a value of k∈{0, 1}_n T₁ times, and calculate a stabilizer operator {circumflex over ( )}s_k defined by the following equation for each k, where Q_i,j^†=V_i(×)W_j, k_i is an i-th bit of k, Z_i is a Pauli Z gate acting on an i-th qubit, i_L and j_L are L-th bits of i and j, i·j=(+)_L=1Di_Lj_L, and T₁ is a predetermined positive integer;

$\begin{array}{cc}\text{?}& \left[\mathrm{Math}.15\right]\end{array}$ $\text{?}\text{indicates text missing or illegible when filed}$

an estimation unit configured to randomly select (i, j, i′, j′) T₂ times for each k and calculate estimates of a real part of a value of the following equation to obtain T₂ estimates, where ρ_out is a state output by the quantum circuit U;

$\begin{array}{cc}{\left(-1\right)}^{i·j+i^{\prime }·j^{\prime }}\mathrm{Tr}\left[{\rho }_{\mathrm{out}}\left[Q_{i,j}^{+}\left(\prod _{i=1}^n{z}_i^{k_i}\right)Q_{i^{\prime },j^{\prime }}\right]\right]& \left[\mathrm{Math}.16\right]\end{array}$

an average calculation unit configured to obtain an average of the T₂ estimates for each k and set the obtained average as an estimate of Tr[ρ_out{circumflex over ( )}s_k] corresponding to each k; and a fidelity estimation value calculation unit configured to obtain an average of estimates of Tr[ρ_out{circumflex over ( )}s_k] corresponding to each k and set the average as an estimate F_est of fidelity F of the quantum circuit U.

Advantageous Effects of Invention

It is possible to verify a quantum computer more efficiently than before.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating an example of a functional configuration of a quantum computer verification apparatus.

FIG. 2 is a diagram illustrating an example of a processing procedure of a quantum computer verification method.

FIG. 3 is a diagram for describing a density of a quantum state.

FIG. 4 is a diagram for describing processing of an estimation unit 3.

FIG. 5 is a diagram illustrating an overview of an operation of an embodiment.

FIG. 6 is a diagram illustrating an example of a graph showing a quantum chip.

DESCRIPTION OF EMBODIMENTS

Hereinafter, an embodiment of the present invention will be described in detail. In the drawings, components having the same functions are denoted by the same reference numerals, and redundant description will be omitted.

[Quantum Computer Verification Apparatus and Method]

As illustrated in FIG. 1, a quantum computer verification apparatus includes, for example, a division unit 1, a stabilizer operator calculation unit 2, an estimation unit 3, an average calculation unit 4, and a fidelity estimation value calculation unit 5.

A quantum computer verification method is realized by each component of the quantum computer verification apparatus performing processing of steps S1 to S5 described below and illustrated in FIG. 2.

Note that the symbol “{circumflex over ( )}” used in the text would normally be written immediately above the immediately following character, but is written immediately before the character due to limitations of text notation. In mathematical expressions, these symbols are described at their normal positions, that is, directly above the characters. For example, “^{{circumflex over ( )}}X” in the text is written as follows in a mathematical expression.

$\begin{array}{cc}\hat{X}& \left[\mathrm{Math}.17\right]\end{array}$

The quantum computer verification apparatus and the quantum computer verification method are an apparatus and a method for performing verification of a quantum computer more efficiently than before. Verification involves evaluating closeness between an actually output quantum state and a theoretically expected correct quantum state as a quantity called fidelity.

In the following, a method of estimating fidelity by measuring a number of copies, which is expressed as the following expression,

$\begin{array}{cc}O\left(\frac{2^{12D}}{{ϵ}^6}{\left(D+\log \frac{1}{{\mathrm{\delta ϵ}}^4}\right)}^3\right)& \left[\mathrm{Math}.18\right]\end{array}$

through a number of qubits, which is less than n, for an n-qubit state with a density D is proposed. This method can also be applied to a general quantum computer similarly to the conventional method. This method is particularly efficient in a case where it is used for verification of a quantum computer in which the density of an output quantum state is D=O(log n). As described later, this method can also be used for verification of a quantum computer in which D≠O(log n).

The density of a quantum state is defined as follows. A gate set including single-qubit gates and controlled-Z (CZ) gates is conceived.

$\begin{array}{cc}\mathrm{CZ}\equiv \left(\begin{array}{cccc}1& 0& 0& 0\\ 0& 1& 0& 0\\ 0& 0& 1& 0\\ 0& 0& 0& -1\end{array}\right)& \left[\mathrm{Math}.19\right]\end{array}$

An n-qubit circuit configured by combining polynomial gates selected from the gate set is denoted by U. The n-qubit circuit U is abbreviated as a quantum circuit U. If the qubits are divided into two sets A and B having a size O(n), the number of gates across A and B in the quantum circuit U is defined as CUT(A:B). The density D of a quantum state |Ψ>=U|Oⁿ> is a minimum value of CUT(A:B) in all the divisions A:B. Here, |0ⁿ> is n tensor products of |0>=(1,0)^T.

A quantum circuit with a depth of O(log n) on a quantum chip represented by a graph that can be divided into two partial graphs having the same number of vertices by removing a constant number of sides is defined as a noisy intermediate-scale quantum (NISQ) computer. Therefore, the density of an output state of the NISQ computer is D=O(log n).

For example, a quantum chip that can be represented by a one-dimensional graph as illustrated in FIG. 3 is conceived. This graph can be divided into two partial graphs having the same number of vertices by removing the middle side. In a case where a quantum circuit having a depth d is mounted on the quantum chip represented by this graph, the density D is at most d.

F_est satisfying |F_est−<Ψ_t|ρ_out|Ψ_t≥ε is efficiently obtained with a probability of at least 1−δ for desired 0<ε and δ<1 and any n-qubit state |Ψ_t>=U|0ⁿ> with a density D=O(log n). Here, ρ_out is an actual output state of the NISQ computer, and it is assumed that this state does not change with time. Furthermore, it is assumed that any (m+1) qubit gates can be realized with an error of a diamond norm ε/4^D+2 for n/2≤m<n−1.

First, the division unit 1 divides the n qubits on which the quantum circuit U acts into m qubits and (n−m) qubits such that the number of CZ gates across the qubits becomes D=O(log n) (step S1). Since the density of |Ψ_t> is D=O(log n), such a division can necessarily be performed.

The divided quantum circuit U is represented as follows.

$\begin{array}{cc}U=\frac{1}{2^D}\sum _{i,j\in 0,1^D}{\left(-1\right)}^{i·j}{V}_i\otimes W_j& \left[\mathrm{Math}.20\right]\end{array}$

For any i and j, V_i and W_j respectively represent an m-qubit gate and an (n−m)-qubit gate.

The stabilizer operator calculation unit 2 randomly selects a value of k∈{0, 1}ⁿ T₁ times and calculates a stabilizer operator {circumflex over ( )}s_k defined by the following expression for each k (step S2). The stabilizer operator calculation unit 2 selects a value of k∈{0, 1}ⁿ, for example, uniformly randomly, T₁ times.

$\begin{array}{cc}\text{?}=\frac{1}{4^D}\text{?}\left[Q_{i,j}^{+}\left(\prod _{i=1}^n{z}_i^{k_i}\right)Q_{i^{\prime },j^{\prime }}\right]& \left[\mathrm{Math}.21\right]\end{array}$ $\text{?}\text{indicates text missing or illegible when filed}$

T₁ is a predetermined positive integer. Q_i,j^†=V_i(×)W_j, k_i is an i-th bit of k, Z_i is a Pauli Z gate acting on the i-th qubit, i_L and j_L are L-th bits of i and j, and i·j=(+)_L=1Di_Lj_L. Here, (×) represents a tensor product. (+) represents an exclusive OR. † represents complex conjugate transposition.

The estimation unit 3 randomly selects (i, j, i′, j′) T₂ times for each k, and calculates estimates of the real part of the values of the following expression to obtain T₂ estimates (step S3). The estimation unit 3 uniformly randomly selects (i, j, i′, j′) T₂ times for each k. The obtained T₂ estimates are sent to the average calculation unit 4. T₂ is a predetermined positive integer. Tr represents a diagonal sum.

$\begin{array}{cc}{\left(-1\right)}^{i·j+i^{\prime }·j^{\prime }}\mathrm{Tr}\left[{\rho }_{\mathrm{out}}\left[Q_{i,j}^{+}\left(\prod _{i=1}^n{z}_i^{k_i}\right)Q_{i^{\prime },j^{\prime }}\right]\right]& \left[\mathrm{Math}.22\right]\end{array}$

The estimation unit 3 calculates an expected value of Σ_L∈_{{0,1}{circumflex over ( )}3}β(i, j, i′, j′, L)/2 as an estimate of the real part of the above equation (step S3).

For this purpose, the estimation unit 3 operates the quantum circuit in FIG. 4 T₃ times for each L, for example. T₃ is a predetermined positive integer. H represents a Hadamard gate, and X represents a Pauli X gate. Symbols with vertical lines attached to square boxes (V_i^†, V_i,^†, W_j^†, W_j,^†) represent controlled quantum gates written in the square boxes. Further, for any L∈{0,1}³, C_L=S{circumflex over ( )}(δ_L1,1δ_L2,0)H{circumflex over ( )}(δ_L1+L2,1)X{circumflex over ( )}(L₃). S=√Z with Z as a Pauli Z gate. δ_a,b is Kronecker delta. δ_a,b=1 if a=b, and δ_a,b=0 if a≠b. The mark on the meter represents a Pauli Z measurement. o∈{0, 1}, b∈{0, 1}, and z∈{0, 1}ⁿ represent measurement results.

A part surrounded by a broken line on the upper side in FIG. 4 is referred to as a first quantum circuit. The first quantum circuit is a quantum circuit including V_i that represents an m-qubit gate. Inputs of the first quantum circuit are |0> and m qubits divided by the division unit 1 in ρ_out.

A part surrounded by a broken line on the lower side in FIG. 4 is referred to as a second quantum circuit. The second quantum circuit is a quantum circuit including W_j that represents an m-qubit gate. Inputs of the second quantum circuit are |0> and n-m qubits divided by the division unit 1 in ρ_out.

β(i, j, i′, j′, L)=(−1)^{{circumflex over ( )}}((1+δ_L1,0δ_L2,0)o)α(i, j, i′, j′). It is assumed that α(i, j, i′, j′)∈{1, −1} becomes 1 only when (+)_i=1ⁿz_ik_i=i·j(+)i′·j′(+)b is satisfied and becomes −1 otherwise.

The average calculation unit 4 obtains an average of the T₂ estimates for each k, and sets the obtained average as an estimate of Tr[ρ_out{circumflex over ( )}s_k] corresponding to each k (step S4). The obtained estimate of Tr[ρ_out{circumflex over ( )}s_k] corresponding to each k is sent to the fidelity estimation value calculation unit 5.

The fidelity estimation value calculation unit 5 obtains an average of the estimate of Tr[ρ_out{circumflex over ( )}s_k] corresponding to each k, and sets the average as an estimate F_est of fidelity F of the quantum circuit U (step S5). In step S2, k is selected T₁ times. Therefore, it can also be said that the fidelity estimation value calculation unit 5 obtains an average of estimates of T₁ Tr[ρ_out{circumflex over ( )}s_k] and uses the average as an estimate F_est of the fidelity F of the quantum circuit U.

An overview of such an operation is illustrated in FIG. 5. First, the qubits of the quantum circuit U are divided into m qubits and n-m qubits. The m qubits of the output state ρ_out of the quantum circuit U and |0> are input to the first quantum circuit. The n-m qubits of the output state ρ_out of the quantum circuit U and |0> are input to the second quantum circuit.

In FIG. 5, calculation performed using measurement results of the first quantum circuit and the second quantum circuit is represented as classical post-processing.

Since the size of the first quantum circuit is m+1 and the size of the second quantum circuit is n−m+1, and both are less than n, the size of the quantum circuit used for verification is less than the size of the quantum computer (in this case, a NISQ computer) to be verified.

In the conventional method, it is used that fidelity to be estimated can be written by the sum of expected values of tensor products of a Pauli matrix. Therefore, a required number of copies increases exponentially with respect to the size n of the quantum computer to be verified. On the other hand, this problem is avoided by using a decomposition method different from the conventional method as in the above embodiment, for example.

The number of samples required for the method described in the embodiment is at most the value expressed as the following expression.

$\begin{array}{cc}\frac{32768{\left(5·4^D+1\right)}^6}{{ϵ}^6}{\left(\log \frac{10240{\left(5·4^D+1\right)}^4}{{\mathrm{\delta ϵ}}^4}\right)}^3=O\left(\frac{{16}^D}{{ϵ}^2}\left(D+\log \frac{1}{{\mathrm{\delta ϵ}}^4}\right)\right)& \left[\mathrm{Math}.23\right]\end{array}$

In the case of a NISQ computer, this number is a polynomial with respect to the qubit number n because D=O(log n). In particular, in a case where D, δ, and ε are constants, the time required for verification does not change and is constant even when the size of the quantum computer increases. That is, the method described in the embodiment makes it possible to verify the NISQ computer in a shorter time than before.

The method described in the embodiment can also be applied to a case where the quantum computer to be verified is not a NISQ computer, in other words, a case where a quantum chip is not sparse although the depth is O(log n). Even in this case, the method described in the embodiment is more efficient than the conventional method. Many quantum chips currently produced can be represented by a plane graph having a constant maximum order. In the case of such representation, the dependency of the number of samples in the method described in the embodiment is 2{circumflex over ( )}(O((√n)log n)). 2{circumflex over ( )}(O((√n)log n)) is not a polynomial, but is smaller than the conventional number of samples, O(2n).

Modified Example

While the embodiment of the present invention has been described above, specific configurations are not limited to the embodiment, and it is needless to say that appropriate design changes, and the like are included in the present invention without deviating from the gist of the present invention.

The various types of processing described in the embodiment may be performed not only in chronological order in accordance with the described order, but also in parallel or individually depending on the processing capability of a device that performs the processing or as necessary.

Claims

1. A quantum computer verification apparatus comprising processing circuitry configured to: divide n qubits on which a quantum circuit U acts into m qubits and (n−m) qubits such that a number of CZ gates across the qubits becomes D=O(log n), the quantum circuit U being assumed to be able to be expressed by the following expression using an m-qubit gate Vi and an (n−m) qubit gate Wj;

2. A quantum computer verification method comprising: a division step in which a division unit divides n qubits on which a quantum circuit U acts into m qubits and (n−m) qubits such that a number of CZ gates across the qubits becomes D=O(log n), the quantum circuit U being assumed to be able to be expressed by the following expression using an m-qubit gate Vi and an (n−m) qubit gate Wj by a stabilizer operator calculation unit;