Patent Application
20250212701
The present application relates to the field of quantum devices wherein at least one item of quantum information based on a given quantum state from at least two measurable levels is used. This quantum state is referred to as qubit or quantum bit.
One particular type of qubit is the spin qubit when the intrinsic degree of freedom of the spin of individual electrons is used for coding the quantum information.
Qubits can be formed in a semiconductor material within nano-sized electrostatically and/or physically defined confinement structures. These confinement structures are typically referred to as “quantum dots”.
A quantum dot behaves like a potential well confining one or more elementary charges (electrons or holes) in a semiconductor region.
To measure the state of a qubit, proceeding with a spin/charge conversion that makes it possible to convert the spin state of the charged particles into a state of charge of the quantum dots containing said particles is known. It is then necessary to measure this state of charge in order to deduce therefrom the spin state of the charged particles before conversion. For this, a means of measuring the state of charge is generally disposed facing or in proximity to each quantum dot.
A qubit can in particular be read using another quantum dot referred to as a “reading island” or “detection island” coupled to that of the qubit intended to be read. These two elements form two potential wells separated by a potential barrier.
Devices in which the detection islands and quantum dots are disposed facing each other and in one and the same plane parallel to the main plane of a substrate on which the quantum dots and detection islands are formed are known.
The document by R Pillarisetty “High Volume Electrical Characterization of Semiconductor Qubits”, 2019 IEEE International Electron Devices Meeting (IEDM) proposes, for example, a device with quantum dots formed in a first elongate semiconductor block (“fin”) and detection islands formed in a second elongate semiconductor block parallel to the first block.
The problem is posed of producing a new quantum device that is preferably improved in terms of integration density while retaining good detection sensitivity.
According to one aspect, the present invention relates to a quantum electronic device provided with a substrate, this substrate being clad:
Advantageously, the dielectric region is configured so as to allow an electrostatic coupling between a first semiconductor region from the semiconductor regions of the first set and a given semiconductor region from the semiconductor regions of the first set or of the second set, the first semiconductor region and the given semiconductor region being located on one and the same first axis, the dielectric region being configured so as to prevent an electrostatic coupling between the first semiconductor region and another given semiconductor region distinct from the given semiconductor region, the other given semiconductor region being located on a second axis passing through the first semiconductor region, the second axis being distinct from the first axis and non-collinear with the first axis.
According to a possible implementation, the dielectric region can be configured so as to allow an electrostatic coupling between the first lower semiconductor region and the second lower semiconductor region and so as to allow an electrostatic coupling between the first upper semiconductor region and the second upper semiconductor region.
The dielectric region, through the heterogeneous composition thereof, can also be designed so as to prevent an electrostatic coupling between the first lower semiconductor region and the second upper semiconductor region and so as to prevent an electrostatic coupling between the first upper semiconductor region and the second lower semiconductor region.
Thus a device is used with quantum dots that can be disposed in different planes and here a coupling is allowed between these quantum dots and semiconductor regions or detection islands disposed opposite or facing while preventing a coupling with regions of different levels.
Advantageously, the dielectric region between the first set of semiconductor regions and the second set of semiconductor regions is designed with a heterogeneous dielectric composition so that, in a central portion located between the first lower semiconductor region and the second upper semiconductor region and between the first upper semiconductor region and the second lower semiconductor region, the dielectric region is formed by an empty space, or has a composition with a given dielectric material and a given dielectric constant k2, and so that, in another portion located between the first lower semiconductor region and the second lower semiconductor region or between the first upper semiconductor region and the second upper semiconductor region, the dielectric region has a second composition and a higher relative dielectric constant than the given dielectric constant k2.
According to one embodiment, the dielectric region between the first set of semiconductor regions and the second set of semiconductor regions can be formed:
According to another possibility of implementation, the dielectric region with a heterogeneous composition between the first set of semiconductor regions and the second set of semiconductor regions is formed:
According to one variant, the dielectric region can be provided with a heterogeneous composition so as to allow an electrostatic coupling between the first lower semiconductor region and the second upper semiconductor region and so as to allow an electrostatic coupling between the first upper semiconductor region and the second lower semiconductor region, and so as to prevent an electrostatic coupling between the first lower semiconductor region and the second lower semiconductor region and to prevent an electrostatic coupling between the first upper semiconductor region and the second upper semiconductor region.
In this case, advantageously, the dielectric region between the first set and the second set of semiconductor regions can be formed:
According to another variant, the dielectric region can be configured so as to allow an electrostatic coupling between the first lower semiconductor region and the first upper semiconductor region and so as to allow an electrostatic coupling between the second lower semiconductor region and the second upper semiconductor region, said dielectric region furthermore being designed so as to prevent an electrostatic coupling between firstly the first lower semiconductor region and secondly respectively the second upper semiconductor region and the second lower semiconductor region, and so as to prevent an electrostatic coupling between firstly the first upper semiconductor region and secondly the second lower semiconductor region and the second upper semiconductor region.
According to a particular embodiment of this variant, the dielectric region between the first set of semiconductor regions and the second set of semiconductor regions can be designed with a heterogeneous dielectric composition so that, between the first set of semiconductor regions and the second set of semiconductor regions, the dielectric region is formed by a juxtaposition of a first dielectric portion, a central dielectric portion and a second dielectric portion, the central dielectric portion being arranged between the first dielectric portion and the second dielectric portion, the first dielectric portion, the second direction portion and the central dielectric portion each being arranged facing the first lower semiconductor region, the first upper semiconductor region, the second lower semiconductor region and the second upper semiconductor region, the central dielectric portion being made from a given dielectric material having a first dielectric constant, the first electric portion and the second electric portion being based on at least one dielectric material different from said given dielectric material and with a respective dielectric constant lower than that of the central dielectric portion.
According to a particular embodiment, the separation zones can be designed so as to allow an electrostatic coupling between the first lower semiconductor region and the first upper semiconductor region and so as to allow an electrostatic coupling between the second lower semiconductor region and the second upper semiconductor region.
According to a possibility of implementation of the device, the first lower semiconductor region and the first upper semiconductor region are regions respectively of a lower semiconductor bar and of an upper semiconductor bar, the lower semiconductor bar and the upper semiconductor bar extending parallel to a first direction parallel to a main plane of the substrate. Thus a plurality of quantum dots can be distributed along one and the same first semiconductor bar and a plurality of detection islands can be distributed along a second semiconductor bar located facing the first semiconductor bar.
Advantageously, the quantum electronic device can furthermore comprise: a plurality of control gates of the lower semiconductor bar and of the upper semiconductor bar, the control gates extending in a second direction producing a non-zero angle with the first direction and advantageously orthogonal to the first direction.
According to an embodiment, the quantum electronic device can furthermore comprise:
According to another aspect, the present invention relates to a method for making a quantum electronic device and in particular a quantum device as defined above.
Another aspect of the invention provides a method for manufacturing a quantum device as defined above and wherein forming the first set of semiconductor regions and of the second set of semiconductor majors comprises the steps of:
Forming the second dielectric region can comprise the steps of:
According to a possibility of implementation, after depositing the first dielectric material and prior to depositing the given dielectric material: a partial removal of the first dielectric material is implemented in the trench, and wherein, after the given dielectric material is deposited and prior to the formation of the upper dielectric portion, a partial removal of the given dielectric material is implemented.
According to a possibility of implementation, forming the second heterogeneous dielectric region can comprise steps of:
According to another possibility of implementation, the method for forming the dielectric region can comprise steps of:
The present invention will be better understood upon reading the description of exemplary embodiments provided merely for illustrative purposes and which are in no way limiting, with reference to the appended drawings wherein:
Identical, similar or equivalent parts of the various figures bear the same reference numerals so as to make it easier to switch from one figure to another.
The various parts shown in the figures are not necessarily drawn to a uniform scale, to make the figures more legible.
In addition, in the following description, terms which depend on the orientation of the structure such as “above”, “below”, “lower”, “upper”, “juxtaposed”, “superimposed” apply on the assumption that the structure is oriented as illustrated in the figures.
The device is arranged on a substrate 5, which may be, for example, of the semiconductor-on-insulator type, in particular of the SOI (silicon-on-insulator) type or of the bulk type, for example of silicon.
The device is here provided with quantum dots BQ1, BQ2 formed in a first set of superimposed semiconductor regions 102L, 104L, for example of silicon or germanium. A quantum dot BQ1 is thus made in a first so-called “lower” semiconductor region 102L, while another quantum dot BQ2 disposed above the first lower semiconductor region is formed in a first so-called “upper” semiconductor region 104L.
The quantum dots BQ1 and BQ2 each confine at least one elementary charge (electron(s) or hole(s)). Preferably, each quantum dot BQ1, BQ2 herein includes a single elementary charge. The spin of this charge in particular an electron, can be provided for coding the quantum information. In this case, the qubits associated with quantum dots BQ1, BQ2 are spin qubits.
To enable detection of a quantum state also referred to as “state of charge” of the quantum dots BQ1, BQ2, a charge detection structure is provided in proximity to and in this example in front of the quantum dots BQ1, BQ2.
This detection structure comprises detection islands ID1, ID2 formed in a second set of superimposed semiconductor regions 102R, 104R, typically based on the same semiconductor material as the regions 102L, 104L. A detection island ID1 is thus made in a second lower semiconductor region 102R which faces the first lower semiconductor region 102L, while another detection island ID2 is formed in a second upper semiconductor region 104R disposed above the second lower semiconductor region 102R and faces the first upper semiconductor region 104L.
The first semiconductor regions 102L, 104L are thus each designed to form a qubit, while the second semiconductor regions 102R, 104R are dedicated to reading the qubits.
In the particular exemplary embodiment illustrated, the lower semiconductor regions 102L, 102R are arranged in one and the same first plane P1, while the upper semiconductor regions 104L, 104R are arranged in one and the same second plane P2, the first and second planes P1 and P2 being parallel to a main plane of the substrate 5 (i.e. a plane defined throughout the description as a plane passing through the substrate 5 and which is parallel to the plane [0; x; y] of the orthogonal reference frame [0; x; y; °z]).
The device is also provided with at least one dielectric region RD based on at least one dielectric material located between, on the one hand, the superimposition of quantum dots BQ1, BQ2 and, on the other hand, the superimposition of islands ID1, ID2.
In this exemplary embodiment, the operation of the device is based on capacitive coupling, also referred to as “electrostatic coupling”, between each quantum dot BQ1, BQ2 and a detection island ID1, ID2 arranged opposite the quantum dot BQ1, BQ2. In this case, the dielectric material(s) of the dielectric region RD are selected in particular in terms of relative permittivity or dielectric constant and the dimensions D1, D2 (corresponding respectively to the distance between upper semiconductor regions and the distance between lower semiconductor regions) of this dielectric region RD for achieving such electrostatic coupling. Such coupling can result in a measurable useful signal which is greater than a parasitic signal and which can be in the order of several fF (femtofarads).
For example, for achieving electrostatic coupling between a quantum dot and an island facing this dot, the dielectric region RD can be formed from SiO2, SiN, Al2O3, HfO2, and with dimensions D1, D2 of between 10 nm and 60 nm, for example, advantageously between 20 nm and 40 nm.
For achieving electrostatic control of quantum dots and detection islands, provision is made for gates formed by a conductive or semiconductive block of gate material 22, for example polysilicon, against a dielectric gate layer 21 disposed between the gate block and the semiconductive regions. The arrangement proposed in
The quantum dots BQ1, BQ2 are controlled by a first group of superimposed gates GI1, GS1, each gate GI1, GS1 being herein disposed against a quantum dot BQ1, BQ2. A first so-called “lower” gate GI1 for electrostatic control of the first lower semiconductor region 102L is located in the first plane P1, while a first so-called “upper” gate GS1 for electrostatic control of the first upper semiconductor region 104L is located in the second plane P2.
The first upper gate GS1 is superimposed on and separated from the first lower gate GI1 via a first insulation zone ZI1. This first insulation zone ZI1 between the lower GI1 and upper GS1 gates is typically of insulating material and preferably of sufficient thickness e0 to electrically insulate the gates GI1, GS1 from each other. For example, the first insulation zone ZI1 is formed from SiO2 and has a thickness e0 which may be between 5 nm and 20 nm, for example.
For achieving electrostatic control of the semiconductor regions 102R, 104R, a second group of superimposed gates GI2, GS2 is provided, each gate GI2, GS2 being herein juxtaposed against a semiconductor region 124a, 124b. A second lower gate GI2 is located in the first plane P1, while a second upper gate GS2 is located in the second plane P2 and insulated from the lower gate GS2 via an insulation zone Z12. This second insulation zone ZI2 of the lower GI2 and upper GS2 gates is advantageously provided with a thickness and material similar to that of the first insulation zone ZI1.
In this exemplary embodiment, there is thus advantageously an alignment of the lower gates GS1, GR1 and the lower semiconductor regions 102L, 102R in one and the same plane P1 and an alignment of the upper gates GS2, GR2 and the upper semiconductor regions 104L, 104R in one and the same upper plane P2 distinct from the plane P1.
According to a possible implementation of the device, it can be provided that each qubit stage is independent of the other stages, thus preventing electrostatic coupling between the first lower semiconductor region 102L and the first upper semiconductor region 104L. Electrostatic coupling between the second lower semiconductor region 102R and the second upper semiconductor region 104R is then also typically prevented. In this case, only horizontal interactions (in other words in directions parallel to the main plane of the substrate) between quantum dots BQ1, BQ2 and detection islands ID1, ID2 are promoted.
To enable the lower stage to be insulated from the upper stage, so-called “separation” zones ZS1, ZS2 arranged respectively between the first lower and upper semiconductor regions 102L and 104L and between the second lower and upper semiconductor regions 102R and 104R are provided, herein preferably of dielectric material, for example SiO2, and with a sufficient thickness (also referred to as height) H1, H2, for example of at least 30 nm, and typically of between 30 nm and 100 nm.
It can be envisaged integrating several other quantum dots in the lower stage N1 in which quantum dot BQ1 is located and several other quantum dots in the upper stage N2 in which quantum dot BQ2 is located. In this case, the first lower semiconductor region 102L may be a region of a semiconductor block typically in the form of a bar (cross-section view in
Similarly, the first upper semiconductor region 104L may be formed in another semiconductor bar referred to as the first upper semiconductor bar in which other semiconductor regions forming other quantum dots each controlled by a gate are arranged. The second lower semiconductor region 102R may be a region of a second lower semiconductor bar located in the same first plane P1 as the first lower semiconductor bar and in which other semiconductor regions forming other detection islands each controlled by a gate are arranged. Similarly, the second upper semiconductor region 104R may be formed in a second upper semiconductor bar in which other semiconductor regions forming other detection islands each controlled by a gate are disposed. A partial perspective view given in
The first and second lower and upper semiconductor bars all extend in a first direction (direction orthogonal to the plane of
As can be seen from the exemplary embodiment illustrated in
Gates GI3, GS3 of a third group of superimposed gates, juxtaposed with the first group of superimposed gates GI1, GS1 (
Advantageously, the device can be further provided with dopant reservoirs DT1 and DT2 at the ends of the lower and upper rows of quantum dots and detection islands. These dopant reservoirs can be in the form of blocks, typically of doped semiconductor material, for example phosphorus-doped silicon or boron-doped silicon germanium. In the particular exemplary embodiment illustrated, each block forming a dopant reservoir DT1, DT2 is connected to one end of the set of semiconductor bars.
Advantageously, exchange electrodes GE11, GE12, GE22 also referred to as “exchange gates” can be provided in inter-gate spaces. In the particular exemplary embodiment of
The exchange electrodes GE11, GE12 mainly extend in a direction parallel to that in which the gates GI1, GS1, GI3, GS3 extend and which is preferably orthogonal to the first direction (the first direction being parallel to the axis y), in other words to the direction in which the semiconductor bars accommodating the detection islands and quantum dots extend. Each exchange electrode is typically separated from adjacent gates via an insulating spacer layer 33.
The arrangement of the exchange electrodes GE11, GE12 can be similar to that of the gates GS3, GI3 or GS1, GI1, so that an upper exchange electrode GE12 is disposed above a lower exchange electrode GE11 and insulated from this lower exchange electrode GE11 by the insulating layer an insulating separation layer CSI. The exchange electrodes achieve charge exchanges between neighbouring quantum dots or between neighbouring detection islands distributed along one and the same semiconductor bar. Thus the exchange electrode GE11 enables charge exchange between a first lower semiconductor region controlled by the gate GI1 and a lower semiconductor region controlled by the gate GI3 and located on one and the same semiconductor bar as the first lower semiconductor region.
The implementation of exchange electrodes is optional, in particular when the pitch Δ of the gates is small, for example less than 40 nm. In this case, some of the gates can be used to control exchange between adjacent quantum dots or detection islands of one and the same semiconductor portion.
Thus, in an alternative embodiment illustrated in
In
In either of the exemplary embodiments just given, the device comprises two levels or stages N1, N2 of quantum dots and detection islands. However, the quantum device is not limited to this number and can integrate a higher number k (with k>2) of stages. Thus, more generally, a quantum device as implemented according to the invention can comprise a number of superimposed semiconductor region stages greater than two.
As an alternative to either of the previously described exemplary embodiments in which horizontal interactions between quantum dot BQ1 (or BQ2) and detection island ID1 (or ID2) are implemented, a device with both horizontal and vertical interactions between different levels of semiconductor regions may be provided. In this case, in particular, the separation zones ZS1, ZS2 illustrated in
The capacitance, which is a measurable value, between 104L and 102L is greater than the capacitance measured between 104L and 104R.
A quantum device as described previously can adapt to different types of reading circuit. For example, it adapts to a transport reading circuit where the quantum state of a quantum dot is read by measuring current in the associated detection island. It also adapts to a reading circuit operating by reflectometry in which an RF signal is emitted in the direction of the detection island and then a reflected RF signal is detected in order to deduce the state of charge of a quantum dot associated with this detection island.
A quantum device as provided according to one or more of the previously described modes can be implemented using a thin-film microelectronic manufacturing method.
A stack of layers formed by alternating layers 101, 103, 105 of a first material 12 and layers 102, 104 of a second material 14 is made on the substrate 5. The materials 12, 14 are typically semiconductor materials different from each other, the first material 12 being able to be etched selectively with respect to the second material 14. The particular exemplary embodiment illustrated in
The layers 101, 103, 105 based on the first material 12 can advantageously be made with a thickness greater than that of the layers 102, 104 based on the second material 14, and which can be, for example, more than twice that of the layers 102, 104. The layers 101, 103, 105 based on the first material 12 can have a thickness e1 of, for example, between 10 nm and 50 nm, while the layers 102, 104 have a thickness e2 of, for example, between 5 nm and 20 nm.
For example, the first material 12 is silicon while the second material 14 is Si1-xGex, with x>0, x being, for example, of the order of 30%. The layers 101, 103, 105, 102, 104 can be made by successive epitaxies.
When the first layer 101 is SiGe, this layer can optionally be formed from a surface layer of silicon on an SOI substrate by a Germanium enrichment method known to those skilled in the art, which consists in performing silicon epitaxy and then carrying out oxidation in order to diffuse germanium. Etching is then implemented so as to remove the oxide formed.
Then (
Gate patterns 25 are then formed from gate material 22 on either side of the structure 16.
For this purpose, first of all at least one layer 21 of at least one gate dielectric is deposited, for example of silicon oxide (SiO2, or formed by a stack of silicon oxide and a high-k material such as for example HfO2. This deposition is followed by that of at least one layer of conductive gate material 22, such as doped polysilicon (
Preferably, after deposition and possible planarisation by CMP, a non-zero thickness e′ of conductive material 22, for example of the order of 50 nm, is left to protrude from the structure 16 of active zone.
Hard masks 31, typically dielectric and for example formed from a stack of SiN and SiO2, are then made (
Then (
After forming the gate patterns 25, dopant reservoirs DT1 and DT2 can advantageously be formed (
According to one method, a thin insulating spacer layer 33 is first conformally deposited on the gate patterns 25 (
Lithography is then carried out so as to remove portions of the thin insulating spacer layer 33 and extend this etching into parts of the structure 16 of active zone located around another part 161 in vertical alignment with the set of gate patterns 25 (
In order to form the dopant reservoirs in contact with the semiconductor layers 102, 104 in which it is intended to form the quantum dots and detection islands without bringing these reservoirs into contact with the other layers 101, 103, 105 of the structure, partial etching of the first material 12 selectively with respect to the second material 14 can advantageously be performed in order to create recesses 41 (
Once the plugs 43 have been made, selective epitaxy of semiconductor material 48 can be performed from the uncovered ends of the layers 102, 104, based on the second material 14. Epitaxy can include in situ doping. For example, dopant reservoirs DT1, DT2 of Si:P or SiGe:B can be epitaxially formed from ends of silicon layers. The epitaxy formed may or may not follow preferred crystalline orientations, and the epitaxial fronts from the different Si layers may possibly meet, as in the exemplary embodiment shown in
Superimposed gates can then be formed.
For this purpose, one method consists first of all in implementing an insulating encapsulation 52 around the gate patterns. Insulating encapsulation 52 can be made, for example, by depositing a PMD-type material (“Pre Metal Dielectric”) such as for example SiO2 over the entire structure, followed by a CMP planarisation step. This step is preferably carried out so that the polishing front stops at the top of the structure 16 of active zone. This enables the material 22 of the gate patterns to be uncovered, typically a conductive gate material such as polysilicon.
Then (
Etching is performed in such a way as to control the height of the lower block 24 of gate material relative to that of the semiconductor layers of the structure 16 of active zone. Partial removal is implemented so that this block 24 for forming a lower gate GI faces only a single layer 102 based on the second material 14, in particular the lower-level semiconductor layer for accommodating quantum dots or qubits.
These cavities 54 are then filled (
A separation trench 65 is then made (
The masking 61 is for example formed from a stack of lithographic resin typically comprising a photosensitive resin formed on a non-reflecting layer itself formed on a so-called “planarising” layer, typically organic and for example of the SOC type (standing for “Spin-On-Carbon”). Etching the trench is typically anisotropic, for example using a fluorocarbon plasma.
According to one particular exemplary embodiment, the width D (dimension measured parallel to the axis x in
In the particular exemplary embodiment in which, rather than being based on an insulating material, a first semiconducting material 12 is used for the layers 101, 103, 105 of the stack on the basis of which the portions 16R, 16L are each formed, it may be provided to replace this semiconductor material 12 with a dielectric material in order to form separation zones between the various levels of layers 102, 104 based on the second material 14.
Thus, in this case, removal of the layers 101, 103, 105 based on the first material 12 is first carried out (
Spaces 71 between regions based on the second material 14 are thus released. The dopant reservoirs (not visible in
This is then filled with a dielectric material 73 to form insulating “separation” zones ZS1, ZS2.
The dielectric material of the insulating zones ZS1, ZS2 is selected in particular in terms of permittivity or dielectric constant of this material depending on whether or not it is wished to favour coupling in the vertical direction (direction parallel to the axis z) between successive semiconductor stages of material 14 in the portions 16A, 16B.
The insulating zones ZS1, ZS2 are typically made by conformal deposition of dielectric material 73 and then anisotropic etching or a combination of anisotropic/isotropic etching(s) of this dielectric material 73 so as to retain this dielectric material 73 only in spaces situated in vertical alignment with the remaining regions of the semiconductor layers 102, 104 based on the second material 14 (
The dielectric region RD is then formed (
For this, a conformal deposition of dielectric material 85 and then a CMP planarisation of this dielectric material 85 are typically performed so as to fill the remaining empty volume forming a reduced trench 75 separating the two portions 16R, 16L. Two sets of semiconductor regions facing each other are then separated by this dielectric material 85. Here again, the dielectric and its permittivity are selected so as to promote or not promote coupling in the horizontal direction (parallel to the axis x) between the two arrays of semiconductor regions facing each other.
In the exemplary method embodiment just given, for the implementation of superimposed gates GI, GS, lower gates GI formed from the same material 22 as the upper gates GS are provided. Alternatively, it is however possible to provide different materials between the lower gates GI on the one hand and the upper gates GS on the other hand.
Likewise, in the exemplary embodiment just given, the gates formed against the portion 16R of active zone dedicated, for example, to accommodating quantum dots are based on the same material as those located against the portion 16L of active zone facing it and which is dedicated, for example, to accommodating detection islands.
Alternatively, it is however possible to provide different materials between the gates located against the portion 16R on the one hand and the gates located against the portion 16L on the other hand. Such an alternative can be made to obtain different output works and consequently different operating regimes between, for example, gates controlling quantum dots and gates controlling detection islands. To implement such an alternative, one or more lithography steps and one or more additional deposition steps may be provided.
As an alternative to the exemplary method embodiment just given for the implementation of the superimposed gates GI, GS, which describes an approach of the type commonly referred to as “gate-last” in which at least partial replacement of patterns is carried out with a stack having gates separated by an insulation zone, it may be envisaged making this stack directly.
Thus, according to one alternative embodiment of the gates, a “gate-first” approach can be provided. In this case, directly after the step of forming the structure 16 of active zone described previously in connection with
In either of the exemplary embodiments just described, contact on different gate levels as well as on different semiconductor layer levels can be made, for example, by providing a staircase shape at the ends of the gate structures or portions of active zone.
In a quantum device as described previously, where horizontal interactions are promoted (in other words in directions parallel to the main plane of the substrate) between, on the one hand, a quantum dot BQ1 (and respectively BQ2) and, on the other hand, a detection island ID1 (and respectively ID2) located in the same horizontal plane as this quantum dot BQ1 (and respectively BQ2), a so-called “diagonal” coupling in a diagonal direction DIAG1 (and respectively DIAG2) between a quantum dot BQ1 (and respectively BQ2) and a detection island ID2 (and respectively ID1) located in a different plane to this quantum dot BQ1 (and respectively BQ2) can furthermore be wished to be avoided.
Thus, in an exemplary embodiment illustrated in
An exemplary method for making this type of device is illustrated in
A structure as described in connection with
The dielectric material 241, for example such as SiN or HfO2, is then partially removed (
Another dielectric material 243 is then deposited, typically with a dielectric permittivity lower than the dielectric permittivity of the dielectric material 241 (
An optional planarisation by CMP of this other material 243 is then performed.
In the particular exemplary embodiment illustrated in
The dielectric material 241 can then be deposited again to form an upper portion 246 of the dielectric region RD (
Alternatively, the upper portion 246 may be formed from a third dielectric material different from that of the portions 242, 244 but with a dielectric permittivity higher than the dielectric permittivity of the dielectric material 243 of the central portion 244.
Another example of making a dielectric region RD heterogeneous in terms of dielectric material composition is given in
The dielectric region RD is here formed by a dielectric material 305 having a dielectric constant k1 cladding each of the first and second lower and upper semiconductor regions 102R, 102L, 104R, 104L, so as to form lower insulating envelopes 308R, 308L against the first and second lower semiconductor regions 102R, 102L and upper insulating envelopes 309R, 309L against the first and second upper semiconductor regions 102R, 104R.
An insulating space formed between the insulating envelopes 308R, 308L 309R, 309L is here filled in by a dielectric material 303 having a second dielectric constant k2 lower than the dielectric constant k1 of the dielectric material 305. A central portion 344 of dielectric material 303 is thus provided to prevent “diagonal” coupling between the semiconductor regions 102L and 104R, and between the semiconductor regions 102R, 104L.
An example method for making this type of device is illustrated in
A structure as described in connection with
First of all (
This space 302 is then filled with a given dielectric material 303 having a given dielectric constant k2, for example SiO2 (
Selective removal of the semiconductor envelope 301 based on sacrificial material 312 is then carried out (
The galleries 304A, 304B are then filled with a dielectric material 305 of dielectric constant k1, for example SiN or HfO2 or Al2O3. In particular, an ALD (Atomic Layer Deposition) method can be implemented to avoid any filling defects (
According to a variant embodiment (
To implement such an alternative, a structure as obtained previously and described in connection with
Another exemplary method for making the dielectric region RD between the two portions 16A, 16B of active zone is illustrated in
This time, a structure of the type described in connection with
The sacrificial semiconductor envelope 301 is then first of all formed (
The dielectric material 303 with dielectric constant k2, for example SiO2, is then deposited (
Next, the selective removal of the sacrificial semiconductor envelope 301 based on the first material 12 is implemented (
The galleries 304A, 304B are then filled with a dielectric material 305 of dielectric constant k1, for example SiN or HfO2 or Al2O3, advantageously as a deposition method of the ALD type in order to avoid a filling defect (
As with the exemplary embodiment described previously, the dielectric material 303 of dielectric constant k2 can again optionally then be selectively removed (
As an alternative to either of the above exemplary methods that have just been described, it may be envisaged making exchange electrodes in inter-gate spaces.
For this, a method illustrated in
After removing the masking 410, depositing a conductive material 416, for example a TiN/W type stack, is performed to fill the holes 414 thus defined (
Alternatively, however, it is possible to form superimposed exchange gates which have an arrangement similar to that of the gate electrodes between which these exchange gates are sandwiched. In each inter-gate space, pairs of superimposed exchange gates separated from each other by an insulator can thus be formed. For this, a method similar to that used to make the gates and described previously in connection with
In a variant embodiment, a dielectric region RD is provided between the set of semiconductor regions 102R, 104R and the set of semiconductor regions 102L, 104L with a heterogeneous composition this time making it possible to establish coupling between the first lower semiconductor region 102R and the second upper semiconductor region 104L and between the second lower semiconductor region 102L and the first upper semiconductor region 104R, while preventing coupling between the first lower semiconductor region 102R and the second lower semiconductor region 102L and preventing coupling between the second upper semiconductor region 104L and the first upper semiconductor region 104R.
A particular embodiment of this variant is illustrated on
An example method for making this type of device is illustrated in
In the particular exemplary embodiment illustrated in
In a variant, the upper portion 2446 may be formed from a third dielectric material different from that of the portions 442, 444 but with a dielectric permittivity lower than the dielectric permittivity of the dielectric material 443 of the central portion 444.
In another variant embodiment illustrated in
A central dielectric portion 494 is here interposed between a first dielectric portion 492 and a second dielectric portion 496 with respective compositions different from that of the central dielectric portion 494. The central dielectric portion 494 is made from a given dielectric material 493 having a first dielectric constant, for example HfO2 or SiN, while the first dielectric portion 492 and the second dielectric portion 496 are based on at least one dielectric material, for example SiO2, different from said given dielectric material and with respective dielectric constants lower than that of said given dielectric material. For this variant, an electrostatic coupling can be established between superimposed semiconductor regions 102L and 104L or 102R and 104R of one and the same set, while preventing such coupling between semiconductor regions of distinct sets, in other words between distinct superimpositions of semiconductor regions.
| Number | Date | Country | Kind |
|---|---|---|---|
| FR2315160 | Dec 2023 | FR | national |
