Patent Application
20230163238
The present disclosure generally relates to light emitting structures, such as light emitting diodes (LEDs) used in various types of displays and other devices.
The number of light emitting elements (e.g., pixels) in displays continues to increase to provide better user experiences and to enable new applications. However, increasing the number of light emitting elements is challenging from both a design perspective and a manufacturing perspective. Reducing the size of light emitting elements enables an increased density of such light emitting elements in a device. However, effective and efficient techniques for making smaller light emitting elements in large numbers and high densities are not widely available. For example, it is challenging to manufacture smaller light emitting diodes (LEDs) and incorporate such LEDs into increasingly sophisticated display architectures with stringent requirements for performance and size. Additionally, improvements are needed in light emitting characteristics of light emitting elements for full color display applications.
Accordingly, techniques and devices are presented herein that enable effective and efficient design and fabrication of light emitting elements and improved operation of the light emitting elements.
The present disclosure describes aspects of semiconductor light emitters that provide for light emission over a full visible spectrum with improved efficiency. In some implementations, the disclosed aspects may be included in micro-scale light emitting diodes (microLEDs). In some implementations, the aspects may be applied in microLED displays including one or more arrays of microLEDs, such as used in augmented reality (AR) and virtual reality (VR) displays, head-mounted displays, head-up displays, image projectors, and light field displays. For instance, aspects described herein can enable applications of LED technology and display technology that maintain high efficiency at reduced device sizes.
In a general aspect, an LED structure may include regrown p-type layers and have a mesa structure formed on a substrate. The mesa structure may include preparation layers, an active multiple quantum well (MQW) structure, a first electron blocking layer (EBL), and one or more first p-type layers stacked in a c-plane direction. The sidewalls of the mesa may be substantially vertical or may exhibit a sloped profile. A second EBL may be conformally deposited over the mesa structure, followed by one or more second p-type layers deposited over the conformal second EBL layer. The second EBL and/or second p-type layer(s) deposited over the mesa structure may be referred to herein as regrown layers.
In another general aspect, an LED structure may include regrown p-type layers including preparation layers and/or hole blocking layer(s) (HBL) above which (on which) a mesa structure is grown. The mesa structure may include additional preparation layers, active quantum wells (e.g., MQWs), a first EBL, and first p-type layer(s), such as a p GaN layer. A second EBL may be conformally deposited above the mesa structure. One or more second p-type layers, such as a p or p+ GaN layer, may be grown on the sidewalls of the mesa structure.
In another general aspect, an LED structure may include regrown p-type layers formed above the top (on an upper surface) of a mesa structure, a surface of a field, and/or along sidewalls of the mesa structure. Process conditions for forming the regrown p-type layers may be selected such that layer thicknesses of the p-type layer are different on the top of the mesa, the surface of the field, and the sidewall of the mesa structure.
As discussed above, increasing number of light-emitting structures, elements, and pixels in light devices or displays may improve user experience and enable new applications. However, it is challenging to increase the number of light-emitting elements or the density of light emitting elements. A reduction in the size of light emitting structures, which enables an increase in both count and density of the light emitting structures within a device, makes the potential use of small LEDs, such as microLEDs or nano emitters, more attractive. However, the currently available techniques for making small LEDs in large numbers, high densities, and capable of producing different colors (e.g., red, green, blue) are cumbersome, time consuming, costly, or result in structures with performance limitations. For instance, the manufacture of a tricolor array of LEDs may involve separate formation of multiple LEDs of a single color (e.g., red only, green only, blue only) on a substrate, then transferring each LED onto a display substrate with the LEDs of various colors placed in tricolor arrays. This transfer process, sometimes referred to as “pick and place,” can lead to inaccuracies in the positioning of the LEDs with respect to each other and requires each LED be of a certain minimum size (e.g., several microns or larger in dimensions) for proper handling. Accordingly, new techniques, devices, or structural configurations that enable the formation of small light emitting structures with high quality active (e.g., emitting) regions are needed.
The present disclosure describes aspects of semiconductor light emitters that enable light emission with improved efficiency. The aspects presented herein enable applications of LED technology that maintain high efficiency at reduced light emitting device sizes. In some examples, the light emitters may have a size on a micron scale or even a sub-micron scale.
As one example, III-nitride LEDs may be incorporated into a lighting or display system to cover a wide portion of the visible spectrum of light. However, the efficiency of the light emitters may drop for the emission of longer wavelengths (e.g., in the red wavelengths) and/or for smaller sizes of individual light emitters due to, for example, sidewall surface degradation, epitaxial growth issues, reduced volume of light-emitting materials which are more susceptible to non-radiative processes with high carrier concentrations at desired brightness, and/or non-uniform distribution of holes throughout an LED's quantum well structure, leading to asymmetric carrier concentrations across the active quantum well region of the light emitter.
While preparation layer 120, active QW structure 130, and p-type layer 140 are shown in
Substrate 110 may be, for example, a semiconductor substrate, a non-semiconductor substrate prepared with one or more semiconductor layers, such as a sapphire substrate coated with a gallium nitride layer, or a semiconductor template formed using semiconductor epitaxy. Preparation layer 120, for example, may include one or more layers and act as a transitional layer providing surface step and/or morphology to improve the material characteristics of active QW structure 130 grown on preparation layer 120, as compared to an LED structure where active QW structure 130 is grown directly on substrate 110.
As shown in
In the examples of this disclosure, a substrate may be n-doped, a preparation layer may be undoped or n-doped, and/or an active QW structure may be n-doped, p-doped or undoped.
In example implementations, light emission characteristics of active QW structure 130 depends on injection of holes from p-type layer 140 into active QW structure 130 through a c-plane surface 139 in a c-plane direction 150 for a III-nitride light emitter. In example implementations, c-plane direction 150 is parallel to a surface normal 160 defined with respect to a plane of the surface of substrate 110. As shown in
Aspects of a microLED and/or nano-LED structure are presented herein that enable higher efficiencies at a broader range of wavelengths, as well as a broader range of current densities as additional quantum wells can be incorporated into the active light emitting region, through a light emitting structure configured for sidewall hole injection of one or more quantum well layers. For example, the aspects described herein may improve efficiency at longer wavelengths of light emission. It is noted that the device configurations and techniques disclosed herein may be applicable to any semiconductor QW structures and devices.
In the example implementation shown in
In some implementations, preparation layer 220 may be formed on substrate 110 such that one or more surfaces of preparation layer 220 are parallel to top surface 119, as shown in
In this example, because InGaN alloys have a lower bandgap than GaN, with a higher In concentration corresponding to a lower bandgap, a desired wavelength may be achieved by selecting a desired In % concentration. For instance, an In % concentration may be at least 10% (or at least 15%, or at least 20%, or at least 25%, or at least 30%). In some implementations, In % concentration may be in a range of 10-20% (or in a range of 15-25%, or in a range of 20-30%, or in a range of 25-35%, or in a range of 30-40%). In some examples, InGaN may also be used in the preparation layers. In such implementations, an In % concentration in the preparation layers may be lower than an In % concentration in the QWs. For instance, In % concentration in the preparation layers may be in a range 0-5%, or in a range of 0-10%, or in a range of 2-8%, or in a range of 1-10%.
Still referring to
In the example of
In the LED structure 200 of
In some implementations, preparation layer 220 may include InGaN layers with a lower In % composition than active QW structure 230, such that hole injection into preparation layer 220 is not significant. For instance, a voltage necessary for hole injection into preparation layer 220 may be at least 3V, and the LED structure 200 may be operated a voltage below 3V (or below 2.7V, or below 2.5V, or below 2.2V).
In some examples, at least 80% (or at least 90%, or at least 99%) of a hole current may be injected into active QW structure 230. This injection may be lateral, vertical, or both lateral and vertical. That is, in example implementations described herein, there may be direct contact between p-type regions and n-type regions surrounding an active QW structure, but preferential current injection in the active QW structure.
Sidewall hole injection also allows for an increased number of QW/QB pairs within active QW structure 230 (or other active QW structures described herein), as well as an increase in a thickness of each corresponding QB layer (e.g., of a QW layer and QB layer pair), as is discussed in further detail below. That is, sidewall hole injection allows more uniform distribution of holes throughout an entire set of QW layers within active QW structure 230, even with increased numbers of QW/QB layers and thicker QB layers, leading to improved LED light emission performance as well as additional device design and epitaxial growth structure flexibility. For instance, with sidewall hole injection, tens of QW/QB combination layers (pairs) can be incorporated into LED structure 200, thus providing extended design options for emission of light over a wider range of wavelengths than previously possible. Also, each QB layer can have a thickness of 50 nm or greater (or 30 nm or greater, or 20 nm or greater, or 10 nm or greater, or 8n m or greater, or 6 nm or greater), with more uniform distribution of holes throughout active QW structure 230 and without a reduction in EQE characteristics of LED structure 200. Increased thickness of each QB layer may help to improve, for example, strain balance and growth morphology for the overall active QW structure 230. A QB may include several layers, including layers of GaN, layers of InGaN, and layers of AlGaN (with an Al % composition of at least 10% (e.g., at least 20%, 30%, 40%, 50%)) or even AlN. Further, a p-contact 260 is formed on p-type layer 250 to provide electrical contact to LED structure 200. P-contact 260 is formed, for example, of a metal, metal alloy, a transparent conductor, and/or other conductive material compatible with p-type layer 250.
Active QW regions may be characterized by one or more of following aspects, alone or in combination, which may be facilitated by lateral injection. For instance an active QW region (active QW structure) can have a plurality of quantum wells (e.g., at least 4, or at least 6, or at least 8, or at least 10, or at least 12, or at least 14, or at least 16, or at least 18, or at least 20). An active QW region can operation with efficient lateral injection of holes into a plurality of QWs, with at least 4 (e.g., at least 6, or at least 8, or at least 10, or at least 12, or at least 14, or at least 16, or at least 18, or at least 20) QWs being laterally injected with holes. An active QW region can include thick barrier layers (e.g., quantum barrier (QB) layers) between respective quantum wells. These barrier layers can have a thickness of at least 6 nm (e.g., at least 8 nm, or at least 10 nm, or at least 15 nm, or at least 20 nm). Such barrier layers may include at least one GaN layer, and/or at least one AlGaN layer, where the Al % concentration is at least 10% (e.g., at least 20%, at least 30%, at least 40%, at least 50%). QWs of an active QW region can operate (emit light at a desired wavelength) at an operating voltage less than V0+1V (e.g., less than V0+0.5V, less than V0+0.3V) where V0=1240/lambda (where lambda is a peak emission wavelength), measured at a current density of at least 1 A/cm2 (e.g., at least 10 A/cm2, at least 100 A/cm2). A peak emission wavelength (lambda) may be at least 590 nm (e.g., at least 600 nm, at least 610 nm, at least 620 nm, at least 630 nm) at a current density of at least 1 A/cm2 (e.g., at least 10 A/cm2, at least 100 A/cm2).
In an example implementation, an LED structure can have six or more quantum wells each emitting light at a wavelength lambda, at a current density of at least 1 A/cm2, where lambda is at least 600 nm; The six or more quantum wells may be separated by quantum barriers (QBs) having a thickness of at least 6 nm. The LED structure can also include p-layers disposed on the sidewalls of the LED structure, where the p-layers and the QWs are arranged to facilitate sidewall injection of holes into the quantum wells from the p-layers, thus facilitating an operating voltage lower than V0+0.5V (where V0=1240/lambda) and an operating current density of at least 1 A/cm2.
Further modifications to LED 200 are possible. For example, EBL 240 may be omitted in some implementations. Additionally, p-contact layer 260 may be conformally wrapped over the vertical sides of p-type layer 250, as is discussed further below. Still further, preparation layer 220 or equivalent materials promoting favorable growth conditions for active QW structure 230 (e.g., lattice matching, adhesion, and/or defect control) may be incorporated into substrate 110.
In some aspects, one or more additional hole blocking layers can be incorporated into the LED structure for prevention of hole migration into the preparation layer, which may improve hole injection efficiency into a corresponding active QW structure. Two examples of LED structures including hole blocking layers are respectively illustrated in
As shown in
In the example of
As with other implementations described herein, p-type layer 550 facilitates hole injection into QW layers 534 in a direction other than c-plane direction 150, thus leading to greater uniformity in hole injection into, and hole migration through active QW structure 530. Consequently, implementations of LED structure 500 may exhibit improved EQE and light emission improvement over LED devices without a device architecture which enables sidewall hole injection.
Such regrown layers adjacent to the sidewalls of the mesa structure enables hole injection into a larger volume of the active MQW structure. Such an effect may provide improved brightness of light emission from the resulting LED structure, as well as the ability to tune the brightness of the light emission by adjusting hole injection through modification of respective thicknesses and materials used in the regrown p-type layers. Further, as the sidewalls of the mesa structures, and the active MQWs in particular, do not have exposed QW materials (e.g., InGaN layers), the use of regrown p-type layers allows greater flexibility in device size and perimeter-to-area ratio of the LED. This factor may be particularly beneficial for microLED devices with dimensions on the order of a few microns or even a fraction of a micron. In some implementations, a micro-LED mesa may have a lateral dimension in a range 1-10 um (or in a range of 1-3 um, or in a range of 1-5 um, or in a range of 2-20 um). Additionally, by decoupling the QW design from the p-side stack design, as used in traditional MQW designs relying on hole injection in the c-plane direction, greater flexibility may be obtained in designing the active QW region and p-type layers of the LED. For instance, the last barrier, e.g., at a top of an active MQW structure, in the MQW and EBL composition and thickness can be modified with greater flexibility due to the availability of efficient sidewall hole injection through the regrown p-type layers.
While mesa structure 801 is shown in
In contrast to LED structure 200 illustrated in
In some implementations, the p-type layers may include several portions. For instance, a first portion may be positioned above the active QW region, and a second portion and/or third portion may be positioned on respective sidewalls of the LED structure. The first portion and the second portion (and third portion) may be in direct contact with each other, allowing flow of holes between the various portions. Each portion may include p-GaN, p-AlGaN and/or other p-type layers. The first portion may enable vertical injection of holes into the active QW region. For instance, in some implementations, the first portion may be configured to limit, or suppress, injection of holes. The second portion may enable (facilitate, etc.) lateral injection of holes into the active QW region. The second portion may be in contact with the substrate (or template), or with a planar layer grown on the substrate (e.g., a preparation layer, a hole blocking layer, an n-doped layer, etc.). A p-contact may be formed on the first portion and/or on the second portion.
As a further variation, in the structure illustrated in
As used herein, a p+ layer refers to a highly p-doped layer. For instance, p-doping of GaN and III-nitrides may be achieved, e.g., using Mg or Ge doping. In example implementations, p-type doping with Mg may be Mg in a range 1e18 cm−3 to 5e19cm−3,, while p+ doping with Mg may be in a range 5e19cm-3 to 1e21cm−3. In the example of
Various modifications to the exemplary LED structure shown in
As illustrated in
The example process illustrated in
In some implementations, mesas 1001 are formed and regrown p-layers 1010 are grown on mesas 1001. The resulting LED emits light at a first wavelength. An etch to form regions 1015 is then performed. Selective area growth of mesa 1110 is then performed (e.g., to form mesas in regions 1015. The resulting second LED may emit light at a second wavelength. Optionally, a second etch is performed (e.g., to define additional regions 1015, and a second selective area growth of one or of mesa 1110 is performed. The resulting third LED may emit light at a third wavelength. The wavelengths of the various LED structures may respectively correspond to red, green, and blue light (in any combination respective to the first, second, and third wavelengths). For instance, a first wavelength is red, a second wavelength is green, and a third wavelength is blue, thought other wavelength combinations are possible.
The regrown p-layers further enable configurations of microLED arrays that were not previously achievable. The regrown p-layers enable sidewall injection of holes in regions unavailable via hole injection in the c-plane direction alone. For instance, each mesa structure may include two or more active MQW structures, each active MQW structure corresponding to a different emission wavelength from other active MQW structures, and one or more of the active MQW structures may be enhanced by sidewall and/or c-plane hole injection.
As an example, an array of LED mesa structures with like construction may first be formed, with each mesa structure including two or more active MQW structures for different wavelength light emission. Then, by performing masked pattern and etch or other processes for facilitating regrowth of p-type layers over the mesa structures, a patterned formation of regrown p-type layers may be formed to enhance different active QW structures within each mesa structure in the array, thus resulting in an interlaced array of LED structures respectively emitting light at multiple different wavelengths from the uniform array of mesa structures.
As shown in
As shown in
In particular, as shown in
In the example LED structures of
In some implementations, active layers (e.g., of an active QW structure) may be characterized by a first band gap Eg1, and be part of a first p-n junction whose turn-on voltage is approximately Eg1/eV. Other portions of the LED (e.g., an interface between substrate 1005 and p-layers 1010) may form a second p-n junction characterized by a second band gap Eg2. Eg1 may correspond to InGaN (e.g., Eg1 is less than 3 eV, less than 2.8 eV, less than 2.6 eV, less than 2.4 eV, less than 2.2 eV, less than 2 eV). Eg2 may correspond to GaN (e.g., where Eg2 is about 3.4 eV) or may generally be higher than at least Eg1 plus 0.1 eV (or Eg1 plus 0.2 eV). Each p-n junction can be operated at a voltage that is roughly equal to its corresponding band gap (divided by eV). Therefore, by operating the LED at a voltage of about Eg1/eV, the first p-n junction corresponding to the QWs is turned on while the second p-n junction is not.
As shown in
The substrate with the mesas formed thereon may then be loaded into equipment configured for regrowth of the p-type layer(s) thereon. In operation 1930, the substrate with the mesas formed thereon may be subjected to one or more in-situ process, such as one or more chemical and/or thermal treatment processing steps. Such processing steps may include, without limitation, a wet chemical treatment (e.g., wet etch, acid treatment, base treatment, organic treatment, etc.), a dry or gas-phase chemical treatment (e.g., dry etch, a reactive ion etch (RIE), an inductively coupled plasma (ICP) etch, a flow of a gas, etc.), a thermal treatment (e.g., at a temperature above 100 C, or above 300 C, or above 500 C, or above 700 C, or above 900 C, or above 1100 C), and/or combinations of such steps (e.g., wet etch above a certain temperature, flow of a gas above a certain temperature).
In operation 1940, an initial growth layer for a regrowth interface is formed on the mesa structure and/or substrate. In some implementations, operation 1940 can be omitted. This initial growth layer may be, for example, a GaN or other material compatible with the materials included in the mesa structures and the subsequent one or more p-type layers (including p type and/or p+ type) grown thereon to enhance the material quality of the regrown p-type layers in subsequent operations. Such an initial growth layer may be an electron blocking layer, hole blocking layer, preparation layers, and the like.
Still referring to
While many of the mesa structures illustrated above have been shown with vertical sidewalls, in some implementations, the mesa structures themselves may have sloped sidewalls, as shown, for example, in
The foregoing is illustrative of example implementations and is not to be construed as limiting. Although a number of example implementations have been described, those skilled in the art will readily appreciate that many modifications are possible in the example implementations without departing from the teachings and advantages of the implementations described herein. For example, a variety of mesa structures and methods of manufacture thereof can be used in accordance with embodiments described herein.
Accordingly, many different implementations may stem from the above description and drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and sub-combination of these implementations. As such, the present description and associated drawings shall be construed to constitute a complete written description of all combinations and sub-combinations of the implementations described herein, and of the manner and process of making and using them, and shall support claims to any such combination or sub-combination.
For example, in the illustrated embodiments, various layers may be omitted, replaced or added For instance, in
A number of implementations are described below as Examples, and are provided for purposes of illustration. In some implementations, variations of the described Examples are possible, and can include a number of variations and modifications in accordance with the details and aspects of this disclosure.
Example 1: An LED structure including regrown p-type layers includes a mesa structure formed on a substrate. The mesa structure may include preparation layers, active multiple quantum well (MQW) structure, a first electron blocking layer (EBL), and one or more first p-type layers stacked along a c-plane. The sidewalls of the mesa structure may be substantially vertical or may exhibit a sloped profile. A second EBL maybe conformally deposited over the mesa structure, followed by one or more second p-type layers deposited over the conformal second EBL layer. The second EBL and/or second p-type layer(s) deposited over the mesa structure may be regrown layers.
Example 2: The LED structure of Example 1, where the mesa structure is formed as a standalone structure using techniques such as selective area growth.
Example 3: The LED structure of Example 1, where the mesa structure is formed by applying wet and/or dry etch processes to a multilayer planar structure.
Example 4: An LED structure including regrown p-type layers. The LED structure may include one or more preparation layers, and/or one or more hole blocking layers (HBLs), on which a mesa structure is formed. The mesa structure may include additional preparation layers, multiple active quantum wells (e.g., MQWs), a first EBL, and first p-type layer(s), such as a p-GaN layer. A second EBL may be conformally deposited over the mesa structure. One or more second p-type layers, such as a p or p+ GaN layer, may formed on the sidewalls of the mesa structure.
Example 5: The LED structure of Example 4, where the second p-type layer on the sidewalls is vertically terminated or grown in a sloped manner. A slope of the second p-type layer growth may be varied by adjusting growth conditions of the p or p+ GaN layer and/or with additional material formed over the second EBL.
Example 6: An LED structure including regrown p-type layers includes an n-AlGaN layer formed on a substrate. A preparation structure, such as a bulk layer and/or a superlattice of multiple layers, may be formed on the n-AlGaN layer. Active quantum wells may be formed on the preparation structure, followed by a first EBL, a first p-GaN layer, and a first p+ layer to form a mesa structure. A second EBL may be conformally formed over the mesa structure, followed by a second p-GaN layer and a second p+ layer.
Example 7: An LED structure including regrown p-type material (one or more p-type layers) formed above a defined mesa structure. The LED structure includes an electron blocking layer (EBL), a p-type layer, and a p+ layer. The p-type layer may include p-GaN.
Example 8: An LED structure including regrown p-type layers formed on the top of a mesa structure, a field, and/or along sidewalls of the mesa structure. Process conditions for forming the regrown p-type layers may be selected such that layer thicknesses of the p-type layer are different on the top of the mesa structure, the field, and the sidewall of the mesa structure.
Example 9: The LED structure of Example 8, where respective layer thicknesses of the regrown p-type layers on the top of the mesa structure, the field, and the sidewall of the mesa structure are substantially the same.
Example 10: The LED structure of Example 8, where a layer thickness of the regrown p-type layers along the sidewall of the mesa structure is greater than respective layer thicknesses of the regrown p-type layers on the top of the mesa structure and on the field.
Example 11: The LED structure of Example 8, where a layer thickness of the regrown p-type layers on the top of the mesa structure is greater than respective layer thicknesses of the regrown p-type layers along the sidewall of the mesa structure and above the surface of the field.
Example 12: The LED structure of Example 8, where respective layer thicknesses of the regrown p-type layers on the top of the mesa structure and above the field are greater than a layer thickness along the sidewall of the mesa structure.
Example 13: The LED structure of Example 8, wherein respective layer thicknesses of the regrown p-type layers on the top of the mesa structure and along the sidewall of the mesa structure are greater than a layer thickness on the field.
Example 14: A method for forming LED structures including regrown p-type layers may include the following. For instance, the method may include forming mesa structures on a substrate. The method may further include subjecting the mesa structures to ex-situ and/or in-situ chemical and/or thermal processing.
Example 15: The method of Example 14, where the method may further include loading the substrate, with the mesas formed thereon, into equipment configured for forming one or more regrown p-type layers.
Example 16: The method of Example 14, where the method may further include forming an initial growth layer for a regrowth interface over the mesas and/or substrate.
Example 17: The method of Example 16, where the initial growth layer can be at least one of a GaN layer or other material compatible with the mesa structures and the regrown p-type layers to enhance material quality of the regrown p-type layers.
Example 18: The method of Example 14, where the regrown p-type layer may include one layer or a multi-layer stack.
Example 19: The method of Example 14, where the regrown p-type layer may include at least one of an EBL, a p-type layer, and/or a p-contact layer.
Example 20: The method of Example 19, where the regrown p-type layer may be formed as a combination of different layers of (In, Al, GaN).
Example 21: The method of Example 19, where deposition conditions of the regrown p-type layer may be selected to obtain respective desired layer thickness profiles.
Example 22: The method of Example 19, where the method may further include subjecting the substrate, with the mesas formed thereon, to further device fabrication processes to form fully functional LED devices.
Example 23: The method of Example 22, where device fabrication processes include at least one of bonding, hybrid bonding, encapsulation, and/or optical integration.
Example 24: A device with a mesa containing multiple QWs, a first p-material located on top of a mesa and a second p-material located on the sidewalls of the mesa, where preferential injection of holes into the QWs occurs from the second p-material. For instance, at least 90% (or 99%) of the hole current may flow from the second p-material to the multiple QWs.
Example 25: A method of forming or configuring the device of Example 24 to achieve preferential hole injection from the second p-material.
Example 26: The device of Example 24, where a hole blocking layer (or an n-doped layer containing AlGaN) is formed between the first p material and the multiple QWs. to facilitate a reduction in hole injection from the first p-material to the QWs.
The detailed description set forth above in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well known components are shown in block diagram form in order to avoid obscuring such concepts.
As used in this disclosure, the term “light emitting structure” and “light emitting element” may be used interchangeably, where the term “light emitting structure” may be used to describe a structural arrangement (e.g., materials, layers, configuration) of a single component configured to produce light of a particular color, and the terms a “light emitting element,” “light emitter,” or simply “emitter” may be used to more generally refer to the single component.
It is noted that as used herein and in the claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a layer” includes two or more layers, and so forth.
Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range, and any other stated or intervening value in that stated range, can be included in implementations described herein. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges, and may also be included in implementations described herein, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits may also be included. Where the modifier “about” or “approximately” is used, the stated quantity can vary by up to 10%. Where the modifier “substantially equal to” or “substantially the same” is used, the two quantities may vary from each other by no more than 5%.
The term “horizontal” as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term “vertical” will refer to a direction perpendicular to the horizontal as previously defined. Terms such as “above”, “below”, “bottom”, “top”, “side” (e.g., sidewall), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact between the elements. The term “above” will allow for intervening elements.
The term “substrate” as used herein may refer to any workpiece on which formation or treatment of material layers is desired. Substrates may include, without limitation, silicon, gallium nitride, indium gallium nitride, silica, sapphire, silicon carbide, aluminum nitride, indium nitride, and combinations (or alloys) thereof. The term “substrate” or “wafer” may be used interchangeably herein. Semiconductor wafer shapes and sizes can vary and include commonly used round wafers of 50 mm, 100 mm, 150 mm, 200 mm, 300 mm, or 450 mm in diameter.
Terms such as “grown,” “formed,” and “deposited” may be used to describe the formation of one or more layers above a substrate and will be considered to be interchangeable, regardless of the deposition technique employed.
Those skilled in the art will appreciate that each of the layers discussed herein may be formed using any common formation technique such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PE-ALD), atomic vapor deposition (AVD), ultraviolet assisted atomic layer deposition (UV-ALD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), epitaxial growth (EPI), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). Generally, because of the complex morphology of the device structure, CVD, MOCVD, or EPI are preferred methods of formation. However, any of these techniques are suitable for forming each of the various layers discussed herein. Those skilled in the art will appreciate that the teachings described herein are not limited by the technology used for the deposition process.
Those skilled in the art will appreciate that each of the layers discussed herein may be patterned using any common technique such as wet chemical etching, reactive ion etching, ion beam etching, or plasma etching. The process parameters of the etch step may be selected such that the etch proceeds in an isotropic manner. The process parameters of the etch step may be selected such that the etch proceeds in an anisotropic manner. Those skilled in the art will appreciate that the teachings described herein are not limited by the technology used for the etch process.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims.
This application claims the benefit of, and priority to U.S. Provisional Application No. 63/299,953, filed on Jan. 15, 2022, and entitled “Quantum Well-Based LED Structure Enhanced with Sidewall Hole Injection” and U.S. Provisional Application No. 63/340,598, filed on May 11, 2022 and entitled “Quantum Well-Based LED Structure Enhanced with Sidewall Hole Injection.” This application is also a continuation-in-part of U.S. patent application Ser. No. 17/324,461, filed on May 19, 2021, and entitled “Quantum Well-Based LED Structure Enhanced with Sidewall Hole Injection,” which claims the benefit of U.S. Provisional Patent Application No. 63/027,069, filed on May 19, 2020, and entitled “Quantum Well-Based LED Structure Enhanced with Sidewall Hole Injection.” The disclosures of each of the foregoing referenced applications are incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 63299953 | Jan 2022 | US | |
| 63340598 | May 2022 | US | |
| 63027069 | May 2020 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17324461 | May 2021 | US |
| Child | 18155681 | US |
