QUASI-RESONANT ISOLATED VOLTAGE CONVERTER

Abstract

A circuit includes a first transistor and a second transistor. The circuit also includes a third transistor and a fourth transistor. Additionally, the circuit includes a switch network coupled to the first transistor, to the second transistor, to the third transistor, and to the fourth transistor. Also, the circuit includes a first buffer having an input and an output, where the output is coupled to the second transistor and a second buffer having an input and an output, where the output is coupled to the first transistor. Additionally, the circuit includes a third buffer having an input and an output, the input coupled to the input of the first buffer and the output coupled to the third transistor; and a fourth buffer having an input and an output, where the input is coupled to the input of the second buffer and the output is coupled to the fourth transistor.

Description

BACKGROUND

A voltage converter is an electrical circuit (e.g., an integrated circuit, “IC”) that receives an input voltage at one voltage level and generates an output voltage typically at a different voltage level. Some voltage converters are isolated converters which include a galvanic barrier between the input and the output. A galvanic isolation barrier lacks a direct electrical connection. One type of galvanic isolation barrier is a transformer, which has two inductors—a primary coil for the input side of the converter and a secondary coil for the output side of the converter—and there is no direct electrical connection between the primary and secondary coils. Isolated voltage converters have a wide variety of applications such as in controller area networks (CANs), power supply start-up bias and gate drives, isolated sensor interfaces, etc.

SUMMARY

In one example, a circuit includes a first transistor having a current terminal and a control terminal and a second transistor having a current terminal and a control terminal. The circuit also includes a third transistor having a current terminal and a control terminal and a fourth transistor having a current terminal and a control terminal. Additionally, the circuit includes a switch network coupled to the current terminal of the first transistor, to the current terminal of the second transistor, to the current terminal of the third transistor, and to the current terminal of the fourth transistor. Also, the circuit includes a first buffer having an input and an output, where the output is coupled to the control terminal of the second transistor and a second buffer having an input and an output, where the output is coupled to the control terminal of the first transistor. Additionally, the circuit includes a third buffer having an input and an output, the input coupled to the input of the first buffer and the output coupled to the control terminal of the third transistor; and a fourth buffer having an input and an output, where the input is coupled to the input of the second buffer and the output is coupled to the control terminal of the fourth transistor.

In an example, a circuit includes a first transistor having a current terminal and a control terminal and a second transistor having a current terminal and a control terminal. The circuit also includes a third transistor having a current terminal and a control terminal and a fourth transistor having a current terminal and a control terminal. Additionally, the circuit includes a fifth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the first transistor and a sixth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the second transistor and the control terminal coupled to the second current terminal of the fifth transistor. Also, the circuit includes a seventh transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the third transistor, the second current terminal coupled to the second current terminal of the fifth transistor, and the control terminal coupled to the control terminal of the fifth transistor and an eighth transistor having a first current terminal and a second current terminal, the first current terminal coupled to the current terminal of the fourth transistor, the second current terminal coupled to the second current terminal of the sixth transistor, and the control terminal coupled to the control terminal of the sixth transistor. The circuit also includes a first buffer having an input and an output, where the output is coupled to the control terminal of the second transistor and a second buffer having an input and an output, where the output is coupled of the control terminal of the first transistor. Additionally, the circuit includes a third buffer having an input and an output, the input coupled to the input of the first buffer and the output coupled to the control terminal of the third transistor and a fourth buffer having an input and an output, where the input is coupled to the input of the second buffer and the output is coupled to the control terminal of the fourth transistor.

In an example, a circuit includes a first transistor having a current terminal and a control terminal and a second transistor having a current terminal and a control terminal. The circuit also includes a third transistor having a current terminal and a control terminal and a fourth transistor having a current terminal and a control terminal. Additionally, the circuit includes a fifth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the first transistor and a sixth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the second transistor and the control terminal coupled to the second current terminal of the fifth transistor. Also, the circuit includes a seventh transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the third transistor, the second current terminal coupled to the second current terminal of the fifth transistor, and the control terminal coupled to the control terminal of the fifth transistor and an eighth transistor having a first current terminal and a second current terminal, the first current terminal coupled to the current terminal of the fourth transistor, the second current terminal coupled to the second current terminal of the sixth transistor, and the control terminal coupled to the control terminal of the sixth transistor. The circuit also includes a first buffer having an input and an output, where the output is coupled to the control terminal of the second transistor and a second buffer having an input and an output, where the output is coupled to the control terminal of the first transistor. Additionally, the circuit includes a third buffer having an input and an output, the input coupled to the input of the first buffer and the output coupled to the control terminal of the third transistor and a fourth buffer having an input and an output, where the input is coupled to the input of the second buffer and the output is coupled to the control terminal of the fourth transistor. Also, the circuit includes a transformer having a first winding and a second winding, the first winding having a first terminal and a second terminal, the first terminal coupled to the second current terminal of the fifth transistor and the second terminal coupled to the second current terminal of the sixth transistor and a rectifier coupled to the second winding of the transformer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a quasi-resonant voltage converter, in accordance with an example.

FIG. 2 is a schematic diagram of a power stage within the quasi-resonant voltage converter of FIG. 1, in accordance with an example.

FIG. 3A is a voltage waveform of the switch nodes within the power stage of FIG. 2 illustrating bridge capacitive imbalance due to the parasitic capacitances.

FIG. 3B is a voltage waveform of the switch nodes within a power stage which reduces the effects of capacitive imbalance, in accordance with an example.

FIG. 4 is a schematic diagram of the power stage of FIG. 2 illustrating parasitic capacitance within the power stage, in accordance with an example.

FIG. 5 is a voltage waveform of the switch nodes within the power stage of FIG. 3 further illustrating bridge capacitive imbalance due to the parasitic capacitances.

FIG. 6 is a schematic diagram of the power stage including additional capacitors to reduce the effects of bridge capacitive imbalance, in accordance with an example.

FIG. 7 is a schematic diagram illustrating the drive circuitry for the power stage of the quasi-resonant voltage converter in accordance, with an example.

DETAILED DESCRIPTION

The example embodiments described herein are directed to a voltage converter. In one example, the voltage converter is an isolated voltage converter including a transformer that isolates a “primary” side from a “secondary” side of the converter. The isolated voltage converter is configured to convert an input direct current (DC) voltage received on the primary side to a different (or the same) DC voltage on the secondary side using the transformer. The primary side includes a power stage that may include a switch network that receives the DC input voltage and produces a time-varying voltage to the primary winding of the transformer. The time-varying voltage on the primary winding of the transformer induces a time-varying current/voltage in the secondary winding of the transformer. The secondary side includes a rectifier to convert the time-varying current/voltage from the secondary winding to an approximately DC output voltage. The DC output voltage may have some degree of ripple within the specifications for the application of the voltage converter. Because the converter is an isolated voltage converter, the output voltage is referred to herein as an isolated output voltage (Viso).

The magnitude of the energy transfer through the converter is influenced by, among other things, the inductances of the transformer's primary and secondary windings, the resonant capacitance, and the switching frequency of the primary side power stage. In one embodiment, the isolated voltage converter is an “integrated” isolated power converter meaning that the components of the converter including the transformer are formed as an integrated circuit on the same semiconductor die or in the same package containing multiple dies. That being the case, the transformer is small and thus the inductance of its windings are relatively small and the coupling coefficient of the transformer is also relatively small. That the transformer may be a relatively poor performance transformer can be compensated by switching at higher frequencies and by implementing a desired magnitude of the resonant capacitance. Also, to the extent that a circuit to implement the power stage on the primary side has a common mode voltage with a substantially large higher frequency component, the converter may generate substantial electromagnetic interference (EMI). The EMI results from the time-varying common mode voltage causing the isolated ground planes on the primary and secondary sides to radiate electromagnetic energy. The embodiments described herein provide example implementations of the power stage to reduce EMI.

FIG. 1 is a block diagram of an isolation voltage converter 100 in accordance with an example embodiment. The isolation voltage converter 100 has a primary side 105 and a secondary side 107. The isolated voltage converter 100 includes a transformer 120 that is operable as an isolation transformer to galvanically isolate the primary side 105 from the secondary side 107. The dashed line 101 delineates the primary side 105 from the secondary side 107. No electrical connection is present between the primary and secondary sides. The terms “primary” and “secondary” refer to the primary and secondary inductors (also referred to as coils or windings) of the transformer 120.

The primary side 105 includes a voltage input 111. The DC input voltage provided to the voltage input 111 is labeled Vin. The secondary side 107 includes a voltage output 131. The isolated output voltage from the voltage output 131 is Viso. The primary side 105 includes a primary-side power stage 110. The secondary side 107 includes a rectifier 130. In one example, the rectifier 130 is a full-bridge rectifier comprising four diodes, although other implementations of the rectifier are possible as well. The primary side 105 has a ground Vssp. The secondary side 107 has a ground Vsss. The grounds Vssp and Vsss are isolated from each other.

The transformer 120 has a primary winding 121 and a secondary winding 122. The primary-side power stage 110 receives Vin, and switch nodes VP1 and VP2 of the primary-side power are coupled to the terminals of the primary winding 121 of the transformer 120 as shown. The rectifier 130 is coupled to the secondary winding 122 of the transformer 120. The rectifier 130 converts the time-varying voltage from the secondary winding 122 of the transformer to the DC output voltage Viso. The voltages Vin and Viso do not share the same ground and are galvanically isolated from each other.

FIG. 2 is a schematic diagram illustrating one example implementation of the primary-side power stage 110. In this example, the primary-side power stage 110 includes transistors M1-M4 and a switch network 210. The switch network 210 includes two pairs of cross-coupled transistors. One pair of cross-coupled transistors includes transistors M5 and M6 and the other pair of cross-coupled transistors includes transistors M7 and M8. M1, M2, M5, and M6 are p-channel field effect transistors (PFETs), and M3, M4, M7, and M8 are n-channel field-effect transistors (NFETs). The sources of M1 and M2 are coupled together and receive Vin. The sources of M3 and M4 are coupled together at ground Vssp. The drain of M1 is coupled to the source of M5, and the drain of M2 is coupled to the source of M6. The gate of M5 is coupled to the drain of M6, and the gate of M6 is coupled to the drain of M5.

The drains of M5 and M7 are coupled together at the switch node VP1, and the drains of M6 and M8 are coupled together at the switch node VP2. The gate of M7 is coupled to the drain of M8, and the gate of M8 is coupled to the drain of M7. The source of M7 is coupled to the drain of M3, and the source of M8 is coupled to the drain of M4. The terminals of the primary winding 121 of the transformer 120 are coupled to the switch nodes VP1 and VP2.

In one embodiment, M1, M2, M3, and M4 are lower voltage-rated transistors than M5, M6, M7, and M8. The voltage rating of the transistor refers to the maximum allowed drain-to source voltage (Vds) and the maximum allowed gate-to-source voltage (Vgs). A lower voltage rated transistor has a better Figure of Merit (FoM) in terms of the product of the on-resistance and the gate charge (Rdson*Qg), which means that lower voltage-rated transistors produce lower loss when switching at a higher frequency compared to a transistor rated for higher voltages. In one specific example, each of M5-M8 are 5V transistors (maximum allowed Vds or Vgs is 5V), and M1-M4 are 1.5V transistors (maximum allowed Vds or Vgs is1.5V).

M1, M2, M3, and M4 are actively driven through the use of control signals discussed below with reference to FIG. 6. During operation, the control signals are asserted in a manner to cause M2 and M3 to be ON concurrently, while M1 and M4 are OFF, and then to cause M1 and M4 to be ON, while M2 and M3 OFF. The ON and OFF states of M1-M4 repeats—M1 and M4 ON (M2 and M3 OFF), then M2 and M3 ON (M1 and M4 OFF), then M1 and M4 ON again (M2 and M3 OFF), and so on.

The ON and OFF states of the cross-coupled transistors M5/M6 and M7/M8 are controlled as a result of the ON/OFF states of M1-M4. That is, M5-M8 are not actively driven by independently supplied control signals as otherwise is the case for M1-M4. For example, with M2 and M3 ON (and M1 and M4 OFF), M6 and M7 also are ON (and M5 and M6 are OFF). In this portion of each switching cycle, of the eight transistors, M2, M6, M7, and M3 are ON and the remaining transistors are OFF. With M2 and M6 being ON, switch node VP2 is pulled high towards Vin, and with M3 and M7 being ON, switch node VP1 is pulled low towards Vssp. In the opposite state of the switching cycle (M1, M5, M8, and M4 being ON, and M2, M6, M7, and M3 being OFF), switch node VP1 is pulled high towards Vin and switch node VP2 is pulled low towards Vssp.

FIG. 3A shows example waveforms for the switch nodes VP1 and VP2 for a conventional primary-side power stage. The common mode voltage (CM) also is shown. The CM voltage is the average of the VP1 and VP2 voltages. When one switch node is at Vin and the other switch node is at Vssp (or close to those voltages), the CM voltage is (Vin-Vssp)/2 (i.e., half-way between Vin and Vssp). In the example of FIG. 3A, the cross-over points 301 at which the VP1 voltage equals the VP2 voltage is larger than (Vin-Vssp)/2 due to asymmetries in a conventional primary-side power stage. The cause of such CM asymmetry is related to the different turn-on mechanisms of the transistors within a conventional primary-side power stage. For example, one conventional power stage includes an upper pair self-driven transistors (couple to VDD) and a lower pair of actively driven transistors couple to ground. Diagonal pairs of transistors (one self-driven and one actively driven) are nominally turned ON simultaneously during each switching cycle. However, the actively driven transistor is turned ON when its drain-to-source voltage is approximately 0V to reduce switching losses, but its diagonal self-driven transistor partner (whose gate is coupled the drain of the actively driven transistor) turns ON earlier (as soon as its gate-to-source voltage reaches the threshold voltage for the transistor. In other words, diagonal pairs of transistors turn ON, but not at exactly the same instance in time, which creates the asymmetry in the voltage waveforms. As a result of the cross-over point being higher than (Vin-Vssp)/2, the CM voltage increases at each cross-over point as shown (or decreases if the cross-over points are below (Vin-Vssp)/2). The increase (or decrease) in the CM voltage at each switching point contributes to higher frequency content in the CM voltage. The higher frequency content in the CM voltage results in EMI generation.

The primary-side power stage 110 described herein has an architecture that results in less asymmetry of the switching waveforms. The primary-side power stage 110 described herein has four actively driven transistors that are controlled to increase the symmetry of the voltage waveforms and reduce the CM voltage. FIG. 3B shows the VP1 and VP2 waveforms for the primary-side power stage 110 as described herein. The cross-over points 321 are approximately centered between Vin and Vssp and thus the CM waveform is relatively flat even through the switching points. The CM waveform resulting from the primary-side power stage described herein has relatively little higher frequency content compared to a conventional power stage. As a result, the primary-side power stage 110 contributes to little if any EMI.

FIG. 4 illustrates parasitic capacitances within the primary-side power stage 110. Capacitances Cp represents the parasitic capacitances of the drains of respective PFET transistors M1 and M2 when such transistor is OFF). Capacitances Cn represents the parasitic capacitances of the drains of the respective NFET transistors M3 and M4 when such transistor is OFF. Capacitance Cx represents the capacitance across VP1/VP2 when transistors M5-M8 are OFF. Capacitance Cx includes the drain-to-gate capacitances (Cdg) of transistors M5-M8, the series capacitance of the gate-to-source capacitance (Cgs)-Cn and drain-to-source capacitance (Cds)-Cn for the lower-side cross-coupled transistors M7/M8, and Cds-Cp and Cds-Cp for the upper cross-coupled transistors M5 and M6. Because a PFET has a smaller mobility than a comparably sized NFET, the M1 and M2 PFETs are sized larger than the NFETs M3 and M4 so as to have the same or similar on-resistances, which is helpful to balance the design efficiency and mitigate the difference in resistive drop during the ON-time which could otherwise affect the CM in the flat parts of the voltage waveforms. However, larger FETs have larger parasitic capacitance and thus Cp is larger than Cn.

FIG. 5 shows the waveforms of the switch nodes during the dead-time between two conduction phases at a cross-over point. The slope of VP1 is approximately piece-wise linear from Vssp to Vin. Three different slopes S1, S2, and S3 are identified for VP1. S1 is the slope as VP1 begins to increase with M3 turned OFF (starting at point 501) and M7 beginning to turn OFF. The slope S1 is predominantly influenced (from a parasitic capacitance perspective) by the sum of Cn and Cx. At 502, M7 is fully OFF, and the slope S2 is predominantly influenced to Cx only. At 503, M5 begins to turn ON and the slope S3 is predominantly influenced by the sum of Cp and Cx until M1 turns ON to start the next conduction phase. The waveform of the other switch node VP2 is similar but with the opposite sequencing. Because Cp is larger than Cn, the slope S3 is different than the slope S1. This bridge capacitive imbalance tends to force the cross-over points of the switching node waveforms to deviate from the mid-point between Vin and Vssp towards the upper half.

FIG. 6 is a schematic diagram of a primary-side power stage 610 usable as the primary-side power stage 110 of FIG. 1. The primary-side power stage 610 is largely the same as that of FIG. 2. Transistors M1-M8 are present and coupled in the same fashion as shown in FIG. 2 and described above. Capacitor devices C1 and C2 are also included. In one embodiment, capacitor devices C1 and C2 are capacitors (e.g., formed as metal layers separated by a dielectric on semiconductor die. In another embodiment, capacitor devices C1 and C2 are metal oxide semiconductor field effect transistors (MOSFETs) in which one terminal is the gate, and the source and drain are connected together to provide the other terminal of the capacitor. In other embodiment, four capacitors are included—a first capacitor across the drain and source of M3, a second capacitor across the drain and gate of M3, a third capacitor across the drain and source of M4, and a fourth capacitor across the drain and gate of M4.

C1 is coupled between the drain and source of M3. C2 is coupled between the drain and source of M4. C1 is thus in parallel with the parasitic capacitance Cn of M3. Similarly, C2 is in parallel with M4's parasitic capacitance. Accordingly, the total capacitance across M3 is (Cn+C1), and the total capacitance across M4 is (Cn+C2). The choice of the magnitude of C1 and C2 is made so that the sum of Cn and the respective capacitor is approximately the same as Cp. The models of the respective FETs indicate the values of Cp and Cn, and C1 and C2 can be calculated based on those values. By including the additional capacitors C1 and C2, the slopes of S1 and S3 can be made to be approximately equal thereby forcing the cross-over points to be closer to the midpoint between Vin and Vssp, thereby reducing the higher frequency content of the CM waveform, which results in lower EMI generation.

FIG. 7 is a schematic diagram of the primary-side power stage of FIG. 2 and the drive circuitry for controlling the ON and OFF states of M1-M4. The same drive circuitry can be used for the primary-side power stage of FIG. 6 as well. The drive circuitry includes buffers 602, 604, 606, and 608, capacitors C3 and C4, and transistors M9 and M10. The control signals mentioned above are shown in FIG. 7 as PH1 and PH2. PH1 and PH2 are digital signals having a higher logic state (“1”) and a lower logic state (“0”). PH1 and PH2 may be generated by, for example, an oscillator. PH1 and PH2 are at opposite logic states—when PH1 is a 1, PH2 is a 0, and vice versa, and a suitable dead-time is implemented as well.

Buffers 606 and 608 are inverting buffers, and buffers 602 and 604 are non-inverting buffers. The inputs of buffers 602 and 606 receive PH1. The output of buffer 602 is coupled to the gate of M3. The output of buffer 606 is coupled to the lower plate of C3. The upper plate of C3 is coupled to the drain of M9 and to the gates of M2 and M10. M9 and M10 are PFETs and, in some embodiments are smaller than M1 and M2. The inputs of buffers 604 and 608 receive PH2. The output of buffer 604 is coupled to the gate of M4. The output of buffer 608 is coupled to the lower plate of C4. The upper plate of C4 is coupled to the drain of M10 and to the gates of M1 and M9.

Vin can be any voltage in a range of values. In one example, the valid range of values for Vin is from 3V to 5.5V. Buffers 602, 604, 606, and 608 are 1.5V buffers. Accordingly, their output voltages are either approximately 0V or approximately 1.5V. The following explanation assumes PH1 is logic low and PH2 is logic high which causes M1 and M4 to be ON and M3 and M2 to be OFF. With PH1 being logic low, the output of inverting buffer 606 and thus the lower plate of capacitor C3 is at a voltage of approximately 1.5V. The gates and sources of M1 and M9 are coupled together and thus if M1 is on, M9 also is on. With M1 and M9 both being ON, assuming Vin is 5V, then the upper plate of C3 is at a voltage of approximately 5V. Accordingly, the voltage across C3 is approximately 3.5V (5-1.5). The upper plate of C3 is coupled to the gates of M2 and M10, and the voltage of 5V on the upper plate of C3 is too high to turn ON M2 or M10.

After the ON-time has elapsed, PH2 becomes logic low thereby turning OFF M1, M9, and M4During the next switching event, PH1 changes state from logic low to logic high to turn on M3. Responsive to PH1 now being logic high, inverting buffer 606 forces its output voltage to be approximately 0V. Thus, the voltage on the lower plate of C3 is pulled down from approximately 1.5V to approximately 0V. The voltage across C3, however, maintains the same voltage difference, and thus the voltage on the upper plate of C3 also is pulled down by 1.5V from approximately 5V to 3.5V. The drop in the voltage on the upper plate of C3 also pulls down the voltage on the gates of M2 and M10 to a low enough level to cause M2 and M10 to turn ON. With M10 now being ON, its drain voltage is pulled upward towards Vin. The drain of M10 is coupled to the gates of M1 and M9 and the increase in the voltage on the drain of M10 causes M1 and M9 to remain OFF.

Also, with M10 ON, current flows to C4 to thereby recharge C4. The voltage on the upper plate of C4 is approximately 5V. The voltage on the lower plate of C4 is approximately 1.5V, as a result of the output voltage from inverting buffer 608 being approximately 1.5 while PH2 is logic low.

The operation of the drive circuitry is largely the same in the next switching event when PH1 changes from logic high to low and PH2 changes from logic low to high. The decrease in voltage on the lower plate of C4 causes a commensurate decrease in the voltage on the upper plate of C4 which causes M1 and M9 to turn ON. M9 turning ON, in turn, causes the voltage on the gates of M2 and M10 to be forced high enough to turn OFF M2 and M10.

The drive circuitry of FIG. 7 advantageously does not require active level shifters for the gate voltages of the PFETs M1 and M2. Further, only two digital control signals are needed to operate all four transistors M1-M4. Further, the drive buffers 602, 604, 606, and 608 all share the same voltage supply, which reduces the source of possible delay mismatches in the PFET versus NFET gate drive signals.

In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-channel field effect transistor (PFET) may be used in place of an n-channel field effect transistor (NFET) with little or no changes to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)). Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

References herein to a field effect transistor (FET) being “ON” means that the conduction channel of the FET is present and drain current may flow through the FET. References herein to a FET being “OFF” means that the conduction channel is not present and drain current does not flow through the FET. A FET that is OFF, however, may have current flowing through the transistor's body-diode.

Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A circuit comprising: a first transistor having a current terminal and a control terminal;a second transistor having a current terminal and a control terminal;a third transistor having a current terminal and a control terminal;a fourth transistor having a current terminal and a control terminal;a switch network coupled to the current terminal of the first transistor, to the current terminal of the second transistor, to the current terminal of the third transistor, and to the current terminal of the fourth transistor;a first buffer having an input and an output, wherein the output is coupled to the control terminal of the second transistor;a second buffer having an input and an output, wherein the output is coupled to the control terminal of the first transistor;a third buffer having an input and an output, the input coupled to the input of the first buffer and the output coupled to the control terminal of the third transistor; anda fourth buffer having an input and an output, wherein the input is coupled to the input of the second buffer and the output is coupled to the control terminal of the fourth transistor.

2. The circuit if claim 1, wherein the first buffer is an inverting buffer, the second buffer is an inverting buffer, the third buffer is a non-inverting buffer, and the fourth buffer is a non-inverting buffer.

3. The circuit of claim 1, further comprising: a fifth transistor having a current terminal and a control terminal, the current terminal coupled to the output of the first buffer and to the control terminal of the second transistor, and the control terminal coupled to the control terminal of the first transistor; anda sixth transistor having a current terminal and a control terminal, the current terminal coupled to the output of the second buffer and to the output of the first buffer, and the control terminal coupled to the control terminal of the second transistor.

4. The circuit of claim 3, further comprising: a first capacitor coupled between the current terminal of the fifth transistor and the output of the first buffer; anda second capacitor coupled between the current terminal of the sixth transistor and the output of the second buffer.

5. The circuit of claim 1, further comprising: a first capacitor coupled to the current terminal of the third transistor; anda second capacitor coupled to the current terminal of the fourth transistor.

6. The circuit of claim 1, wherein the first buffer is configured to receive a first signal at the input of the first buffer, the second buffer is configured to receive a second signal at the input of the second buffer, the third buffer is configured to receive the first signal at the input of the third buffer, and the fourth buffer is configured to receive the second buffer at the input of the fourth buffer.

7. The circuit of claim 1, wherein the switch network comprises: a fifth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the first transistor;a sixth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the second transistor and the control terminal coupled to the second current terminal of the fifth transistor;a seventh transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the third transistor, the second current terminal coupled to the second current terminal of the fifth transistor, and the control terminal coupled to the control terminal of the fifth transistor; andan eighth transistor having a first current terminal and a second current terminal, the first current terminal coupled to the current terminal of the fourth transistor, the second current terminal coupled to the second current terminal of the sixth transistor, and the control terminal coupled to the control terminal of the sixth transistor.

8. A circuit comprising: a first transistor having a current terminal and a control terminal;a second transistor having a current terminal and a control terminal;a third transistor having a current terminal and a control terminal;a fourth transistor having a current terminal and a control terminal;a fifth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the first transistor;a sixth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the second transistor and the control terminal coupled to the second current terminal of the fifth transistor;a seventh transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the third transistor, the second current terminal coupled to the second current terminal of the fifth transistor, and the control terminal coupled to the control terminal of the fifth transistor;an eighth transistor having a first current terminal and a second current terminal, the first current terminal coupled to the current terminal of the fourth transistor, the second current terminal coupled to the second current terminal of the sixth transistor, and the control terminal coupled to the control terminal of the sixth transistor;a first buffer having an input and an output, wherein the output is coupled to the control terminal of the second transistor;a second buffer having an input and an output, wherein the output is coupled to the control terminal of the first transistor;a third buffer having an input and an output, the input coupled to the input of the first buffer and the output coupled to the control terminal of the third transistor; anda fourth buffer having an input and an output, wherein the input is coupled to the input of the second buffer and the output is coupled to the control terminal of the fourth transistor.

9. The circuit if claim 8, wherein the first buffer is an inverting buffer, the second buffer is an inverting buffer, the third buffer is a non-inverting buffer, and the fourth buffer is a non-inverting buffer.

10. The circuit of claim 9, further comprising: a ninth transistor having a current terminal and a control terminal, the current terminal coupled to the output of the first buffer and to the control terminal of the second transistor, and the control terminal coupled to the control terminal of the first transistor; anda tenth transistor having a current terminal and a control terminal, the current terminal coupled to the output of the second buffer and to the output of the first buffer, and the control terminal coupled to the control terminal of the second transistor.

11. The circuit of claim 10, further comprising: a first capacitor coupled between the current terminal of the ninth transistor and the output of the first buffer; anda second capacitor coupled between the current terminal of the tenth transistor and the output of the second buffer.

12. The circuit of claim 8, further comprising an inductor having a first terminal and a second terminal, the first terminal coupled to the second current terminal of the fifth transistor and the second terminal coupled to the second current terminal of the sixth transistor.

13. The circuit of claim 8, further comprising: a first capacitor coupled to the current terminal of the third transistor; anda second capacitor coupled to the current terminal of the fourth transistor.

14. The circuit of claim 8, wherein the first buffer is configured to receive a first signal at the input of the first buffer, the second buffer is configured to receive a second signal at the input of the second buffer, the third buffer is configured to receive the first signal at the input of the third buffer, and the fourth buffer is configured to receive the second buffer at the input of the fourth buffer.

15. A circuit comprising: a first transistor having a current terminal and a control terminal;a second transistor having a current terminal and a control terminal;a third transistor having a current terminal and a control terminal;a fourth transistor having a current terminal and a control terminal;a fifth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the first transistor;a sixth transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the second transistor and the control terminal coupled to the second current terminal of the fifth transistor;a seventh transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the current terminal of the third transistor, the second current terminal coupled to the second current terminal of the fifth transistor, and the control terminal coupled to the control terminal of the fifth transistor;an eighth transistor having a first current terminal and a second current terminal, the first current terminal coupled to the current terminal of the fourth transistor, the second current terminal coupled to the second current terminal of the sixth transistor, and the control terminal coupled to the control terminal of the sixth transistor;a first buffer having an input and an output, wherein the output is coupled to the control terminal of the second transistor;a second buffer having an input and an output, wherein the output is coupled to the control terminal of the first transistor;a third buffer having an input and an output, the input coupled to the input of the first buffer and the output coupled to the control terminal of the third transistor;a fourth buffer having an input and an output, wherein the input is coupled to the input of the second buffer and the output is coupled to the control terminal of the fourth transistor;a transformer having a first winding and a second winding, the first winding having a first terminal and a second terminal, the first terminal coupled to the second current terminal of the fifth transistor and the second terminal coupled to the second current terminal of the sixth transistor; anda rectifier coupled to the second winding of the transformer.

16. The circuit if claim 15, wherein the first buffer is an inverting buffer, the second buffer is an inverting buffer, the third buffer is a non-inverting buffer, and the fourth buffer is a non-inverting buffer.

17. The circuit of claim 15, further comprising: a ninth transistor having a current terminal and a control terminal, the current terminal coupled to the output of the first buffer and to the control terminal of the second transistor, and the control terminal coupled to the control terminal of the first transistor; anda tenth transistor having a current terminal and a control terminal, the current terminal coupled to the output of the second buffer and to the output of the first buffer, and the control terminal coupled to the control terminal of the second transistor.

18. The circuit of claim 17, further comprising: a first capacitor coupled between the current terminal of the ninth transistor and the output of the first buffer; anda second capacitor coupled between the current terminal of the tenth transistor and the output of the second buffer.

19. The circuit of claim 15, further comprising: a first capacitor coupled to the current terminal of the third transistor; anda second capacitor coupled to the current terminal of the fourth transistor.

20. The circuit of claim 15, wherein the first buffer is configured to receive a first signal at the input of the first buffer, the second buffer is configured to receive a second signal at the input of the second buffer, the third buffer is configured to receive the first signal at the input of the third buffer, and the fourth buffer is configured to receive the second buffer at the input of the fourth buffer.