The present invention relates generally to integrated circuits and more particularly to low power implementation of high speed, high density, and high capacity logic switching circuits.
The electrical erasable and programmable EEPROM memory devices have become more widely used in the last decade. The technological advances and broad product applications have made EEPROM memory devices the most viable candidate for implementing SOC level component integrations.
On the process and device technology side, the general practice of memories has been focused on the miniaturization of the physical size of the storage bit, scaling down the cell operating voltages and currents and therefore lowering power consumption. Thereby implementing multilevel signal storages per physical cell area can be implemented. In addition, chip apparatus can be built to manage per bit, byte, large and partial arrays, resource sharing schemes. The ultimate goal is to achieve highest level of system integration with mixed analog and logic circuits in a common chip and therefore improve IC devices with performance, reliability, system efficiency and capacity etc.
Flash memory is a good choice for information storage devices based upon their increasing capacity. The name of “Flash memory and logic device” is adopted based upon the device's fast operation and its use in large arrays. The Flash devices are closely related to the Flash technology. The density, power, and speed capability of Flash arrays exceed what is offered by rotating disks, so the semiconductor EEPROM is replacing the mechanical disk medium in many applications. The Flash memory can also replace DRAM/SRAM for certain applications if the speed/performance requirements are met. Flash memory is nonvolatile and has high density per cell for information storage.
The EEPROM device may be applicable as ideal memory device; both as standalone memory/logic part and as part of an embedded storage/logic unit in an ASIC. The Flash device has several attractive features such as compactness, low power and high speed. A Flash device could replace conventional mechanical and optical disks, controller and microprocessors for network and communications. There is an interest to extend the use of the Flash devices in printed circuit board (PCB) assemblies. However, conventional PCB subsystem assemblies still use standalone logic chips, memory chips, and discrete components interconnecting them with the PCB wiring. It is desirable for a small system such as SD card, stick card, pen drives, PDA, mobile phone to merge the memory capacity, processing power, and even some analog functions in a universal IC. This will be advantageous in both the space and cost savings, and to optimize performance.
There are numerous prior art methods and systems in Flash technology, which has been utilized for information storage. The Flash transistor has been successfully developed as either a single bit or a dual bit system storage circuit element. However, typically the Flash transistor is not utilized as logic circuit element.
Field Programmable Logic Devices represented by PLA solutions utilizing Flash devices are well known. The field programmable ICs either reconfigure prime term logic arrays or functional units with on-chip wiring switches and tracks. However, these devices are not utilized to make functional units by directly programming the threshold of the switch transistor and in configuring a basic logic circuit unit. A typical FPGA contains standalone CMOS-TTL implementations with device capacity in the range of a couple hundred gates to about 10 k gates. The basic building blocks contain I/O and logic elements for the latch and the TTL hard and soft macros, RAM arrays, wiring switches and tracks. The most advanced FPGA uses 1.8V supply. The device is highly popular for it flexibility and supported software package. It is difficult to merge a Flash array with the CMOS-TTL logic circuit for the process and circuit compatibility issues, and there is no business advantage to merge these technologies for neither the manufacturers of FPGA nor the manufacturers of Memory standard parts.
In conventional integrated circuits billions of transistors are successfully found therein. However, many parts that perform different functions are still difficult to integrate. One of the most obvious reasons for this difficulty is the process compatibility issue. It is difficult to merge present technologies because of different process cost objectives for volume parts such as memory and logic units. Memory commodity parts are remarkably cost sensitive and even a minor complication would cost more to the standardized parts. As long as the standardized parts are selling in high volume, there is a barrier for any newly emerged parts or approaches to begin. Usually a tremendous breakthrough in speed, density, power, or capacity is required to make this change. In addition typically reliability-availability-serviceability (RAS) must be of a high quality for such a breakthrough.
Nevertheless, an opportunity to merge the FPGA and Flash technology is desired. By adding the computing power with the densest logic circuit to the densest storage devices, a universal part is emerged, and great design flexibility is added to device capacity and performance options. Furthermore, logic circuits may be augmented to contain analog function and multi-valued logic, and still perform at low power.
Computer systems today are based on two-valued (binary) logic. In most cases, a signal wire carries only two signal levels at any time. Boolean algebra and its associated developments have helped the acceptance and exploitation of binary logic. However, the most pressing problems in systems made from binary logic systems are interconnection issues, both of nets on chip and between chips. Accordingly, what is needed is a system and method for addressing the need for such devices with at least some or many signal wires carrying more than two signal levels. The present invention addresses such a need.
A logic circuit comprising a trinary or quaternary logic switching circuit which includes a multilevel storage cell (MLSC), and the variable threshold logic (VTL) means to yield an improved space, power, and time-efficient performance device is disclosed. The present invention is used for the implementation of a customized new logic design to further improve the cost-effectiveness of the application.
The present invention relates generally to integrated circuits and more particularly to multileveled logic switching circuits. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
The present invention utilizes device and system architecture for providing intelligent nonvolatile subsystems. The nonvolatile subsystem encompasses embedded units of Flash and memory arrays (SRAM, DRAM, ROM) and programmable logic arrays. The goal is to optimize an organization of low cost, high capacity, distributive computing and memory storages. Flash transistors and SBD-CMOS transistors are the basic circuit elements to implement the various hardware constructs. SFPGA software and transmission line signal control means are key to ensure high performance operations.
SFPGA techniques are utilized to allocate and configure certain portion of the logic circuits of a memory intensive chip. Both circuit unit types can be mixed to form a universal programmable device with Logic and Storage arrays. The users can field program certain high performance critical nets, IO ports, buffers, and clocking constructs. A wide performance range switching operations can be supported. Prior arts of fine-tuning clocking systems, reflection containment, data transfer protocols, and collision detection and error correction issues from leading vendors are greatly improved by the present invention.
Prior art U.S. Pat. No. 6,590,800 entitled “Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL”, issued Jul. 8, 2003, by the inventor of this application describes a process and circuit scheme to lower the logic and RAM cell supply voltage to 1.2V and lower the current down to sub microamperes. By lowering the current and voltage in this manner, the array peripheral organization can be revamped using low power logic circuits. Copending U.S. patent application entitled “3D Flash EEPROM Cell and Methods of Implementing the Same”, Ser. No. ______ (3064), copending U.S. patent application entitled “Variable Threshold Transistor for the Schottky FPGA and Multilevel Storage Cell Flash Arrays”, Ser. No. ______ (3065) copending U.S. patent application entitled “SCL Type FPGA with Multi-Threshold Transistors and Method for Forming Same”, Ser. No. ______ (3070P), and copending U.S. patent application entitled entitled “Distributive Computing Subsystem of Generic IC Parts”, Ser. No. ______ (3072P), also disclose these features and are incorporated by reference herein. These features therefore allow for the development of:
A system and method in accordance with the present invention utilizes memory arrays with certain field programmable logic resources to provide circuit functionality and inter unit connectivity in the PCB. Ratios for the right mixture of the fixed and re-configurable units are at the discretion of the user as each functional part is defined.
The combined chips provide intensive large (Gbit) storage capacity plus a large number (10-100 k) of gates, relatively smaller dedicated physical resources of processing and buffering power, re-configurable ports, and stored software constructs. Wide application chip sets can be formed from the embedded memory, processor and logic arrays in accordance with the present invention. Utilizing the system and method in accordance with the present invention, a plural number of chips can form subsystems with single to large string of super or universal (UIC) chips. Finally, subsystem PCBs can provide distributive computing powers by partitioning them with various PCB arrangements and instantiated controls through reconfiguration procedures utilizing a system and method in accordance with the present invention.
One preferred embodiment shown in
Flash Transistors for Embedded Memory and Logic Solutions
The process technology of the present invention devices emphasizes the compatibility for making Flash transistors, CMOS transistors, and Schottky barrier diodes.
One of ordinary skill readily recognizes that more variations can be derived from the teachings of this invention by mixing low power SCL circuits with Flash array and FPGA for other applications at system and device levels.
The cost of Flash memory has been significantly reduced in a per bit basis by the NAND Flash invention. The basic cell of a NAND Flash memory can be SLC or MLC. In the MLC case, the integration of computational logic to MVL functional blocks results in the current invention. Due to the capability of SFPGA and multiple valued logic (MVL) gates, the invention is extended to a useful Quaternary sorter implementation.
The state transit diagram and programming cycles are shown in
The Quaternary Logic Gate and State Machines
The reverse action is also realizable. According to the method depicted in
The subsystem in
Table 2 below shows the simple VR generator truth table. The reference taps are derived from rail to rail voltages with SBD diode drops or offsets (0.3V per step) either from VCC or above GND.
Quaternary Logic Circuitry and Exemplary Implementation of Selected Logic Operations Tables 3-1˜3 are the initial implementations of 3 quaternary logic operators. Assumptions are that each of the input variables has 4 states { 0,1,2,3 }. The flow diagrams in
A Multiple-Valued Logic Sorter Using Multiple-Level Storage Cell (Flash) and Variable Threshold Transistors
The present mainstream computers are based on two-valued (binary) logic. Boolean algebra and its associated developments have helped the acceptance and exploitation of binary logic. The most pressing problems in binary systems, however, are too many interconnection or bandwidth is low on a per signal wire basis, both for on chip and between chips. Multiple-valued logic (MVL) on the other hand can raise information contents per interconnection. Comparing the number of interconnection lines with required 100 binary lines, quaternary logic only needs 50 lines. Furthermore, in general for any numeric system, the larger the radix the smaller the number of digits is needed to express a given quantity. For a cost or complexity criterion where system hardware is proportional to the digit capacity R·d, where R is the radix and d is the necessary number of digits, quaternary logic scores the same as binary logic.
For another cost or complexity criterion where system hardware is independent of R, the total system cost of quaternary logic scores only half of that of binary logic system. While potential applications call for a true multi-state device higher than binary, here in this invention, we proposed a psuedo multilevel logic hardware and software solution. It is practical to integrate binary system with quaternary logic system. The coexistence of multilevel logic and binary constructs allows the trinary logic driver and quaternary sorter in accordance with the present invention to be integrated with other parts of the system. While ternary logic has the advantage of a balanced system values for arithmetic {−1,0,1}, quaternary is convenient for binary interfacing between R=2 and R=4. The sorter in accordance with the present invention uses quaternary logic.
Using the present invention of the MLSC and VTL to implement the sorter in accordance with the present invention, the advantage of the SFPGA efficiency is utilized. In general, FPGA wins in programmability, re-configurability, integration and development cycle but loses in some throughput performance, area utilization and power consumption against ASIC. Nevertheless, the SFPGA mitigate these shortcomings but scores high in density, low power, high speed and easy to reconfigure.
Quaternary Logic Blocks
Referring now to
To sort 2p data using bitonic sorters requires only (½)p(p+1) stages each with 2p−1 comparison units for (p2+p)2p−2 units, where bitonic referring to a sequence of data formed by juxtaposition of two monotonic sequences, one ascending, the other descending. It is more cost-effective than a normal crossbar in hardware requirement.
To illustrate the construction rule and the sorting operation described above, refer to
To complete the implementation of the sorter's functionality, the comparison unit or comparator with inputs A and B and outputs H and L should have a specification as depicted in
To realize the comparator, available quaternary logic is chosen and operational algebra is used.
A design of the quaternary comparison unit in accordance with the present invention is given in
The sorter in accordance with the present invention uses the well-known sorting-by-merging scheme to construct the sorting network or sorting memory. The data represented in quaternary form are combined two at a time to form ordered list of length two.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
The present invention is related to copending U.S. patent application entitled “3D Flash EEPROM Cell and the Methods of Implementing the Same”, Ser. No. 10/800,257, filed on Mar. 11, 2004, and assigned to the assignee of the present invention; and copending U.S. patent application entitled “Variable Threshold Transistor for the Schottky FPGA and Multilevel Storage Cell Flash Arrays”, Ser. No. 10/817,201, filed on Apr. 2, 2004, and assigned to the assignee of the present invention which is related to copending U.S. patent application entitled “SCL Type FPGA with Multi-Threshold Transistors and Method for Forming Same”, Ser. No. ______ (3070P) filed on Apr. 19, 2004, and assigned to the assignee of the present invention, and U.S. patent application entitled “Distributive Computing Subsystem of Generic IC Parts”, Ser. No. ______, (3072P) filed on May 7, 2004, and assigned to the assignee of the present invention, all of which are incorporated by reference herein.