Patent Application
20090059675
Embodiments of the invention relate to metal oxide semiconductor (MOS) non-volatile semiconductor memories. Specifically, the invention relates to non-volatile semiconductor memory, and methods for making the same, intended to operate in a radiation exposed environment.
Non-Volatile Semiconductor Memory (NVSM) is a class of non-volatile memory (NVM) where the stored content or information (bit) in the semiconductor memory is preserved whenever power is removed from the device. Thus, NVSM devices retain stored information even without a power source. NVSM devices are used in computers, PDAs, mobile phones, digital cameras, and other devices requiring a non-volatile memory.
NVSMs that use charge storage as the memory mechanism utilize one of two physical device structures called “floating gate” and “SONOS” (silicon-oxide-nitride-oxide-silicon). A conventional floating gate memory cell contains a control gate and an electrically isolated floating gate. The electrically isolated floating gate is located below the control gate and above a transistor channel. The electrically isolated floating gate is separated from the control gate and the transistor by oxide. The floating gate includes a conducting material, typically a poly-silicon layer. Floating gate memory devices store information by holding electrical charge within the floating gate. Adding or removing charge from the floating gate changes the threshold voltage of the cell, thereby defining whether the memory cell is in a “programmed” or “erased” state.
A SONOS device stores charge within discrete traps located in a nitride film in a gate dielectric. Therefore, the SONOS device is often referred to as a nitride-based read only memory (NROM).
The above-described types of memories are susceptible to environmental conditions, such as external radiation. Radiation can induce undesirable charge into the memory cell structure, resulting in a reduction in the sensitivity to the state of the stored memory bit. After radiation exposure, the write and erase state threshold voltages may begin to converge, which in turn will result in loss of the ability to distinguish between the write and erase state. The difference between the write and erase states is referred to as the memory window. As the threshold voltages of the two states converge, the memory window becomes smaller until there is no longer a memory window present and the ability to distinguish between the logic one (high VTH) or zero (low VTH) in the cell is lost.
In one aspect, a radiation hardened transistor includes a buried source, buried drain and a poly-silicon gate separated from the buried source and the buried drain by a buried oxide. A recessed P+ implant or a blanket P+ implant is disposed in a substrate. A portion of the recessed P+ implant or a portion of the blanket P+ implant is disposed beneath outer edges of the poly-silicon gate, in a channel separating the buried source and the buried drain.
As indicated above, the NROM cell 180 comprises a nitride layer 189, which serves as a trapping dielectric for two separate localized charge packets at each end of the cell 180, effectively storing two bits. Each charge can be maintained in one of two states, either “programmed” or “erased,” represented by the presence or absence of a pocket of trapped electrons, which enables the storage of two bits of information. Each storage area in an NROM cell 180 can be programmed or erased independently of the other storage area. An NROM cell is programmed by applying a voltage that causes negatively charged electrons to be injected into the nitride layer near one end of the cell.
As shown in
To program the other side of the NMOS cell 180, BL1183 is grounded and a voltage (e.g., 4V) is applied to BL2184 (not shown). In this case, the electrons (e.g., charge 198) are trapped on the nitride layer 189 closest to BL2184. Once the charge or electrons (e.g., charge 195 or 198) is stored, it can be read in a direction opposite to the direction it was programmed. The multi-bit functionality of the NROM cell 180 is achieved by storing charge (equivalent to one bit of data) at both sides (source and drain) of the device channel as evident from the symmetric nature of the structure.
Erasing of the NROM cell 180 is accomplished by applying voltages to a cell that cause positive charges, referred to as “holes” to be injected into the nitride layer and cancel the effect of the electrons previously stored there during programming. Because a significantly smaller amount of trapped charges is needed to program a device, and due to the physical mechanisms used for program and erase, the NROM cell 180 can be both programmed and erased faster than devices based on traditional floating gate technology. When the NROM cell 180 is programmed, the trapped electrons (negative charge) 195 create a positive shift in the threshold voltage of the NROM cell 180 due to the potential barrier created at the surface directly underneath the narrow charge storage region in the nitride layer 189. Due to the reverse read, the threshold voltage of the device is determined solely by the opposite (drain) bit. When the NROM cell 180 is erased, the holes either recombine with electrons or are trapped within the nitride, resulting in a negative shift in the threshold voltage of the memory device.
Due to the above indicated advantages of the SONOS or NROM devices, it is desirable to use these devices in radiation environments. However, ionizing radiation induces large amounts of trapped positive charge within thick oxide regions of the SONOS device. This trapped positive charge can significantly lower the NROM threshold voltage in p-type semiconductor channel regions immediately adjacent to the oxide edge (gate overlap region) and results in high off-state NMOS leakage currents (between the N+ doped source and drain regions).
The threshold voltages of SONOS devices are modulated by the presence of positive or negative charge within a charge storage layer. The low and high threshold voltage states are assigned logic values in order to store a bit of data in the memory cell. For example, the high threshold voltage is often referenced as a logic “one” while the low threshold voltage is referenced as the logic “zero.” Changes in the threshold voltage of the memory device directly correspond to whether (or not) a bit of information is stored within the memory cell. If the threshold voltage changes due to, for example, external radiation environments, the information stored in the SONOS NROM device may be misread or not read at all.
An embodiment provides a novel semiconductor device that may significantly increase the per unit area memory density of radiation hard non-volatile semiconductor memory (RHNVSM) by employing a multi-bit one transistor (1T) Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) transistor structure. In an embodiment, a recessed P+ region or a blanket P+ region may be used to improve the radiation hardness of the SONOS non-volatile semiconductor memory (NVSM). In addition, radiation hardness of peripheral (e.g., to the memory array) NMOS transistors may also be improved using the structures or techniques described herein.
In an embodiment, one or more techniques are provided to periodically and/or adaptively refresh, for example, a SONOS memory cell or memory array to offset any detrimental effects of radiation exposure on the memory cell or memory array. For example, the memory cell may be adaptively refreshed after a pre-set radiation dose and may be refreshed several times in order to extend the life of the system. Additionally or optionally, the memory cell may be refreshed based on a predetermine time interval or based on a comparison between a present threshold value and a predetermined reference or target value. The stored memory bit may be refreshed using several different methods including a single re-write, erase then re-write, or an adaptive refresh. The refresh technique may provide an improvement in the ability of the system to disseminate between the write and erase states after elevated radiation doses.
A radiation-hard non-volatile memory relates to a NVM that is operated in ionizing radiation environments—such as outside of the earth's atmosphere—where the ionizing radiation induces positive trapped charge in thick oxide regions.
SONOS type NVM have the ability to trap charge uniformly throughout the entire nitride, or locally within separate lateral regions of the nitride layer, which alters the threshold voltage in the channel directly below this stored charge. This allows independent regions of charge to store multiple bits of memory data within a single SONOS device, improving the density of stored memory bits.
As shown in step 740 of
In an alternative embodiment, as shown in step 760, a blanket P-type implant 765 may be diffused instead of the self-aligned P+ regions 755. The blanket P-type implant 765 raises the NMOS threshold voltage in all P-type regions that enclose the poly silicon gate and the buried N+ regions. Using the blanket P-type implant, the memory cell size may be reduced since the buried bit lines (e.g., bit lines 521 and 531) can be formed closer to each other since the recessed self-aligned P+ regions are not required.
Techniques described above may eliminate the threshold voltage shift resulting from radiation-induced charge trapping in the buried oxide as well as edge leakage. However, charge trapping in the NROM gate dielectric layer may also degrade memory operation. Radiation-induced positive charge introduced to the NROM gate dielectric can either trap within the dielectric layer or recombine with electrons stored in the nitride layer (in the write state). Both conditions can result in a shift of the threshold voltage (VTH) toward the depletion mode and an overall reduction in the sensitivity to the state of the stored memory bit. Consequently, the write and erase state threshold voltages begin to converge after radiation exposure, which in turn will result in loss of the ability to distinguish between the write and erase state. The difference between the write and erase states is referred to as the memory window. As the threshold voltages of the two states converge, the memory window becomes smaller until there is no longer a memory window present and the system cannot distinguish between the logic one (high VTH) or zero (low VTH) and the data is lost.
To mitigate effects of radiation-induced charge trapping in the gate dielectric, one or more methods are provided for incrementally refreshing the memory state during radiation exposure, enhancing radiation hardened memory performance. In an embodiment, the stored memory state is refreshed after a memory device or cell has been exposed to a pre-set or incremental level of radiation as illustrated. The refresh techniques described herein provide a dramatic improvement in the ability of the system to disseminate between the write and erase states after elevated radiation doses.
Referring again to
The memory state refresh may be handled using different methods. For example, the memory state can be refreshed simply by injecting additional electrons into the memory device to compensate for electrons which have recombined with the radiation-induced charge. This technique may be referred to as a “rewrite,” which results in a larger memory window.
A second approach for refreshing the write state is to first erase the memory device and then re-write the device. This approach prevents excess of electrons from being injected into the memory bit so the device is not over-written.
Several embodiments of the present invention are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.
