Patent Application
20240418873
The present disclosure relates to a radiation imaging apparatus, a radiation imaging system, and a control method for the radiation imaging apparatus.
A radiation imaging apparatus has been put into practical use as an imaging apparatus used for medical image diagnosis or nondestructive inspection. A radiation image generated by a radiation imaging apparatus includes noise caused by a dark current flowing to a photodiode or an afterimage generated by last radiation irradiation. To reduce such noise, the radiation image is corrected using an offset image obtained in a state in which the radiation imaging apparatus is not irradiated with radiation. Japanese Patent Laid-Open No. 2014-168602 describes a technique of correcting a radiation image using primary offset data and reference secondary offset data obtained before the start of imaging and immediately preceding secondary offset data obtained after the start of imaging to implement a high frame rate and reduce an afterimage. The immediately preceding secondary offset data is obtained within an exposure time shorter than that of the radiation image. The primary offset data is obtained within an exposure time equal to that of the radiation image. The reference secondary offset data is obtained within an exposure time equal to that of the immediately preceding secondary offset data.
In the technique described in Japanese Patent Laid-Open No. 2014-168602, the temporal relationship of obtaining of the reference secondary offset data with obtaining of the primary offset data is different from the temporal relationship of obtaining of the immediately preceding secondary offset data with obtaining of the radiation image. Therefore, it is difficult to accurately reduce noise in the radiation image.
Some aspects of the present disclosure provide a technique of accurately reducing noise in the radiation image. According to one aspect of the present disclosure, there is provided a radiation imaging apparatus comprising: a plurality of pixels arranged to form a plurality of pixel rows and a plurality of pixel columns and configured to generate and accumulate electric charges; a driving circuit configured to supply, to the plurality of pixels, a driving signal for selecting one of the plurality of pixels; a readout circuit configured to read out a signal based on the electric charges accumulated in the pixel selected by the driving signal; a control circuit configured to control the readout circuit and the driving circuit; and an image generation circuit configured to generate a radiation image, wherein with respect to at least a first pixel among the plurality of pixels, the control circuit controls the readout circuit and the driving circuit to alternately execute, in imaging preparation, a first readout operation of reading out a first offset signal based on electric charges accumulated in the first pixel for a first time length, and a second readout operation of reading out a second offset signal based on electric charges accumulated in the first pixel for a second time length shorter than the first time length, and alternately execute, after imaging preparation ends, a third readout operation of reading out a radiation signal based on electric charges accumulated in the first pixel for a third time length including a period during which the radiation imaging apparatus is irradiated with radiation, and a fourth readout operation of reading out a third offset signal based on electric charges accumulated in the first pixel for a fourth time length shorter than the third time length without including a period during which the radiation imaging apparatus is irradiated with the radiation, and the image generation circuit generates the radiation image based on correction of the radiation signal using the first offset signal, the second offset signal, and the third offset signal.
Further features of the present disclosure will become apparent from the following description of exemplary embodiments (with reference to the attached drawings).
Hereinafter, embodiments will be described in detail with reference to the attached drawings. Note, the following embodiments are not intended to limit the scope of the present disclosure. Multiple features are described in the embodiments, but limitation is not made to the present disclosure that requires all such features, and multiple such features may be combined as appropriate. Furthermore, in the attached drawings, the same reference numerals are given to the same or similar configurations, and redundant description thereof is omitted.
The radiation generating apparatus 140 starts irradiation with radiation 160 in accordance with an exposure instruction (emission instruction) from the exposure control apparatus 130. The radiation 160 emitted from the radiation generating apparatus 140 passes through an object 150 to enter the radiation imaging apparatus 110. The radiation generating apparatus 140 stops irradiation with the radiation 160 in accordance with a stop instruction from the exposure control apparatus 130.
The radiation imaging apparatus 110 includes a radiation detecting panel 111, a control circuit 112, an image generation circuit 113, and a storage device 170. The radiation detecting panel 111 generates a radiation image corresponding to the radiation 160 entering the radiation imaging apparatus 110, and transmits the generated radiation image to the computer 120. The control circuit 112 controls the operation of the radiation detecting panel 111. For example, the control circuit 112 generates a stop signal for stopping the irradiation with the radiation 160 from the radiation generating apparatus 140 based on an image signal obtained from the radiation detecting panel 111. The stop signal is supplied to the exposure control apparatus 130. In response to the stop signal, the exposure control apparatus 130 sends a stop instruction to the radiation generating apparatus 140.
The control circuit 112 may be formed by, for example, a dedicated circuit such as a Programmable Logic Device (PLD) including a Field Programmable Gate Array (FPGA), or an Application Specific Integrated Circuit (ASIC). Instead of this, the control circuit 112 may be formed by a combination of a general-purpose processing circuit such as a processor and a storage circuit such as a memory. In this case, the function of the control circuit 112 may be implemented when the general-purpose processing circuit executes a program stored in the storage circuit. The control circuit 112 controls a timing of accumulating electric charges in an image sensor of the radiation detecting panel 111 and a timing of reading out a signal based on the electric charges accumulated in the image sensor.
The image generation circuit 113 stores a signal supplied from the radiation detecting panel 111 in the storage device 170 (memory), and generates a radiation image based on the signal. Details of a method of generating a radiation image will be described later. The image generation circuit 113 transmits the generated radiation image to the computer 120. The image generation circuit 113 stores, in the storage device 170, a radiation image or an offset image generated based on the signal supplied from the radiation detecting panel 111. The image generation circuit 113 performs image correction processing including offset correction (to be described later) using various kinds of correction data stored in the storage device 170.
The computer 120 includes a control unit that controls the radiation imaging apparatus 110 and the exposure control apparatus 130, a reception unit that receives a radiation image from the radiation imaging apparatus 110, and a signal processing unit that processes a radiation image obtained by the radiation imaging apparatus 110. Similar to the control circuit 112, each of the control unit, the reception unit, and the signal processing unit may be formed by a dedicated circuit or a combination of a general-purpose processing circuit and a storage circuit. In an example, the exposure control apparatus 130 includes an exposure switch. When the user turns on the exposure switch, the exposure control apparatus 130 sends an exposure instruction to the radiation generating apparatus 140, and also sends a start notification indicating the start of radiation irradiation to the computer 120. In response to the start notification, the computer 120 that has received the start notification notifies the control circuit 112 of the radiation imaging apparatus 110 of the start of radiation irradiation. In a case where the exposure control apparatus 130 and the computer 120 are not synchronously connected, the radiation detecting panel 111 may detect the start of irradiation with the radiation 160 based on a pixel signal.
The respective pixel rows of the pixel array 200 will be referred to as the first row to the mth row (m is an integer of 1 or more) sequentially from the upper side of
The conversion device C generates electric charges according to radiation entering the pixel P, and accumulates the electric charges. The conversion device C can accumulate not only electric charges according to radiation but also electric charges generated by a dark current. Generation and accumulation of electric charges by the conversion device C of the pixel P will be referred to as generation and accumulation of electric charges by the pixel P hereinafter.
The switch element S is connected between the conversion device C and the signal line Sig corresponding to this conversion device C. For example, the switch elements S(1, 1) to S(m, 1) are connected between the plurality of conversion devices C(1, 1) to C(m, 1) and the signal line Sig1, respectively. When the switch element S is turned on, the conversion device C and the signal line Sig are rendered conductive, and the electric charges obtained by the conversion device C (for example, the electric charges accumulated in the conversion device C) are transferred to the signal line Sig. The conversion device C may be, for example, an MIS type photodiode arranged on an insulating substrate such as a glass substrate and made of amorphous silicon as a main material. Instead of this, the conversion device C may be a PIN type photodiode. The conversion device C may be formed as a direct type that directly converts radiation into electric charges, or formed as an indirect type that converts radiation into light and then detects the light. In the indirect type, a scintillator may be shared by the plurality of pixels P.
The switch element S is formed by, for example, a transistor such as a thin film transistor (TFT) including a control terminal (gate) and two main terminals (source and drain). The conversion device C includes two main electrodes. One main electrode of the conversion device C is connected to one of the two main terminals of the switch element S, and the other main electrode of the conversion device is connected to a bias power supply Vs via the common bias line Bs. The bias power supply Vs generates a bias voltage.
The control terminals of the switch elements S of the pixels P on the first row are connected to the driving line Vg1. The control terminals of the switch elements S of the pixels P on the second row are connected to the driving line Vg2. The same applies to the third to mth rows.
In accordance with a driving signal supplied from the control circuit 112, the driving circuit 210 supplies a driving signal to the control terminal of the switch element S of each pixel P via the driving line Vg. The driving signal includes an ON signal (to be referred to as a high-level voltage hereinafter) for turning on the switch element S, and an OFF signal (to be referred to as a low-level voltage hereinafter) for turning off the switch element S. The driving circuit 210 includes, for example, a shift register, and the shift register executes a shift operation in accordance with a control signal (for example, a clock signal) supplied from the control circuit 112.
Supply of the ON signal (that is, the high-level driving signal) to the pixel P is represented as selection of the pixel P. That is, the driving signal is a signal for selecting one of the plurality of pixels P. The same driving signal is supplied to the plurality of pixels included in the same pixel row. Selection of the plurality of pixels included in one pixel row is represented as selection of the pixel row.
The readout circuit 220 amplifies a signal that appears in the signal line Sig by selecting the pixel P, and reads out the signal. This signal is based on the electric charges accumulated in the conversion device C. Readout of the signal based on the electric charges accumulated in the conversion device C of the pixel P is represented as readout of the signal based on the electric charges accumulated in the pixel P.
The readout circuit 220 includes one amplification circuit 221 for each signal line Sig. Since the pixel array 200 includes n signal lines Sig in the example shown in
The readout circuit 220 includes a multiplexer 227 that selects signals from the plurality of amplification circuits 221 in a predetermined order and outputs them. The multiplexer 227 includes, for example, a shift register, and the shift register executes a shift operation in accordance with a control signal (for example, a clock signal) supplied from the control circuit 112. This shift operation selects one of signals from the plurality of amplification circuits 221.
The buffer circuit 230 buffers (impedance-converts) the signal output from the multiplexer 227. The A/D converter 240 converts the analog signal output from the buffer circuit 230 into a digital signal. The output from the A/D converter 240, that is, a pixel signal is transmitted to the computer 120.
The pixel P further includes an interlayer insulation film 307 that covers the insulation layer 303 and the conductive layer 306. In the interlayer insulation film 307, a contact plug 308 for connection to the conductive layer 306 (switch element S) is provided. The pixel P further includes, on the interlayer insulation film 307, a conductive layer 309, an insulation layer 310, a semiconductor layer 311, an impurity semiconductor layer 312, a conductive layer 313, a protective layer 314, an adhesive layer 315, and a scintillator 316 in this order. These layers form the indirect type conversion device C. The conductive layers 309 and 313 respectively form a lower electrode and an upper electrode of a photoelectric conversion device forming the conversion device C. The conductive layer 313 is made of, for example, a transparent material. The conductive layer 309, the insulation layer 310, the semiconductor layer 311, the impurity semiconductor layer 312, and the conductive layer 313 form a MIS type sensor as a photoelectric conversion device. The impurity semiconductor layer 312 is formed by, for example, an n-type impurity semiconductor layer. The scintillator 316 is made of, for example, a gadolinium-based material or cesium iodide (CsI) material, and converts radiation into light.
Instead of the above-described example, the conversion device C may be formed as a direct type conversion device that directly converts incident radiation into electric charges. As the direct type conversion device C, for example, there is provided a conversion device made of amorphous selenium, gallium arsenide, gallium phosphide, lead iodide, mercury iodide, CdTe, CdZnTe, or the like as a main material. The conversion device C is not limited to the MIS type, and for example, a pn type or PIN type photodiode may be used.
In the example shown in
An example of the operation of the radiation imaging system 100 will be described with reference to
In the timing chart shown in
In the timing chart shown in
In the timing chart shown in
During the readout period, the control circuit 112 selects each of the plurality of pixels P included in the pixel array 200, and reads out a signal from the selected pixel P. More specifically, the driving circuit 210 sequentially supplies an ON signal to each of the driving lines Vg1 to Vg8. First, the driving circuit 210 supplies the ON signal only to the driving line Vg1. This turns on the switch element S(1, j) (j=1, . . . , n), the conversion device C(1, j) and the signal line Sigj are rendered conductive, and thus the electric charges accumulated in the conversion device C(1, j) are read out into the signal line Sigj. Next, the driving circuit 210 supplies the ON signal only to the driving line Vg2. This turns on the switch element S(2, j), the conversion device C(2, j) and the signal line Sigj are rendered conductive, and thus the electric charges accumulated in the conversion device C(2, j) are read out into the signal line Sigj. When the driving circuit 210 repeats this operation up to the driving line Vg8, the electric charges based on those accumulated in the conversion device C are read out by the readout circuit 220 via the signal line Sigj. In the following description, execution of the readout operation for the plurality of pixels P means execution of the readout operation for each of the plurality of pixels P.
The operation by the radiation imaging apparatus 110 includes an operation executed in imaging preparation and an operation executed after imaging preparation ends. A period after imaging preparation ends may include a period during which a radiation image is captured, and may further include a period during which a moving image is captured. The period during which the radiation image is captured may be called an imaging period. As will be described later, during the imaging period, the radiation imaging apparatus 110 need not always be irradiated with the radiation 160, and may intermittently be irradiated with the radiation 160.
In imaging preparation, the radiation imaging apparatus 110 is not irradiated with the radiation 160. Imaging preparation may end when a predetermined condition is satisfied. The predetermined condition may be, for example, a condition that a predetermined number of offset images (to be described later) are generated. When imaging preparation ends, the radiation imaging apparatus 110 may notify the computer 120 that radiation irradiation is possible.
After imaging preparation ends, the radiation imaging apparatus 110 is irradiated with the radiation 160, thereby generating a radiation image corresponding to the radiation 160. As shown in
The control circuit 112 alternately executes the accumulation operation and the readout operation in imaging preparation. As shown in
During the readout period 412, a signal based on electric charges accumulated for a time length 401 is read out from the pixel P. The time length 401 is a time length from when the last readout operation of the pixel P ends (that is, the driving signal changes to low level) until the current readout operation of the pixel P ends (that is, the driving signal changes to low level again). The same applies to other time lengths for which electric charges are accumulated. The time length 401 includes the accumulation period 411. During the readout period 414, a signal based on electric charges accumulated for a time length 402 is read out from the pixel P. The time length 402 includes the accumulation period 413.
In the example shown in
The image generation circuit 113 generates a long-time offset image S based on the long-time offset signals read out from the plurality of pixels P included in the pixel array 200. The long-time offset image S is represented as a matrix of m rows and n columns, and the signal read out from the pixel P (i, j) is the (i, j) element of the matrix. The image generation circuit 113 generates a short-time offset image T based on the short-time offset signals read out from the plurality of pixels P included in the pixel array 200. The short-time offset image T is represented as a matrix of m rows and n columns, and the signal read out from the pixel P (i, j) is the (i, j) element of the matrix.
The control circuit 112 repeatedly executes the operations in the accumulation period 411 to the readout period 414. That is, the same operations as in the accumulation period 411 to the readout period 414 are executed in the accumulation period 415 to the readout period 418. In this way, the control circuit 112 alternately executes the readout operation of reading out the long-time offset signals and the readout operation of reading out the short-time offset signals in imaging preparation.
After imaging preparation ends, the control circuit 112 starts to capture a moving image (that is, a plurality of radiation images). More specifically, the control circuit 112 alternately executes the accumulation operation and the readout operation. As shown in
During the readout period 422, a signal based on electric charges accumulated for a time length 403 is read out from the pixel P. The time length 403 includes the accumulation period 421. The accumulation period 421 includes a period during which the radiation imaging apparatus 110 is irradiated with the radiation 160. Therefore, the time length 403 includes a period during which the radiation imaging apparatus 110 is irradiated with the radiation 160. The time length 403 may be equal to the time length 401. During the readout period 424, a signal based on electric charges accumulated for a time length 404 is read out from the pixel P. The time length 404 includes the accumulation period 423. The time length 404 does not include a period during which the radiation imaging apparatus 110 is irradiated with the radiation 160. The time length 404 may be equal to the time length 402.
In the example shown in
The image generation circuit 113 generates a radiation image X based on the radiation signals read out from the plurality of pixels P included in the pixel array 200. The radiation image X is represented as a matrix of m rows and n columns, and the signal read out from the pixel P (i, j) is the (i, j) element of the matrix. The image generation circuit 113 generates an imaging offset image U based on the imaging offset signals read out from the plurality of pixels P included in the pixel array 200. The imaging offset image U is represented as a matrix of m rows and n columns, and the signal read out from the pixel P (i, j) is the (i, j) element of the matrix.
The control circuit 112 repeatedly executes the operations in the accumulation period 421 to the readout period 424. That is, the same operations as in the accumulation period 421 to the readout period 424 are executed in the accumulation period 425 to the readout period 428. In this way, the control circuit 112 alternately executes the readout operation of reading out the radiation signals and the readout operation of reading out the imaging offset signals after imaging preparation ends (for example, in capturing a moving image).
Subsequently, a method in which the image generation circuit 113 corrects the radiation image X using the long-time offset image S, the short-time offset image T, and the imaging offset image U will be described. As described above, components of the long-time offset image S, the short-time offset image T, the imaging offset image U, and the radiation image X are respectively given by the long-time offset signal, the short-time offset signal, the imaging offset signal, and the radiation signal. In the following method, the radiation signal is corrected using the long-time offset signal, the short-time offset signal, and the imaging offset signal.
As described above, in imaging preparation, the control circuit 112 alternately executes generation of the long-time offset image S and generation of the short-time offset image T. This generates the plurality of long-time offset images S and the plurality of short-time offset images T. In imaging preparation, the image generation circuit 113 creates one long-time offset image S by averaging the plurality of long-time offset images S, and stores the created image in the memory of the image generation circuit 113 for subsequent processing. Similarly, in imaging preparation, the image generation circuit 113 creates one short-time offset image T by averaging the plurality of short-time offset images T, and stores the created image in the memory of the image generation circuit 113 for subsequent processing. By averaging the plurality of offset images in this way, noise included in the offset image can be reduced. The number of offset images used for averaging may be two, as shown in
After imaging preparation ends, the image generation circuit 113 generates the radiation image X and the imaging offset image U, and stores them in the memory of the image generation circuit 113. The image generation circuit 113 reads out the long-time offset image S from the memory, and subtracts the long-time offset image S from the radiation image X, thereby generating a radiation afterimage (“X−S” in
An afterimage component included in each of the radiation afterimage and the offset afterimage is proportional to a time length for which electric charges are accumulated in the pixel P. The image generation circuit 113 generates an adjustment afterimage (“k(U−T)” in
The above-described calculation order for generating the radiation image X′ is merely an example, and calculation may be performed in another order. The radiation image X′, that is, X−S−k(U−T) is changed to X−kU+(KT−S). In imaging preparation, the image generation circuit 113 may calculate kT−S using the long-time offset image S, the short-time offset image T, and the coefficient k, and store the value as a correction value in the memory of the image generation circuit 113. The coefficient k can be decided based on the preset of a timing at which the driving circuit 210 supplies the ON signal to the pixel array 200. In capturing a moving image, the image generation circuit 113 may correct the radiation image X using the imaging offset image U, the correction value stored in the memory, and the coefficient k. In this way, by storing the correction value instead of storing the long-time offset image S and the short-time offset image T, it is possible to reduce the memory consumption of the image generation circuit 113.
Subsequently, the technical significance to alternately execute obtaining of the long-time offset image S and obtaining of the short-time offset image T will be described. The driving lines Vg1 to Vgm have various capacitive couplings in the pixel array 200. For example, the driving line Vg2 intersects the signal lines Sig1 to Sign at a plurality of positions of the pixel array 200, and has capacitive coupling at each intersection. Since the driving line Vg2 extends in parallel to the driving line Vg3, it also has capacitive coupling with the driving line Vg3. Since the driving line Vg2 extends in parallel to part of the bias line Bs, it also has capacitive coupling with the bias line Bs. Furthermore, the driving line Vg2 has capacitive coupling with a node of a connecting portion between the switch element S and the conversion device C.
These capacitive couplings change the level of the driving signal supplied to the driving line Vg, and thus the potentials of the signal line Sig, the bias line Bs, other driving lines Vg, and the node of the connecting portion between the switch element S and the conversion device C also change. The signal line Sig, the bias line Bs, other driving lines Vg, and the node of the connecting portion between the switch element S and the conversion device C whose potentials have changed return to the original potentials with time. However, the return amount is different depending on the length of the accumulation period.
Even if the switch element S is in the OFF state, a leakage current may flow. When the switch element S is turned off, the node between the conversion device C and the switch element S changes to the low level side due to injection of electric charges from the control terminal (gate). Therefore, immediately after the switch element S is turned off, a potential difference is generated between the main terminals (source and drain) to cause a leakage current to flow. The leakage current depends on the potential difference between the two main terminals (source and drain) of the switch element. If a leakage current flows during the accumulation period, the potential difference becomes small, and thus the leakage current is different depending on the length of the accumulation period. If the leakage current flows to the switch element S, a current also flows to the signal line Sig and the bias line Bs.
For the above reasons, obtained offset images may be different between a case where the long-time offset image S and the short-time offset image T are continuously obtained a plurality of times and a case where the long-time offset image S and the short-time offset image T are alternately obtained. In the above-described operation of the radiation imaging apparatus 110, the long-time offset image S and the short-time offset image T are alternately obtained in imaging preparation, and the radiation image X and the imaging offset image U are alternately obtained after imaging preparation ends. This can make the state of the capacitive coupling in the pixel array 200 in imaging preparation close to the state of the capacitive coupling in the pixel array 200 in capturing a radiation image. Therefore, it is possible to accurately reduce noise included in the radiation image X.
In the operation shown in
In the above-described example, the time length 401 is equal to the time length 403. Instead of this, these time lengths may be different from each other. In a case where the time lengths are different from each other, the image generation circuit 113 may multiply each element of the long-time offset image S by the ratio of the time length 403 to the time length 401, and then subtract the resultant from the radiation image X. In the above-described example, the time length 402 is equal to the time length 404. Instead of this, these time lengths may be different from each other. In a case where the time lengths are different from each other, the image generation circuit 113 may multiply each element of the short-time offset image T by the ratio of the time length 404 to the time length 402, and then subtract the resultant from the imaging offset image U.
Subsequently, an example of the operation of the radiation imaging apparatus 110 different from the above-described operation shown in
For example, the control circuit 112 selects the first pixel row and the second pixel row during a period (that may be referred to as the first pixel row selection period) in which the driving signal supplied to the driving line Vg1 is at high level in the readout period 424. This reads out imaging offset signals based on electric charges accumulated in the pixel P(1, j) and electric charges accumulated in the pixel P(2, j).
By reading out the imaging offset signal by the binning operation, it is possible to shorten the readout period (for example, the readout period 424) for reading out the imaging offset signal. As a result, it is possible to improve the frame rate of a moving image. The accumulation period 423 may be shorter than the accumulation period 421 or may be equal to the accumulation period 421. Even if the length of the accumulation period 423 is equal to that of the accumulation period 421, it is possible to improve the frame rate of a moving image by reading out the imaging offset signals by the binning operation. Since the imaging offset signals are read out by the binning operation, short-time offset signals to be used as differences from the imaging offset signals may be read out by the binning operation. Instead of this, the short-time offset signal may be read out by a normal operation (selection of one row). In this case, the short-time offset signal may be multiplied by the coefficient for adjusting the time length for which electric charges are accumulated in the pixel P.
In the operation shown in
Subsequently, a radiation image generation method in the operation shown in
After that, the image generation circuit 113 generates the short-time offset image T by adjusting the size of the short-time offset image T′ to be equal to the size of the radiation image X. More specifically, the image generation circuit 113 sets, as the (i, j) element (i=1, . . . , m, j=1, . . . , n) of the short-time offset image T, a value obtained by multiplying the (Ceiling (i/2), j) element of the short-time offset image T′ by ½. Ceiling represents a ceiling function, that is, round-up of digits after the decimal point. The reason why the element is multiplied by ½ is that each element of the short-time offset image T′ represents the sum of the signals of two pixels.
After that, as in the explanation of
The image generation circuit 113 generates the radiation image X′ by correcting the radiation image X using the thus generated long-time offset image S, short-time offset image T, and imaging offset image U. The correction processing of the radiation image X may be the same as correction processing 400 shown in
The adjustment of the size of the offset image may be performed in another order. For example, the image generation circuit 113 may generate the adjustment image of the correction processing 400 without adjusting the size of the offset image, and then adjust the size of the adjustment image.
As shown in
The image generation circuit 113 may use an individual coefficient k for each pixel row in the correction processing 400. More specifically, the image generation circuit 113 may use the ratio of the time length 503 to the time length 504 as the coefficient k with respect to the pixel P included in the first pixel row. The image generation circuit 113 may use the ratio of the time length 507 to the time length 508 as the coefficient k with respect to the pixel P included in the eighth pixel row.
With respect to each of the plurality of pixel rows, the length of the accumulation time of the electric charges read out as a long-time offset signal may be equal to the length of the accumulation time of the electric charges read out as a radiation signal. For example, with respect to the first pixel row, a time length 501 may be equal to the time length 503 and a time length 502 may be equal to the time length 504. With respect to the eighth pixel row, a time length 505 may be equal to the time length 507 and a time length 506 may be equal to the time length 508.
Subsequently, an example of the operation of the radiation imaging apparatus 110 different from the above-described operation shown in
In the operation shown in
Subsequently, an example of the operation of the radiation imaging apparatus 110 different from the above-described operation shown in
First, an operation in imaging preparation will be described. An operation in an accumulation period 711 to an accumulation period 713 and an operation in an accumulation period 715 to an accumulation period 717 may be the same as the operation in the accumulation period 411 to the accumulation period 413 in
Similar to the operation shown in
Subsequently, an operation after imaging preparation ends (for example, in capturing a moving image) will be described. An operation in a readout period 721 to a readout period 727 may be the same as the operation in the readout period 712 to the readout period 718 and a description thereof will be omitted.
Similar to the operation shown in
After that, the image generation circuit 113 generates the radiation image X′ by correcting the radiation image X using the thus generated long-time offset image S, short-time offset image T, and imaging offset image U. The correction processing of the radiation image X may be the same as the correction processing 400 shown in
In the above-described first embodiment, the pixel array 200 includes only the pixels P to be used to generate a radiation image. Instead of this, the pixel array 200 may include pixels to be used for the purpose other than generation of a radiation image, like pixels to be used for automatic exposure control. According to the first embodiment, it is possible to accurately reduce noise in a radiation image.
The offset image generation processing will be described below with reference to a timing chart 310 and a correction processing procedure 320 shown in
In the timing chart 310 shown in
In the timing chart 310 shown in
During the readout period, the control circuit 112 selects each of the plurality of pixels P included in the pixel array 200, and reads out a signal from the selected pixel P. More specifically, the driving circuit 210 sequentially supplies an ON signal to each of the driving lines Vg1 to Vgm. First, the driving circuit 210 supplies the ON signal only to the driving line Vg1. This turns on a switch element S(1, j) (j=1, . . . , n), a conversion device C(1, j) and a signal line Sigj are rendered conductive, and thus electric charges accumulated in the conversion device C(1, j) are read out into the signal line Sigj. Next, the driving circuit 210 supplies the ON signal only to the driving line Vg2. This turns on a switch element S(2, j), a conversion device C(2, j) and the signal line Sigj are rendered conductive, and thus electric charges accumulated in the conversion device C(2, j) are read out into the signal line Sigj. When the driving circuit 210 repeats this operation up to the driving line Vgm, the electric charges based on those accumulated in the conversion device C are read out by a readout circuit 220 via the signal line Sigj. In the following description, execution of the readout operation for the plurality of pixels P means execution of the readout operation for each of the plurality of pixels P. Offset image generation processing to be described in the following example is performed in imaging preparation, and is performed in periods 301 to 308 shown in
In imaging preparation, the control circuit 112 alternately executes an accumulation operation and a readout operation in a state in which radiation irradiation is not performed. As shown in
In the example shown in
A signal read out during the readout period 302 or 306 is represented as a long-time offset signal (to be also referred to as the first signal or the first offset signal hereinafter), and a signal read out during the readout period 304 or 308 is represented as a short-time offset signal (to be also referred to as the second signal or the second offset signal hereinafter). In the state in which radiation irradiation is not performed, the control circuit 112 alternately executes the first readout control of reading out the first signal based on the electric charges accumulated during the accumulation period 301 or 305 (first period) and the second readout control of reading out the second signal based on the electric charges accumulated during the accumulation period 303 or 307 (second period) shorter than the first period.
An offset image generated based on the long-time offset signal (first signal) is represented as a long-time offset image (to be also referred to as the first offset image hereinafter), and an offset image generated based on the short-time offset signal (second signal) is represented as a short-time offset image (to be also referred to as the second offset image hereinafter).
In the following description, a long-time offset image obtained when a frame counter is set to N is represented by “S.N”, and a short-time offset image is represented by “T.N”. For example, a long-time offset image obtained when the frame counter is set to N=1 is represented by “S.1”, and a short-time offset image is represented by “T.1”.
In step S401, the control circuit 112 sets the frame counter N to 0. After that, in step S402, the control circuit 112 increments the frame counter N by adding 1 to the frame counter N.
In step S403, the long-time offset image S.1 is obtained. The operation of obtaining the long-time offset image S.1 includes the accumulation operation executed during the accumulation period 301 of
As a practical operation, during the accumulation period 301, the radiation imaging apparatus 110 performs an electric charge accumulation operation in all the pixels P (all image sensors) included in the pixel array 200 of the radiation detecting panel 111 in a state in which irradiation with the radiation 160 is not performed, as indicated by “radiation” in the timing chart 310 shown in
In step S404, the short-time offset image T.1 is obtained. The operation of obtaining the short-time offset image T.1 includes the accumulation operation executed during the accumulation period 303 of
During the accumulation period 303 shorter than the accumulation period 301, the radiation imaging apparatus 110 performs an electric charge accumulation operation in all the pixels P (all the image sensors) included in the pixel array 200 of the radiation detecting panel 111 in a state in which the radiation imaging apparatus 110 is not irradiated with the radiation 160. After that, in the readout operation executed during the readout period 304, the control circuit 112 controls the radiation detecting panel 111 to output a signal (electrical signal) based on the electric charges accumulated during the accumulation period 303, and the image generation circuit 113 generates image data based on the signal (electrical signal) obtained from the radiation detecting panel 111. The image generation circuit 113 stores the generated image data as the short-time offset image T.1 in the storage device 170.
After that, in step S405, the control circuit 112 determines whether the frame counter N has reached a predetermined number. As an example, a case where the predetermined number is two will be described. If it is determined in step S405 that the frame counter N has not reached the predetermined number (NO in step S405), the process is returned to step S402. That is, if the frame counter is N=1, the frame counter N has not reached the predetermined number, and thus the control circuit 112 returns the process to step S402.
After that, in step S402, the control circuit 112 increments the frame counter N by adding 1 to the frame counter N, and advances the process to step S403.
In step S403, a long-time offset image S.2 is obtained. The operation of obtaining the long-time offset image S.2 includes the accumulation operation executed during the accumulation period 305 of
The accumulation operation executed during the accumulation period 305 and the readout operation executed during the readout period 306 are respectively the same as the electric charge accumulation operation during the accumulation period 301 and the readout operation of the signal based on the electric charges during the readout period 302 when generating the long-time offset image S.1. The control circuit 112 controls the radiation detecting panel 111 to output the signal (electrical signal) based on the electric charges accumulated during the accumulation period 305, and the image generation circuit 113 generates image data based on the signal (electrical signal) obtained from the radiation detecting panel 111. The image generation circuit 113 stores the generated image data as the long-time offset image S.2 in the storage device 170. Thus, the storage device 170 stores the long-time offset images S.1 and S.2.
After that, in step S404, a short-time offset image T.2 is obtained. The operation of obtaining the short-time offset image T.2 includes the accumulation operation executed during the accumulation period 307 of
The accumulation operation executed during the accumulation period 307 and the readout operation executed during the readout period 308 are respectively the same as the electric charge accumulation operation during the accumulation period 303 and the readout operation of the signal based on the electric charges during the readout period 304 when generating the short-time offset image T.1. The control circuit 112 controls the radiation detecting panel 111 to output the signal (electrical signal) based on the electric charges accumulated during the accumulation period 307, and the image generation circuit 113 generates image data based on the signal (electrical signal) obtained from the radiation detecting panel 111. The image generation circuit 113 stores the generated image data as the short-time offset image T.2 in the storage device 170. Thus, the storage device 170 stores the short-time offset images T.1 and T.2.
In step S405, the control circuit 112 determines again whether the frame counter N has reached the predetermined number. Assume here that the predetermined number is two. Therefore, the control circuit 112 determines that the frame counter N has reached the predetermined number (YES in step S405), and advances the process to step S406.
In step S406, the image generation circuit 113 performs processing for generating a long-time offset image S. The image generation circuit 113 generates the long-time offset image S by performing addition and averaging of the images from the long-time offset image S. 1 to the long-time offset image S.N (in this example, N=2) stored in the storage device 170. The image generation circuit 113 stores the generated long-time offset image S in the storage device 170.
Subsequently, in step S407, the image generation circuit 113 performs processing for generating a short-time offset image T. The image generation circuit 113 generates the short-time offset image T by performing addition and averaging of the images from the short-time offset image T.1 to the short-time offset image T.N (in this example, N=2) stored in the storage device 170. The image generation circuit 113 stores the generated short-time offset image T in the storage device 170.
Then, the processing for generating the offset image to be used for image processing of a radiation image ends. As described above, in imaging preparation, the control circuit 112 alternately executes generation of the long-time offset image S and generation of the short-time offset image T. This generates the plurality of long-time offset images S and the plurality of short-time offset images T. In imaging preparation, the image generation circuit 113 creates one long-time offset image S by averaging (performing addition and averaging) the plurality of long-time offset images S.i (i=1 to N), and stores the created image in the storage device 170 for subsequent processing. Similarly, in imaging preparation, the image generation circuit 113 creates one short-time offset image T by averaging (performing addition and averaging) the plurality of short-time offset images T.i (i=1 to N), and stores the created image in the storage device 170 for subsequent processing. By averaging the plurality of offset images in this way, it is possible to reduce noise included in the offset image.
Note that in the example described with reference to
In step S501 of
Subsequently, in step S502, the control circuit 112 initializes a parameter F representing the number of captured images to 0. In step S503, the control circuit 112 adds 1 to the parameter F representing the number of captured images.
In step S504, the control circuit 112 and the image generation circuit 113 perform processing for generating a radiation image X. The processing for generating the radiation image X includes an accumulation operation executed during an accumulation period 309 of
The accumulation operation during the accumulation period 309 is performed in a state in which irradiation with radiation 160 is performed, as indicated by “radiation” in the timing chart 310 shown in
During the readout period 310, the control circuit 112 executes the third readout control of reading out, as the third signal, a radiation signal based on electric charges accumulated during the accumulation period 309 (third period) having the time length equal to that of the accumulation period 301 or 305 (first period) in the state in which radiation irradiation is performed. In the readout operation executed during the readout period 310, the control circuit 112 controls the radiation detecting panel 111 to output a signal (electrical signal) based on the electric charges accumulated during the accumulation period 309. The image generation circuit 113 generates the radiation image X based on the signal (electrical signal) output from the radiation detecting panel 111, and stores the generated image in the storage device 170. Note that the readout operation executed by the control circuit 112 during the readout period 310 is the same as the readout operation executed during the readout period 302 or 306 to obtain the long-time offset image S in imaging preparation.
In step S505, the control circuit 112 and the image generation circuit 113 perform processing for generating an imaging offset image U. The processing for generating the imaging offset image U includes an accumulation operation executed during an accumulation period 311 shown in
The accumulation operation during the accumulation period 311 is performed in the state in which irradiation with the radiation 160 is not performed, as indicated by “radiation” in the timing chart 310 shown in
During the readout period 312, the control circuit 112 executes the fourth readout control of reading out, as an imaging offset signal (to be also referred to as the fourth signal hereinafter), a signal based on electric charges accumulated during the accumulation period 311 (fourth period) in the state in which radiation irradiation is not performed after reading out the radiation signal (third signal) during the readout period 310. In the readout operation executed during the readout period 312, the control circuit 112 controls the radiation detecting panel 111 to output a signal (electrical signal) based on the electric charges accumulated during the accumulation period 311.
The image generation circuit 113 generates the imaging offset image U based on the imaging offset signal (fourth signal) output from the radiation detecting panel 111, and stores the generated image in the storage device 170. Note that the readout operation executed by the control circuit 112 during the readout period 312 is the same as the readout operation executed during the readout period 304 or 308 to obtain the short-time offset image T in imaging preparation. Note also that since the short-time offset image T obtained in imaging preparation is generated by performing addition and averaging of the plurality of short-time offset images T.N, noise included in the image is reduced. However, since only one imaging offset image U is used, noise included in the image may be large, as compared with the short-time offset image T.
In step S506, the image generation circuit 113 performs processing for generating a radiation afterimage. The image generation circuit 113 reads out the radiation image X and the long-time offset image S (first offset image) stored in the storage device 170, and subtracts the long-time offset image S (first offset image) from the radiation image X, thereby generating a radiation afterimage (“X−S” in
Subsequently, in step S507, the image generation circuit 113 performs processing for generating an offset afterimage. The image generation circuit 113 reads out the imaging offset image U and the short-time offset image T (second offset image) stored in the storage device 170, and subtracts the short-time offset image T (second offset image) from the imaging offset image U, thereby generating an offset afterimage (“U−T” in
After that, in step S508, the control circuit 112 determines whether the parameter F representing the number of captured images is 1. If it is determined that the parameter F is 1 (YES in step S508), the control circuit 112 advances the process to step S509. If it is determined that the parameter F is not 1 (NO in step S508), the control circuit 112 advances the process to step S510.
In step S509, the image generation circuit 113 performs calculation processing of a correction coefficient k for each pixel region including at least one pixel in the offset afterimage (U−T). The pixel region will also be referred to as a region of interest (to be referred to as an ROI) hereinafter, and the image generation circuit 113 performs calculation processing of the correction coefficient k for each ROI.
The image generation circuit 113 sets the correction coefficient for each region of interest (ROI) based on the result of determining whether the absolute value of the pixel average value for each region of interest (ROI) exceeds the threshold th1. For the ROI determined as an ROI where the absolute value of the pixel average value exceeds the predetermined threshold th1 and an afterimage is generated (an afterimage component is included), the image generation circuit 113 sets the correction coefficient k (to be described later) to be larger than zero (0), and sets the correction coefficient k to become larger as the absolute value of the pixel average value increases. On the other hand, for the ROI determines as an ROI where the absolute value of the pixel average value for each region of interest (ROI) is smaller than the predetermined threshold th1 and no afterimage is generated (no afterimage component is included), the image generation circuit 113 sets the correction coefficient k to zero (0).
After that, in step S510, the image generation circuit 113 performs processing for generating a radiation image by correcting the radiation image X. A radiation image X′ obtained by correcting the radiation image X will also be referred to as a corrected radiation image X′ hereinafter. In this step, the image generation circuit 113 sets a different correction coefficient k for each of the pixel region (ROI) including the afterimage component and the pixel region (ROI) including no afterimage component, which are determined by comparing the statistical information of the pixel values obtained for each pixel region (ROI) with the threshold, and then generates a magnification correction image by correcting the pixel values for each pixel region using the set different correction coefficient k. The image generation circuit 113 generates a magnification correction image (k(U−T) in
After that, the image generation circuit 113 subtracts the offset afterimage (magnification correction image k(U−T)) having undergone the magnification correction processing from the radiation afterimage (X−S) generated in step S506, thereby generating the corrected radiation image (X′=(X−S)−k(U−T) in
In the processing for generating the corrected radiation image X′, the image generation circuit 113 sets the correction coefficient k to zero (0) for the ROI determined as an ROI where no afterimage is generated. Therefore, in the region 601, 603, or 604 of interest (ROI) as a non-afterimage region, by performing the magnification correction processing using the correction coefficient k set to zero (0), the corrected radiation image X′ is generated by calculating X′=X−S. That is, the corrected radiation image X′ is an image obtained by subtracting the long-time offset image S from the radiation image X before correction. Therefore, in the non-afterimage region, noise is not increased by using the imaging offset image U in the processing for generating the corrected radiation image X′.
On the other hand, in the region of interest (ROI) 602 where an afterimage is generated, the correction coefficient k is set to be larger than zero (0), and the corrected radiation image X′ is generated by calculating X′=(X−S)−k(U−T). In the afterimage region, noise can be increased by using the imaging offset image U in the processing for generating the corrected radiation image X′, but a remaining afterimage component can be reduced only in the radiation afterimage (X−S). In this way, while reducing an afterimage component in the ROI where an afterimage is generated, it is possible to generate the corrected radiation image X′ in which an increase in noise is suppressed in the ROI where no afterimage is generated. The image generation circuit 113 transmits the generated corrected radiation image X′ to the PC 120.
After that, in step S511, the control circuit 112 determines whether to continue imaging. In an example, the exposure control apparatus 130 includes an exposure switch (not shown). When the user turns off the exposure switch, the exposure control apparatus 130 sends an exposure stop instruction to the radiation generating apparatus 140, and also sends a stop notification indicating the stop of radiation irradiation to the PC 120. In response to the stop notification, the PC 120 that has received the stop notification notifies the control circuit 112 of the radiation imaging apparatus 110 of the stop of radiation irradiation. The control circuit 112 confirms the presence/absence of an imaging end request from the PC 120. If an imaging end request is sent (YES in step S511), the control circuit 112 ends image processing at the time of radiation imaging. On the other hand, if an imaging end request is not sent to capture a plurality of frames like moving image capturing (NO in step S511), the control circuit 112 returns the process to step S503 again, and repeats the same processing. If imaging is continued, the control circuit 112 and the image generation circuit 113 perform the same processing in an accumulation period 313 (third period), a readout period 314, an accumulation period 315 (fourth period), and a readout period 316.
After that, the processes in steps S503 to S507 are repeated again, and the control circuit 112 determines, in step S508, whether the parameter F representing the number of captured images is 1. Since the number of captured images is not 1 at this time (NO in step S508), the control circuit 112 advances the process to step S510. That is, with respect to the second frame and subsequent frames, the image generation circuit 113 performs magnification correction processing using the correction coefficient k calculated for the first frame (F=1:first frame) in the magnification correction processing in step S510. When capturing radiation images by moving image capturing, the image generation circuit 113 corrects radiation images obtained in the second frame and subsequent frames following the first frame using the correction coefficient k calculated for the first frame of moving image capturing. When capturing a moving image, the image generation circuit 113 calculates the correction coefficient k for the first frame of the moving image, and generates a magnification correction image (k(U−T) using an offset afterimage (U−T) obtained in each frame and the correction coefficient k calculated for the first frame with respect to each frame following the first frame. Then, the image generation circuit 113 generates the corrected radiation image X′ by subtracting the magnification correction image (k(U−T) from the radiation afterimage (X−S) obtained in each frame.
Although the calculation processing of the correction coefficient k requires high performance of the image generation circuit 113, a change in afterimage characteristic is small within a short time, and thus the afterimage can be reduced even by using, for the second frame and the subsequent frames, the correction coefficient k calculated for the first frame for the first time. In this way, it is possible to perform accurate afterimage correction while suppressing an increase in noise. This can reduce the calculation load of the correction coefficient k, and attempt to increase the speed of the processing for generating the corrected radiation image X′.
Note that in steps S509 and S510, the example of dividing the offset afterimage (U−T) into four pixel regions (ROIs) has been described. The present disclosure, however, is not limited to this, and the division number of the offset afterimage may be 1 (that is, no division) or equal to the number of pixels P of the radiation detecting panel 111. That is, the ROI need only include at least one pixel. For example, if the division number is equal to the number of pixels P of the radiation detecting panel 111, the image generation circuit 113 calculates the correction coefficient k for each pixel P.
Furthermore, a method of dividing the offset afterimage is not limited to a method of dividing the offset afterimage so that divided ROIs are adjacent to each other, and the ROIs may be separated from each other.
Furthermore, the control circuit 112 may switch the selection (the setting of the position) of the ROI for which the correction coefficient k is calculated, and the number (division number) of ROIs in accordance with an imaging technique or a captured portion. In this case, the user designates an imaging technique or a captured portion by an input from the input device 115 connected to the PC 120, and the PC 120 transmits the information of the imaging technique or the captured portion to the control circuit 112. The control circuit 112 sets the selection (the setting of the position) of the ROI and the number (division number) of ROIs based on the received information of the imaging technique or the captured portion. For example, if the captured portion is the stomach, the dividing method or the selection of an ROI for which the correction coefficient k is calculated is switched, and the center of the radiation detecting panel 111 may be set as an ROI for which the correction coefficient k is calculated. The control circuit 112 notifies the image generation circuit 113 of the information concerning the division method (division number) or the selection (the setting of the position) of an ROI, that has been notified from the PC 120. The image generation circuit 113 switches the dividing method or the selection of an ROI based on the setting of the control circuit 112.
In the second embodiment, in step S509, the image generation circuit 113 calculates, as the statistical information of each ROI, the absolute value of the pixel average value for each ROI of the offset afterimage, and adjusts the correction coefficient k for each ROI based on a result of comparing the absolute value of the pixel average value with the threshold th1. However, the correction coefficient k may be decided using other statistical information obtained by statistical processing of the pixel values. For example, the correction coefficient k may be decided based on statistical information such as the maximum pixel value, the minimum pixel value, or the standard deviation of the pixel values for each ROI of the offset afterimage. The image generation circuit 113 obtains the statistical information of the pixel values by performing statistical processing for the pixel values in the offset afterimage, and the statistical information includes at least one of the absolute value of the pixel average value, the maximum pixel value, the minimum pixel value, and the standard deviation of the pixel values, which are obtained for each pixel region (ROI) of the offset afterimage.
The second embodiment has exemplarily explained the processing that limits the calculation of the correction coefficient k for each ROI in step S509 to the first frame of a captured radiation image based on the relationship between the afterimage characteristic and the performance of the image generation circuit 113. However, the present disclosure is not limited to this and the correction coefficient k may be calculated for each ROI in all the frames. For example, the image generation circuit 113 may perform the calculation processing of the correction coefficient k for each ROI in step S509 in all the frames, and then perform the processing for generating the corrected radiation image X′ in step S510, without performing the determination processing of step S508.
In this case, as a further different operation, the efficiency of calculation processing of the correction coefficient k may be improved, as illustrated in a flowchart shown in
In step S901, the control circuit 112 confirms the presence/absence of an imaging start request from the PC 120. This processing is the same as that in step S501 of
In step S902, the control circuit 112 resets an internal estimation sampling counter n to 0. The control circuit 112 includes a memory (not shown), and can store the setting of the estimation sampling counter n. In this step, the control circuit 112 resets the setting of the estimation sampling counter n stored in the memory (not shown).
In step S903, the control circuit 112 increments the estimation sampling counter n.
Processes of steps S904 to S906 are the same as those of step S504 (the processing for generating the radiation image X), step S505 (the processing for generating the imaging offset image U), and step S506 (the processing for generating the radiation afterimage (X−S)) of
In step S907, the image generation circuit 113 performs the processing for generating the offset afterimage (U−T). The processing of the image generation circuit 113 in this step includes the processing of step S507 of
The calculation processing of the correction coefficient k in step S908 and the processing for generating the corrected radiation image X′ in step S909 are the same as those of steps S509 and S510 of
Processing of determining in step S910 whether to continue imaging is the same as that in step S511 of
In step S911, the control circuit 112 determines whether the estimation sampling counter n has reached a predetermined number N. If it is determined that the estimation sampling counter n has not exceeded the predetermined number N (NO in step S911), the control circuit 112 returns the process to step S903 and repeats the processes in step S903 and the subsequent steps. On the other hand, if it is determined, in the determination processing of step S911, that the estimation sampling counter n has reached the predetermined number N (YES in step S911), the control circuit 112 advances the process to step S912.
In step S912, the image generation circuit 113 generates an average offset afterimage by averaging the pixel values of a plurality of offset afterimages obtained in advance by continuing imaging. The image generation circuit 113 reads out several latest offset afterimages (U−T) that have been stored in the storage device 170 in step S907, and averages the pixel values of the readout several latest offset afterimages (U−T), thereby generating an average offset afterimage as an average image of the offset afterimages (U−T).
In step S913, the image generation circuit 113 adjusts the correction coefficient k with respect to the afterimage amount of the average offset afterimage generated in step S912 by the same method as in step S509 of
Processes (processes in steps S914 to S917) of newly obtaining various kinds of images by continuing imaging are the same as those of step S904 (the processing for generating the radiation image X), step S905 (the processing for generating the imaging offset image U), step S906 (the processing for generating the radiation afterimage (X−S)), and step S907 (the processing for generating the offset afterimage (U−T)).
In step S918, the image generation circuit 113 calculates a difference in average pixel value between the offset afterimage (U−T) and the average offset afterimage. The image generation circuit 113 calculates the difference (the absolute value of the difference) between the average pixel value for each ROI of the offset afterimage (U−T) generated in step S917 and the average pixel value for each ROI of the average offset afterimage generated in step S912. The image generation circuit 113 changes the correction coefficient k to be used for the processing for generating a magnification correction image by comparing, with a predetermined value, the difference between the average pixel value for each pixel region in the offset afterimage and the average pixel value for each pixel region in the average offset afterimage.
In step S919, the image generation circuit 113 determines whether the difference (the absolute value of the difference) for each ROI, which has been calculated in step S918, exceeds the predetermined value. If the difference (the absolute value of the difference) exceeds the predetermined value in one ROI (NO in step S919), the image generation circuit 113 advances the process to step S923. On the other hand, if it is determined, in the determination processing of step S919, that the difference (the absolute value of the difference) does not exceed the predetermined value in any of the ROIs (YES in step S919), the image generation circuit 113 advances the process to step S920. If it is determined, in the determination processing of step S919, that the difference (the absolute value of the difference) between the average pixel value for each ROI and the average pixel value for each ROI of the average offset afterimage, which has been calculated in step S918, does not exceed the predetermined value, there is no large change in the characteristic of the afterimage. In this case, when the difference (the absolute value of the difference) does not exceed the predetermined value, the image generation circuit 113 generates a magnification correction image using the correction coefficient k calculated for each pixel region in the average offset afterimage, and subtracts the magnification correction image (k(U−T)) from the radiation afterimage X newly obtained by continuing imaging, thereby generating the corrected radiation image X′.
In step S920, the image generation circuit 113 decides, as the correction coefficient k for each ROI to be used for the processing in step S921, the correction coefficient k of the average offset afterimage calculated in step S913.
In step S921, the image generation circuit 113 performs magnification correction processing using the correction coefficient k decided in step S920. Then, the image generation circuit 113 generates a corrected radiation image (X′=(X−S)−k(U−T)) by subtracting the offset afterimage (magnification correction image k(U−T)) having undergone the magnification correction processing from the radiation afterimage (X−S) generated in step S916. The image generation circuit 113 transmits the generated corrected radiation image X′ to the PC 120.
Then, in step S922, the control circuit 112 performs the same processing of determining whether to continue imaging as that in step S910. If it is determined to continue imaging (YES in step S922), the control circuit 112 returns the process to step S914 and repeats the same processing. On the other hand, if it is determined not to continue imaging (NO in step S922), the control circuit 112 ends the image processing at the time of radiation imaging.
In this way, in a case where there is no large change in the characteristic of an afterimage, it is possible to reduce the afterimage using even the correction coefficient k calculated in step S913. Therefore, it is possible to improve the efficiency of calculation processing by omitting calculation of the correction coefficient k.
On the other hand, if it is determined, in the determination processing of step S919, that the difference (the absolute value of the difference) calculated in step S918 exceeds the predetermined value (NO in step S919), such large change that the predetermined value is exceeded occurs in the characteristic of the afterimage in the middle of imaging. In this case, the image generation circuit 113 advances the process to step S923. In subsequent processing, if the difference (the absolute value of the difference) exceeds the predetermined value, the image generation circuit 113 generates the magnification correction image (k(U−T)) using the correction coefficient k recalculated for each pixel region in the offset afterimage (U−T) newly obtained by continuing imaging, and subtracts the magnification correction image (k(U−T)) from the radiation afterimage (X−S) newly obtained by continuing imaging, thereby generating the corrected radiation image X′.
In step S923, the image generation circuit 113 recalculates the correction coefficient k. When performing recalculation, the image generation circuit 113 calculates the correction coefficient k by the same calculation processing as that in step S908 using the offset afterimage (U−T) generated in step S917. The image generation circuit 113 performs calculation processing of the correction coefficient for each region of interest (ROI) using the offset afterimage (U−T) generated in step S917.
In step S924, the image generation circuit 113 performs magnification correction processing using the correction coefficient k calculated in step S923. Then, the image generation circuit 113 generates the corrected radiation image X′(X′=(X−S)−k(U−T)) by subtracting the offset afterimage (magnification correction image k(U−T)) having undergone the magnification correction processing from the radiation afterimage (X−S) generated in step S916. The image generation circuit 113 transmits the generated corrected radiation image X′ to the PC 120. After that, the process returns to step S902 again to perform the same processing. In the processing described with reference to
The third embodiment of the present disclosure will be described next. The third embodiment is different from the second embodiment in that smoothing processing of the correction coefficient is performed after calculation processing of a correction coefficient k for each ROI, which has been described in step S509 of
In step S509 of the second embodiment, the calculation processing of the correction coefficient k for each ROI is performed, thereby deciding the correction coefficient k. However, when a difference in the correction coefficient k between adjacent ROIs is larger than a predetermined value, the difference in the correction coefficient k may cause a case where a step that can visually be perceived is generated at the boundary between the ROIs in the corrected radiation image X′ generated in step S511.
In the third embodiment, to suppress the generation of a step at the boundary between ROIs, after calculation processing of the correction coefficient k for each ROI, an image generation circuit 113 compares the correction coefficients k calculated for the respective ROIs, and performs, if the difference in the correction coefficient k between adjacent ROIs exceeds a predetermined value (second threshold), correction processing (smoothing processing of the correction coefficient k) of smoothing the correction coefficient k between the adjacent ROIs. That is, if the difference between the correction coefficients of adjacent pixel regions among a plurality of pixel regions (ROIs) exceeds the predetermined value (second threshold), the image generation circuit 113 performs smoothing processing for the correction coefficients of the adjacent pixel regions so that the difference between the correction coefficients becomes smaller than the predetermined value (second threshold).
On the left side of
By the smoothing processing of the correction coefficient k, a smoothing correction amount 1001 is added to the correction coefficient k of the ROI 601 obtained by the calculation processing. Furthermore, a smoothing correction amount 1002 is subtracted from the correction coefficient k of the ROI 602 obtained by the calculation processing. A smoothing correction amount 1003 is added to the correction coefficient k of the ROI 604 obtained by the calculation processing. By performing the smoothing processing, the difference in the correction coefficient k between the ROIs 601 and 602 or between the ROIs 602 and 604 is smaller than the predetermined value. Note that in the example of the smoothing processing shown in
As the smoothing processing, various kinds of processes can be applied. As an example of the smoothing processing, for example, processing such as linear interpolation can be applied. The image generation circuit 113 generates a corrected radiation image X′ using the correction coefficient k having undergone the smoothing processing. By performing the smoothing processing, it is possible to suppress generation of a step, that can visually be perceived, at the boundary between the ROIs in the generated corrected radiation image X′.
Note that the third embodiment has explained an example of processing in which the image generation circuit 113 compares the correction coefficients k calculated for the respective ROIs and determines whether the difference in the correction coefficient k between the adjacent ROIs exceeds the predetermined value (second threshold). However, the image generation circuit 113 may perform the smoothing processing for the correction coefficients k of all the ROIs without determining whether the difference in the correction coefficient exceeds the predetermined value (second threshold). The image generation circuit 113 may perform the smoothing processing to reduce the difference in the correction coefficient between the pixel regions among the plurality of pixel regions.
In the techniques disclosed in the above second and third embodiments, it is possible to perform accurate afterimage correction while improving the frame rate and reducing noise in a radiation image.
The offset image generation processing will be described below with reference to a timing chart 310 and a correction processing procedure 320 shown in
In the timing chart 310 shown in
In the timing chart 310 shown in
During the readout period, the control circuit 112 selects each of the plurality of pixels P included in the pixel array 200, and reads out a signal from the selected pixel P. More specifically, the driving circuit 210 sequentially supplies an ON signal to each of the driving lines Vg1 to Vgm. First, the driving circuit 210 supplies the ON signal only to the driving line Vg1. This turns on a switch element S(1, j) (j=1, . . . , n), a conversion device C(1, j) and a signal line Sigj are rendered conductive, and thus electric charges accumulated in the conversion device C(1, j) are read out into the signal line Sigj. Next, the driving circuit 210 supplies the ON signal only to the driving line Vg2. This turns on a switch element S(2, j), a conversion device C(2, j) and the signal line Sigj are rendered conductive, and thus electric charges accumulated in the conversion device C(2, j) are read out into the signal line Sigj. When the driving circuit 210 repeats this operation up to the driving line Vgm, the electric charges based on those accumulated in the conversion device C are read out by a readout circuit 220 via the signal line Sigj. In the following description, execution of the readout operation for the plurality of pixels P means execution of the readout operation for each of the plurality of pixels P. Offset image generation processing to be described in the following example is performed in imaging preparation, and is performed in periods 301 to 308 shown in
In imaging preparation, the control circuit 112 alternately executes an accumulation operation and a readout operation in a state in which radiation irradiation is not performed. As shown in
In the example shown in
A signal read out during the readout period 302 or 306 is represented as a long-time offset signal (to be also referred to as the first signal or the first offset signal hereinafter), and a signal read out during the readout period 304 or 308 is represented as a short-time offset signal (to be also referred to as the second signal or the second offset signal hereinafter). In the state in which radiation irradiation is not performed, the control circuit 112 alternately executes the first readout control of reading out the first signal based on the electric charges accumulated during the accumulation period 301 or 305 (first period) and the second readout control of reading out the second signal based on the electric charges accumulated during the accumulation period 303 or 307 (second period) shorter than the first period.
An offset image generated based on the long-time offset signal (first signal) is represented as a long-time offset image (to be also referred to as the first offset image hereinafter), and an offset image generated based on the short-time offset signal (second signal) is represented as a short-time offset image (to be also referred to as the second offset image hereinafter).
In the following description, a long-time offset image obtained when a frame counter is set to N is represented by “S.N”, and a short-time offset image is represented by “T.N”. For example, a long-time offset image obtained when the frame counter is set to N=1 is represented by “S.1”, and a short-time offset image is represented by “T.1”.
In step S401, the control circuit 112 sets the frame counter N to 0. After that, in step S402, the control circuit 112 increments the frame counter N by adding 1 to the frame counter N.
In step S403, the long-time offset image S.1 is obtained. The operation of obtaining the long-time offset image S. 1 includes the accumulation operation executed during the accumulation period 301 of
As a practical operation, during the accumulation period 301, the radiation imaging apparatus 110 performs an electric charge accumulation operation in all the pixels P (all image sensors) included in the pixel array 200 of the radiation detecting panel 111 in a state in which irradiation with the radiation 160 is not performed, as indicated by “radiation” in the timing chart 310 shown in
In step S404, the short-time offset image T.1 is obtained. The operation of obtaining the short-time offset image T.1 includes the accumulation operation executed during the accumulation period 303 of
During the accumulation period 303 shorter than the accumulation period 301, the radiation imaging apparatus 110 performs an electric charge accumulation operation in all the pixels P (all the image sensors) included in the pixel array 200 of the radiation detecting panel 111 in a state in which the radiation imaging apparatus 110 is not irradiated with the radiation 160. After that, in the readout operation executed during the readout period 304, the control circuit 112 controls the radiation detecting panel 111 to output a signal (electrical signal) based on the electric charges accumulated during the accumulation period 303, and the image generation circuit 113 generates image data based on the signal (electrical signal) obtained from the radiation detecting panel 111. The image generation circuit 113 stores the generated image data as the short-time offset image T.1 in the storage device 170.
After that, in step S405, the control circuit 112 determines whether the frame counter N has reached a predetermined number. As an example, a case where the predetermined number is two will be described. If it is determined in step S405 that the frame counter N has not reached the predetermined number (NO in step S405), the process is returned to step S402. That is, if the frame counter is N=1, the frame counter N has not reached the predetermined number, and thus the control circuit 112 returns the process to step S402.
After that, in step S402, the control circuit 112 increments the frame counter N by adding 1 to the frame counter N, and advances the process to step S403.
In step S403, a long-time offset image S.2 is obtained. The operation of obtaining the long-time offset image S.2 includes the accumulation operation executed during the accumulation period 305 of
The accumulation operation executed during the accumulation period 305 and the readout operation executed during the readout period 306 are respectively the same as the electric charge accumulation operation during the accumulation period 301 and the readout operation of the signal based on the electric charges during the readout period 302 when generating the long-time offset image S.1. The control circuit 112 controls the radiation detecting panel 111 to output the signal (electrical signal) based on the electric charges accumulated during the accumulation period 305, and the image generation circuit 113 generates image data based on the signal (electrical signal) obtained from the radiation detecting panel 111. The image generation circuit 113 stores the generated image data as the long-time offset image S.2 in the storage device 170. Thus, the storage device 170 stores the long-time offset images S.1 and S.2.
After that, in step S404, a short-time offset image T.2 is obtained. The operation of obtaining the short-time offset image T.2 includes the accumulation operation executed during the accumulation period 307 of
The accumulation operation executed during the accumulation period 307 and the readout operation executed during the readout period 308 are respectively the same as the electric charge accumulation operation during the accumulation period 303 and the readout operation of the signal based on the electric charges during the readout period 304 when generating the short-time offset image T.1. The control circuit 112 controls the radiation detecting panel 111 to output the signal (electrical signal) based on the electric charges accumulated during the accumulation period 307, and the image generation circuit 113 generates image data based on the signal (electrical signal) obtained from the radiation detecting panel 111. The image generation circuit 113 stores the generated image data as the short-time offset image T.2 in the storage device 170. Thus, the storage device 170 stores the short-time offset images T.1 and T.2.
In step S405, the control circuit 112 determines again whether the frame counter N has reached the predetermined number. Assume here that the predetermined number is two. Therefore, the control circuit 112 determines that the frame counter N has reached the predetermined number (YES in step S405), and advances the process to step S406.
In step S406, the image generation circuit 113 performs processing for generating a long-time offset image S. The image generation circuit 113 generates the long-time offset image S by performing addition and averaging of the images from the long-time offset image S.1 to the long-time offset image S.N (in this example, N=2) stored in the storage device 170. The image generation circuit 113 stores the generated long-time offset image S in the storage device 170.
Subsequently, in step S407, the image generation circuit 113 performs processing for generating a short-time offset image T. The image generation circuit 113 generates the short-time offset image T by performing addition and averaging of the images from the short-time offset image T.1 to the short-time offset image T.N (in this example, N=2) stored in the storage device 170. The image generation circuit 113 stores the generated short-time offset image T in the storage device 170.
Then, the processing for generating the offset image to be used for image processing of a radiation image ends. As described above, in imaging preparation, the control circuit 112 alternately executes generation of the long-time offset image S and generation of the short-time offset image T. This generates the plurality of long-time offset images S and the plurality of short-time offset images T. In imaging preparation, the image generation circuit 113 creates one long-time offset image S by averaging (performing addition and averaging) the plurality of long-time offset images S.i (i=1 to N), and stores the created image in the storage device 170 for subsequent processing. Similarly, in imaging preparation, the image generation circuit 113 creates one short-time offset image T by averaging (performing addition and averaging) the plurality of short-time offset images T.i (i=1 to N), and stores the created image in the storage device 170 for subsequent processing. By averaging the plurality of offset images in this way, it is possible to reduce noise included in the offset image.
Note that in the example described with reference to
In step S501 of
In step S502, the control circuit 112 and the image generation circuit 113 perform processing for generating the radiation image X. The processing for generating the radiation image X includes an accumulation operation executed during an accumulation period 309 of
The accumulation operation during the accumulation period 309 is performed in a state in which irradiation with radiation 160 is performed, as indicated by “radiation” in the timing chart 310 shown in
During the readout period 310, the control circuit 112 executes the third readout control of reading out, as the third signal, a radiation signal based on electric charges accumulated during the accumulation period 309 (third period) having the time length equal to that of the accumulation period 301 or 305 (first period) in the state in which radiation irradiation is performed. In the readout operation executed during the readout period 310, the control circuit 112 controls the radiation detecting panel 111 to output a signal (electrical signal) based on the electric charges accumulated during the accumulation period 309. The image generation circuit 113 generates the radiation image X based on the signal (electrical signal) output from the radiation detecting panel 111, and stores the generated image in the storage device 170. Note that the readout operation executed by the control circuit 112 during the readout period 310 is the same as the readout operation executed during the readout period 302 or 306 to obtain the long-time offset image S in imaging preparation.
In step S503, the control circuit 112 and the image generation circuit 113 perform processing for generating an imaging offset image U. The processing for generating the imaging offset image U includes an accumulation operation executed during an accumulation period 311 shown in
The accumulation operation during the accumulation period 311 is performed in the state in which irradiation with the radiation 160 is not performed, as indicated by “radiation” in the timing chart 310 shown in
During the readout period 312, the control circuit 112 executes the fourth readout control of reading out, as an imaging offset signal (to be also referred to as the fourth signal hereinafter), a signal based on electric charges accumulated during the accumulation period 311 (fourth period) in the state in which radiation irradiation is not performed after reading out the radiation signal (third signal) during the readout period 310. In the readout operation executed during the readout period 312, the control circuit 112 controls the radiation detecting panel 111 to output a signal (electrical signal) based on the electric charges accumulated during the accumulation period 311.
The image generation circuit 113 generates the imaging offset image U based on the signal (electrical signal) output from the radiation detecting panel 111, and stores the generated image in the storage device 170. Note that the readout operation executed by the control circuit 112 during the readout period 312 is the same as the readout operation executed during the readout period 304 or 308 to obtain the short-time offset image T in imaging preparation.
In step S504, the image generation circuit 113 performs processing for generating a radiation afterimage. The image generation circuit 113 reads out the radiation image X and the long-time offset image S (first offset image) stored in the storage device 170, and subtracts the long-time offset image S (first offset image) from the radiation image X, thereby generating a radiation afterimage (“X−S” in
Subsequently, in step S505, the image generation circuit 113 performs processing for generating an offset afterimage. The image generation circuit 113 reads out the imaging offset image U and the short-time offset image T (second offset image) stored in the storage device 170, and subtracts the short-time offset image T (second offset image) from the imaging offset image U, thereby generating an offset afterimage (“U−T” in
An afterimage amount included in each of the radiation afterimage (X−S) and the offset afterimage (U−T) is proportional to a time length for which electric charges are accumulated in the pixel P. In step S506, the image generation circuit 113 determines the afterimage amount in the offset afterimage (U−T) based on statistical information obtained by statistical processing of pixel values. The statistical information includes, for example, at least one of the maximum pixel value, the minimum pixel value, the standard deviation of the pixel values, the average value (in-plane average pixel value) of the pixel values, and the like in the offset afterimage (U−T).
Next, the image generation circuit 113 adjusts a correction coefficient k in accordance with the afterimage amount determined based on the statistical information obtained by the statistical processing of the pixel values in the offset afterimage (U−T). The afterimage amount is information representing the amount of afterimage components included in the offset afterimage (U−T).
Comparison between the afterimage amount and a threshold is merely an example. For example, if the statistical information is equal to or larger than a threshold th1 (first threshold), the image generation circuit 113 determines that the afterimage amount included in the offset afterimage (U−T) is large (a large afterimage amount), and sets the correction coefficient k based on the electric charge accumulation time. For example, the image generation circuit 113 may calculate the correction coefficient k based on the ratio (time length of third period/time length of fourth period) between the electric charge accumulation time (the time length of the third period) in the state in which radiation irradiation is performed and the electric charge accumulation time (the time length of the fourth period) in the state in which radiation irradiation is not performed.
In a case where, for example, the electric charge accumulation period based on radiation (for example, the period 309 (third period) in
In a case where the statistical information is smaller than the threshold th1 (first threshold) and equal to or larger than a threshold th2 (second threshold) smaller than the threshold th1 (th1>afterimage amount≥th2), the image generation circuit 113 sets “1” as the correction coefficient k. In this case, the image generation circuit 113 determines that the afterimage amount included in the offset afterimage (U−T) is small (a small afterimage amount), and the image generation circuit 113 sets “1” as the correction coefficient k.
In a case where the statistical information is smaller than the threshold th2 (second threshold) (afterimage amount<th2), the image generation circuit 113 determines that no afterimage is generated, and sets the correction coefficient k to zero (0). In this case, the image generation circuit 113 determines that the offset afterimage (U−T) includes no afterimage component (afterimage amount: none), and sets the correction coefficient k to zero (0).
The above-described example is merely an example, and the image generation circuit 113 determines the afterimage amount by the determination processing of comparing, with the threshold, the statistical information obtained by the statistical processing of the pixel values in the offset afterimage (U−T), and adjusts the correction coefficient k stepwise in accordance with the afterimage amount. In this example, the arrangement of using the first and second thresholds has been exemplified. However, the present disclosure is not limited to this, and the user can arbitrarily set, via the input device 115, the number of thresholds to be used for determination of the afterimage amount, the setting value of each threshold, and the like. For example, the setting value of each threshold may be changed in accordance with the intensity and irradiation time of radiation to be emitted, a captured portion, an imaging condition, and the like.
In step S507, the image generation circuit 113 generates an adjustment afterimage (k(U−T) in
In step S508, the image generation circuit 113 subtracts the adjustment afterimage (k(U−T) from the radiation afterimage (X−S) generated in step S504, thereby generating the radiation image X′(X′=(X−S)-k(U−T) in
The radiation image X′ obtained by correcting the radiation image X is an image obtained by correcting the radiation image X using the long-time offset image S (first offset image), the short-time offset image T (second offset image), the imaging offset image U (third offset image), and the correction coefficient k. The image generation circuit 113 transmits the corrected radiation image X′ to the computer 120.
The above-described calculation order for generating the radiation image X′ is merely an example, and calculation may be performed in another order. The radiation image X′, that is, X−S−k(U−T) is changed to X−kU+(kT−S). In imaging preparation, the image generation circuit 113 may calculate kT−S using the long-time offset image S, the short-time offset image T, and the correction coefficient k, and store the value as a correction value in the memory of the image generation circuit 113. The correction coefficient k can be decided based on the preset of a timing at which the driving circuit 210 supplies the ON signal to the pixel array 200. In capturing a moving image, the image generation circuit 113 may correct the radiation image X using the imaging offset image U, the correction value stored in the storage device 170, and the correction coefficient k. In this way, by storing the correction value instead of storing the long-time offset image S and the short-time offset image T, it is possible to reduce the memory consumption of the image generation circuit 113.
After that, in step S509, the control circuit 112 determines whether to continue imaging. In an example, the exposure control apparatus 130 includes an exposure switch (not shown). When the user turns off the exposure switch, the exposure control apparatus 130 sends an exposure stop instruction to the radiation generating apparatus 140, and also sends a stop notification indicating the stop of radiation irradiation to the computer 120. In response to the stop notification, the computer 120 that has received the stop notification notifies the control circuit 112 of the radiation imaging apparatus 110 of the stop of radiation irradiation. The control circuit 112 confirms the presence/absence of an imaging end request from the computer 120. If imaging is not continued (NO in step S509), the control circuit 112 ends the processing for generating the radiation image. On the other hand, if an imaging end request is not sent to capture a plurality of frames like moving image capturing, it is determined to continue imaging (YES in step S509), and the control circuit 112 returns the process to step S502 again, and repeats the same processing. If imaging is continued, the control circuit 112 and the image generation circuit 113 perform the same processing in an accumulation period 313 (third period), a readout period 314, an accumulation period 315 (fourth period), and a readout period 316.
After that, the processes in steps S502 to S508 are repeated again. By generating the corrected radiation image X′ by correcting the radiation image X for each captured frame in the above-described processing, it is possible to perform accurate afterimage correction while improving the frame rate and reducing noise in a radiation image.
Operation example 2 of the radiation imaging apparatus 110 different from operation example 1 of the radiation imaging apparatus 110 described with reference to
As different operation example 2, the efficiency of calculation processing of the correction coefficient k may be improved, as illustrated in the flowchart shown
A range 700 shown in
Referring to
Afterimage amounts 714a and 714b represent afterimage amounts after irradiation with radiation 702, and the afterimage amount 714a indicates an offset afterimage Pn+4a (Pn+4a=Un+4a−Tn+4a) when the radiation image X is captured in an (n+4)th frame Fn+4. In addition, the afterimage amount 714b indicates an offset afterimage Pn+4b (Pn+4b=Un+4b-Tn+4b) when the radiation image X is captured in an (n+4)th frame Fn+4.
Even after irradiation with the radiation 702, the afterimage amount 714a attenuates from the preceding frame Fn+3 in accordance with the attenuation characteristic 703. On the other hand, the afterimage amount 714b is an afterimage amount deviating from the attenuation characteristic 703.
With respect to the offset afterimages (Pn+3 and Pn+4a) newly obtained by continuing imaging, the afterimage amount changes in accordance with the attenuation characteristic 703. Even if the correction coefficient k is calculated for each of the offset afterimages (Pn+3 and Pn+4a), the difference from the correction coefficient KAVE calculated for the average offset afterimage is estimated to be small. In this case, as will be described in steps S621 and S622 when YES is determined in step S620 of
On the other hand, if the difference between the average pixel value in the offset afterimage (Pn+4b) newly obtained by continuing imaging and the average pixel value in the average offset afterimage exceeds the predetermined range (NO in step S620), an adjustment afterimage (K(Un+4b-Tn+4b)) is generated using the recalculated correction coefficient k in the newly obtained offset afterimage (Pn+4b) (steps S625 and S626). The detailed processing procedure will be described below with reference to the flowchart shown in
The flowchart shown in
In step S601, the control circuit 112 confirms the presence/absence of an imaging start request from the computer 120. This processing is the same as that in step S501 of
In step S602, the control circuit 112 resets an internal imaging counter n to 0. The control circuit 112 includes a memory (not shown), and can store the setting of the imaging counter n. In this step, the control circuit 112 resets the setting of the imaging counter n stored in the memory (not shown).
In step S603, the control circuit 112 increments the imaging counter n.
Processes of steps S604 to S611 are the same as those of steps S502 to S509 of
In step S612, the control circuit 112 determines whether the imaging counter n has reached a predetermined number. If it is determined that the imaging counter n has not exceeded the predetermined number (NO in step S612), the control circuit 112 returns the process to step S603 and repeats the processes in step S603 and the subsequent steps. On the other hand, if it is determined, in the determination processing of step S612, that the imaging counter n has reached the predetermined number (YES in step S612), the control circuit 112 advances the process to step S613.
In step S613, the image generation circuit 113 reads out several latest offset afterimages (U−T) that have been stored in the storage device 170 in step S607, for example, Pn, Pn+1, and Pn+2 in
In step S614, the image generation circuit 113 calculates the correction coefficient k with respect to an afterimage amount in the average offset afterimage generated in step S613 by the same method as in step S506 of
Processes of steps S615 to S618 are the same as the processes of steps S502 to S505 of
In step S619, the image generation circuit 113 calculates the difference (the absolute value of the difference) between the average pixel value in the imaging offset afterimage (U−T) generated in step S616 and the average pixel value in the average offset afterimage generated in step S613.
By determining (step S620) whether the difference between the average pixel value in the offset afterimage newly obtained by continuing imaging and the average pixel value in the average offset afterimage falls within the predetermined range, the image generation circuit 113 adjusts the correction coefficient to be used for processing for generating an adjustment afterimage.
In step S620, the image generation circuit 113 determines whether the difference (the absolute value of the difference) calculated in step S619 falls within the predetermined range. If the image generation circuit 113 determines that the difference (the absolute value of the difference) exceeds the predetermined range (NO in step S620), the image generation circuit 113 advances the process to step S625.
On the other hand, if it is determined, in the determination processing of step S620, that the difference (the absolute value of the difference) falls within the predetermined range (YES in step S620), the image generation circuit 113 advances the process to step S621. If it is determined, in the determination processing of step S620, that the absolute value of the difference between the average pixel value in the offset afterimage (U−T) calculated in step S619 and the average pixel value in the average offset afterimage does not exceed the predetermined range, there is no large change in the characteristic of the afterimage.
In step S621, the image generation circuit 113 decides, as the correction coefficient k for generating an adjustment afterimage, the correction coefficient k (the correction coefficient KAVE described with reference to
Processes (processes in steps S622 to S624) of newly obtaining various kinds of images by continuing imaging are the same as those of steps S507 to S509 of
In step S622, the image generation circuit 113 performs processing of generating the adjustment afterimage (k(U−T)) using the correction coefficient k (the correction coefficient KAVE described with reference to
In step S623, the image generation circuit 113 generates the corrected radiation image (X′=(X−S)-k(U−T)) in which the afterimage is reduced from the radiation image X, by subtracting the adjustment afterimage (k(U−T)) generated in step S622 from the radiation afterimage (X−S) generated in step S617. The image generation circuit 113 transmits the generated corrected radiation image X′ to the computer 120.
Then, in step S624, the control circuit 112 performs processing of determining whether to continue imaging, which is the same as in step S611. If it is determined to continue imaging (YES in step S624), the control circuit 112 returns the process to step S615, and repeats the same processing. Note that for the purpose of updating the correction coefficient k to be used in step S621 every time imaging is performed, the processes from step S613 may be repeated.
If it is determined not to continue imaging (NO in step S624), the processing for generating the radiation image is ended. Thus, in a case where there is no large change in the characteristic of the afterimage, it is possible to reduce the afterimage by using even the correction coefficient k calculated in step S614. Therefore, it is possible to improve the efficiency of the calculation processing by omitting calculation of the correction coefficient k.
On the other hand, if it is determined, in the determination processing of step S620, that the difference (the absolute value of the difference) calculated in step S619 exceeds the predetermined range (NO in step S620), such large change that the predetermined range is exceeded occurs in the characteristic of the afterimage in the middle of imaging (for example, the afterimage amount 714b in
In step S625, the image generation circuit 113 recalculates the correction coefficient k. When performing recalculation, the image generation circuit 113 calculates the correction coefficient k by the same calculation processing as that in step S608 (S506) using the offset afterimage (U−T: for example, Pn+4b in
Processes of steps S626 and S627 are the same as those of steps S507 and S508 of
In step S626, the image generation circuit 113 performs processing of generating the adjustment afterimage (k(U−T)) using the correction coefficient k calculated in step S625. Then, the image generation circuit 113 generates the corrected radiation image X′(X′=(X−S)-k(U−T)) in which the afterimage is reduced from the radiation image X, by subtracting the adjustment afterimage (k(U−T)) from the radiation afterimage (X−S) generated in step S617. The image generation circuit 113 transmits the generated corrected radiation image X′ to the computer 120. After that, the process is returned to step S602 again and the same processing is performed. In the processing described with reference to
In the above-described fourth embodiment, the pixel array 200 includes only the pixels P to be used to generate a radiation image. Instead of this, the pixel array 200 may include pixels to be used for the purpose other than generation of a radiation image, like pixels to be used for automatic exposure control.
According to the technique disclosed in the above-described fourth embodiment, it is possible to perform accurate afterimage correction while improving the frame rate and reducing noise in a radiation image.
An example of the operation of a radiation imaging system 100 according to the fifth embodiment will be described with reference to
In the timing chart shown in
In the timing chart shown in
In the timing chart shown in
During the readout period, the control circuit 112 selects each of the plurality of pixels P included in the pixel array 200, and reads out a signal from the selected pixel P. More specifically, the driving circuit 210 sequentially supplies an ON signal to each of the driving lines Vg1 to Vg8. First, the driving circuit 210 supplies the ON signal only to the driving line Vg1. This turns on a switch element S(1, j) (j=1, . . . , n), a conversion device C(1, j) and a signal line Sigj are rendered conductive, and thus electric charges accumulated in the conversion device C(1, j) are read out into the signal line Sigj. Next, the driving circuit 210 supplies the ON signal only to the driving line Vg2. This turns on a switch element S(2, j), a conversion device C(2, j) and the signal line Sigj are rendered conductive, and thus electric charges accumulated in the conversion device C(2, j) are read out into the signal line Sigj. When the driving circuit 210 repeats this operation up to the driving line Vg8, the electric charges based on those accumulated in the conversion device C are read out by the readout circuit 220 via the signal line Sigj. In the following description, execution of the readout operation for the plurality of pixels P means execution of the readout operation for each of the plurality of pixels P.
The operation by the radiation imaging apparatus 110 includes an operation executed in imaging preparation, and an operation executed after imaging preparation ends. A period after imaging preparation ends may include a period during which a radiation image is captured, and may further include a period during which a moving image is captured. The period during which the radiation image is captured may be called an imaging period. As will be described later, during the imaging period, the radiation imaging apparatus 110 need not always be irradiated with the radiation 160, and may intermittently be irradiated with the radiation 160.
In imaging preparation, the radiation imaging apparatus 110 is not irradiated with the radiation 160. Imaging preparation may end when a predetermined condition is satisfied. The predetermined condition may be, for example, a condition that a predetermined number of offset images (to be described later) are generated. When imaging preparation ends, the radiation imaging apparatus 110 may notify a computer 120 that radiation irradiation is possible.
After imaging preparation ends, the radiation imaging apparatus 110 is irradiated with the radiation 160, thereby generating a radiation image corresponding to the radiation 160. As shown in
The control circuit 112 alternately executes the accumulation operation and the readout operation in a state in which radiation irradiation is not performed in imaging preparation. As shown in
During the readout period 412, a signal based on electric charges accumulated for a time length 401 is read out from the pixel P. The time length 401 is a time length from when the last readout operation of the pixel P ends (that is, the driving signal changes to low level) until the current readout operation of the pixel P ends (that is, the driving signal changes to low level again). The same applies to other time lengths for which electric charges are accumulated. The time length 401 includes the accumulation period 411. During the readout period 414, a signal based on electric charges accumulated for a time length 402 is read out from the pixel P. The time length 402 includes the accumulation period 413.
In the example shown in
The image generation circuit 113 generates a long-time offset image S based on the long-time offset signals (first offset signals) read out from the plurality of pixels P included in the pixel array 200. The long-time offset image S is represented as a matrix of m rows and n columns, and the signal read out from the pixel P (i, j) is the (i, j) element of the matrix. The image generation circuit 113 generates a short-time offset image T based on the short-time offset signals (second offset signals) read out from the plurality of pixels P included in the pixel array 200. The short-time offset image T is represented as a matrix of m rows and n columns, and the signal read out from the pixel P (i, j) is the (i, j) element of the matrix.
The control circuit 112 repeatedly executes the operations in the accumulation period 411 to the readout period 414. That is, the same operations as in the accumulation period 411 to the readout period 414 are executed in the accumulation period 415 to the readout period 418. In this way, the control circuit 112 alternately executes the readout operation of reading out the long-time offset signals and the readout operation of reading out the short-time offset signals in imaging preparation.
After imaging preparation ends, the control circuit 112 starts to capture a moving image (that is, a plurality of radiation images). More specifically, the control circuit 112 alternately executes the accumulation operation and the readout operation. As shown in
During the readout period 422, a signal based on electric charges accumulated for a time length 403 is read out from the pixel P. The time length 403 includes the accumulation period 421. The accumulation period 421 includes a period during which the radiation imaging apparatus 110 is irradiated with the radiation 160. Therefore, the time length 403 includes a period during which the radiation imaging apparatus 110 is irradiated with the radiation 160. The time length 403 may be equal to the time length 401. During the readout period 424, a signal based on electric charges accumulated for a time length 404 is read out from the pixel P. The time length 404 includes the accumulation period 423. The time length 404 does not include a period during which the radiation imaging apparatus 110 is irradiated with the radiation 160. The time length 404 may be equal to the time length 402.
In the example shown in
The image generation circuit 113 generates a radiation image X based on the radiation signals read out from the plurality of pixels P included in the pixel array 200. The radiation image X is represented as a matrix of m rows and n columns, and the signal read out from the pixel P (i, j) is the (i, j) element of the matrix. The image generation circuit 113 generates an imaging offset image U based on the imaging offset signals (third offset signals) read out from the plurality of pixels P included in the pixel array 200. The imaging offset image U is represented as a matrix of m rows and n columns, and the signal read out from the pixel P (i, j) is the (i, j) element of the matrix.
The control circuit 112 repeatedly executes the operations in the accumulation period 421 to the readout period 424. That is, the same operations as in the accumulation period 421 to the readout period 424 are executed in the accumulation period 425 to the readout period 428. In this way, the control circuit 112 alternately executes the readout operation of reading out the radiation signals and the readout operation of reading out the imaging offset signals after imaging preparation ends (for example, in capturing a moving image).
Subsequently, a method in which the image generation circuit 113 corrects the radiation image X using the long-time offset image S, the short-time offset image T, and the imaging offset image U will be described. As described above, components of the long-time offset image S, the short-time offset image T, the imaging offset image U, and the radiation image X are respectively given by the long-time offset signal, the short-time offset signal, the imaging offset signal, and the radiation signal. In the following method, the radiation signal is corrected using the long-time offset signal, the short-time offset signal, and the imaging offset signal.
As described above, in imaging preparation, the control circuit 112 alternately executes generation of the long-time offset image S and generation of the short-time offset image T. This generates the plurality of long-time offset images S and the plurality of short-time offset images T. In imaging preparation, the image generation circuit 113 creates one long-time offset image S by averaging the plurality of long-time offset images S, and stores the created image in a storage device 170 of the image generation circuit 113 for subsequent processing. Similarly, in imaging preparation, the image generation circuit 113 creates one short-time offset image T by averaging the plurality of short-time offset images T, and stores the created image in the storage device 170 of the image generation circuit 113 for subsequent processing. By averaging the plurality of offset images in this way, noise included in the offset image can be reduced. The number of offset images used for averaging may be two, as shown in
After imaging preparation ends, the image generation circuit 113 generates the radiation image X and the imaging offset image U, and stores them in the storage device 170 of the image generation circuit 113. The image generation circuit 113 reads out the long-time offset image S from the storage device 170, and subtracts the long-time offset image S from the radiation image X, thereby generating a radiation afterimage (“X−S” in
An afterimage component included in each of the radiation afterimage (X−S) and the offset afterimage (U−T) is proportional to a time length for which electric charges are accumulated in the pixel P. The image generation circuit 113 performs offset correction before multiplying each element of the offset afterimage (U−T) by a coefficient k equal to the ratio of the time length 403 to the time length 404 (that is, a value obtained by dividing the time length 403 by the time length 404).
The image generation circuit 113 performs offset correction of offset noise signals included in the short-time offset signal (second offset signal) and the imaging offset signal (third offset signal), and generates a radiation image based on correction of a radiation signal using the long-time offset signal (first offset signal) and the short-time offset signal and imaging offset signal having undergone offset correction.
The image generation circuit 113 generates an offset correction value using pixel information of a light-shielded pixel included in the short-time offset image T generated based on the short-time offset signals and pixel information of a light-shielded pixel included in the imaging offset image U generated based on the imaging offset signals. The image generation circuit 113 performs offset correction of reducing the offset noise signals using a generated offset correction value V.
By using, as pixel information, the average value of the pixel values of optical black pixels (OBs) included in the offset afterimage, the image generation circuit 113 may generate the offset correction value V to be used for offset correction. With respect to the OBs used for offset correction, the average value of the pixel values of pixels in a region where an irradiation field is narrowed by a collimator and a region where X-rays are shielded may be used as pixel information. Furthermore, in a case where the characteristic changes for each pixel row (line) of the offset afterimage, the offset correction value V may be calculated using, as pixel information, the average value of the pixel values of OBs on the left and right side of each pixel row (line) of the offset afterimage or light-shielded pixels on each pixel row (line).
In a driving method of reading out an image, the offset characteristic for each pixel row may change in a case where, for example, a mode of reading out only the same pixel row within a short time or a cropping readout mode of narrowing an irradiation field is switched to a mode of reading out signals based on electric charges from all the pixel rows (all screen lines) of the pixel array in which the plurality of pixels P are arrayed in a matrix.
In the fifth embodiment, by executing offset correction before multiplying each element of the offset afterimage by the coefficient k, it is possible to reduce artifact caused by the offset characteristic.
The image generation circuit 113 generates an offset afterimage (“(U−T)−V” in
The above-described calculation order for generating the radiation image X′ is merely an example, and calculation may be performed in another order. The offset correction value V can include a correction value Vt for the second offset signal calculated based on the pixel information (for example, the pixel values) of a light-shielded region included in an image based on the short-time offset signals (second offset signals), and a correction value Vu for the third offset signal calculated based on the pixel information of a light-shielded region included in an image based on the imaging offset signals (third offset signals). The image generation circuit 113 performs offset correction of an offset noise signal included in the short-time offset signal (second offset signal) using the correction value Vt for the second offset signal, and performs offset correction of an offset noise signal included in the imaging offset signal (third offset signal) using the correction value Vu for the third offset signal. The image generation circuit 113 corrects a radiation signal using the long-time offset signal, the coefficient k, and the short-time offset signal and imaging offset signal having undergo offset correction.
The radiation image X′, that is, X−S−k((U−T)−V) is changed to X−k(U−Vu)+(k(T−Vt)−S). Thus, in imaging preparation, the image generation circuit 113 may calculate k (T−Vt)−S using the long-time offset image S, the short-time offset image T, and the coefficient k, and store this value as a correction value in the storage device 170 of the image generation circuit 113. At this time, Vu represents an offset correction value calculated from the pixel information of a light-shielded region or OBs in the imaging offset image U, and Vt represents an offset correction value calculated from the pixel information of a light-shielded region or OBs in the short-time offset image T.
In imaging preparation, the image generation circuit 113 may store, in the storage device 170, the first correction value calculated using the long-time offset signal (first offset signal), the short-time offset signal (second offset signal), and the correction value Vt for the second offset signal. The first correction value can be obtained as (T−Vt)−S by each image generated based on each signal. After calculating the coefficient k, the first correction value can be obtained as k (T−Vt)−S.
After imaging preparation ends, the image generation circuit 113 may correct the radiation signal using the second correction value calculated using the imaging offset signal (third offset signal) and the correction value Vu for the third offset signal, and the first correction value stored in the storage device 170 of the image generation circuit 113. The second correction value can be obtained as (U−Vu) by each image generated based on each signal. Furthermore, after calculating the coefficient k, the second correction value can be obtained as k(U−Vu).
Note that if the time length 404 (fourth time length) is equal to the time length 403 (third time length), calculation of the ratio can be omitted, and the first correction value and the second correction value can be obtained using the coefficient k=1. On the other hand, if the time length 404 is different from the time length 403, the image generation circuit 113 may correct the radiation signal using the short-time offset signal (second offset signal) and imaging offset signal (third offset signal) having undergone offset correction further using the ratio of the time length 403 (third time length) to the time length 404 (fourth time length).
The image generation circuit 113 may set, as offset correction target regions, all the regions (all the screen lines) formed by a plurality of pixel rows and a plurality of pixel columns regardless of the control of the control circuit 112. Alternatively, the image generation circuit 113 may set, as an offset correction target region, a region of interest formed by a specific pixel row or pixel column among the plurality of pixel rows and the plurality of pixel columns, which is read out based on the control of the control circuit 112.
The coefficient k can be decided based on the preset of a timing at which the driving circuit 210 supplies the ON signal to the pixel array 200. In capturing a moving image, the image generation circuit 113 may correct the radiation image X using the imaging offset image U, the correction value stored in the storage device 170, and the coefficient k. In this way, by storing the correction value instead of storing the long-time offset image S and the short-time offset image T, it is possible to reduce the memory consumption of the storage device 170 of the image generation circuit 113.
Subsequently, the technical significance to alternately execute obtaining of the long-time offset image S and obtaining of the short-time offset image T will be described. The driving lines Vg1 to Vgm have various capacitive couplings in the pixel array 200. For example, the driving line Vg2 intersects the signal lines Sig1 to Sign at a plurality of positions of the pixel array 200, and has capacitive coupling at each intersection. Since the driving line Vg2 extends in parallel to the driving line Vg3, it also has capacitive coupling with the driving line Vg3. Since the driving line Vg2 extends in parallel to part of a bias line Bs, it also has capacitive coupling with the bias line Bs. Furthermore, the driving line Vg2 has capacitive coupling with a node of a connecting portion between the switch element S and the conversion device C.
These capacitive couplings change the level of the driving signal supplied to the driving line Vg, and thus potentials of the signal line Sig, the bias line Bs, other driving lines Vg, and the node of the connecting portion between the switch element S and the conversion device C also change. The signal line Sig, the bias line Bs, the driving lines Vg, and the node of the connecting portion between the switch element S and the conversion device C whose potentials have changed return to the original potentials with time. However, the return amount is different depending on the length of the accumulation period.
Even if the switch element S is in the OFF state, a leakage current may flow. When the switch element S is turned off, the node between the conversion device C and the switch element S changes to the low level side due to injection of electric charges from the control terminal (gate). Therefore, immediately after the switch element S is turned off, a potential difference is generated between the main terminals (source and drain) to cause a leakage current to flow. The leakage current depends on the potential difference between the two main terminals (source and drain) of the switch element. If a leakage current flows during the accumulation period, the potential difference becomes small, and thus the leakage current is different depending on the length of the accumulation period. If the leakage current flows to the switch element S, a current also flows to the signal line Sig and the bias line Bs.
For the above reasons, obtained offset images may be different between a case where the long-time offset image S and the short-time offset image T are continuously obtained a plurality of times and a case where the long-time offset image S and the short-time offset image T are alternately obtained. In the above-described operation of the radiation imaging apparatus 110, the long-time offset image S and the short-time offset image T are alternately obtained in imaging preparation, and the radiation image X and the imaging offset image U are alternately obtained after imaging preparation ends. This can make the state of the capacitive coupling in the pixel array 200 in imaging preparation close to the state of the capacitive coupling in the pixel array 200 in capturing a radiation image. Therefore, it is possible to accurately reduce noise included in the radiation image X.
In the operation shown in
In the above-described example, the time length 401 is equal to the time length 403. Instead of this, these time lengths may be different from each other. In a case where the time lengths are different from each other, the image generation circuit 113 may multiply each element of the long-time offset image S by the ratio of the time length 403 to the time length 401, and then subtract the resultant from the radiation image X. In the above-described example, the time length 402 is equal to the time length 404. Instead of this, these time lengths may be different from each other. In a case where the time lengths are different from each other, the image generation circuit 113 may multiply each element of the short-time offset image T by the ratio of the time length 404 to the time length 402, and then subtract the resultant from the imaging offset image U.
Subsequently, an example of the operation of the radiation imaging apparatus 110 different from the above-described operation shown in
The plurality of pixel rows include the first pixel row including the first pixel and the second pixel row including the second pixel, and the driving circuit 210 reads out imaging offset signals based on electric charges accumulated in the first pixel and electric charges accumulated in the second pixel by selecting the first pixel row and the second pixel row. For example, the control circuit 112 selects the first pixel row and the second pixel row during a period (that may be referred to as the first pixel row selection period) in which the driving signal supplied to the driving line Vg1 is at high level in the readout period 424. This reads out imaging offset signals based on electric charges accumulated in the pixel P(1, j) and electric charges accumulated in the pixel P(2, j).
By reading out the imaging offset signals by the binning operation, it is possible to shorten the readout period (for example, the readout period 424) for reading out the imaging offset signals. As a result, it is possible to improve the frame rate of a moving image. The accumulation period 423 may be shorter than the accumulation period 421 or may be equal to the accumulation period 421. Even if the length of the accumulation period 423 is equal to that of the accumulation period 421, it is possible to improve the frame rate of a moving image by reading out the imaging offset signals by the binning operation. Since the imaging offset signals are read out by the binning operation, short-time offset signals to be used as differences from the imaging offset signals may be read out by the binning operation. Instead of this, the short-time offset signal may be read out by a normal operation (selection of one row). In this case, the short-time offset signal may be multiplied by the coefficient for adjusting the time length for which electric charges are accumulated in the pixel P.
In the operation shown in
Subsequently, a radiation image generation method in the operation shown in
After that, the image generation circuit 113 generates the short-time offset image T by adjusting the size of the short-time offset image T′ to be equal to the size of the radiation image X. More specifically, the image generation circuit 113 sets, as the (i, j) element (i=1, . . . , m, j=1, . . . , n) of the short-time offset image T, a value obtained by multiplying the (Ceiling (i/2), j) element of the short-time offset image T′ by ½. Ceiling represents a ceiling function, that is, round-up of digits after the decimal point. The reason why the element is multiplied by ½ is that each element of the short-time offset image T′ represents the sum of the signals of two pixels.
After that, as in the explanation of
The image generation circuit 113 generates the radiation image X′ by correcting the radiation image X using the thus generated long-time offset image S, short-time offset image T, and imaging offset image U. The correction processing of the radiation image X may be the same as correction processing 400 shown in
The adjustment of the size of the offset image may be performed in another order. For example, the image generation circuit 113 may generate the adjustment image of the correction processing 400 without adjusting the size of the offset image, and then adjust the size of the adjustment image.
As shown in
The image generation circuit 113 may use the individual coefficient k for each pixel row in the correction processing 400. More specifically, the image generation circuit 113 may use the ratio of the time length 503 to the time length 504 as the coefficient k with respect to the pixels P included in the first pixel row. The image generation circuit 113 may use the ratio of the time length 507 to the time length 508 as the coefficient k with respect to the pixels P included in the eighth pixel row. The ratio of the time length 507 to the time length 508 is different from the ratio of the time length 503 to the time length 504.
With respect to each of the plurality of pixel rows, the length of the accumulation time of the electric charges read out as a long-time offset signal may be equal to the length of the accumulation time of the electric charges read out as a radiation signal. For example, with respect to the first pixel row, a time length 501 may be equal to the time length 503 and a time length 502 may be equal to the time length 504. With respect to the eighth pixel row, a time length 505 may be equal to the time length 507 and a time length 506 may be equal to the time length 508.
Subsequently, an example of the operation of the radiation imaging apparatus 110 different from the above-described operation shown in
In the operation shown in
Subsequently, an example of the operation of the radiation imaging apparatus 110 different from the above-described operation shown in
First, an operation in imaging preparation will be described. An operation in an accumulation period 711 to an accumulation period 713 and an operation in an accumulation period 715 to an accumulation period 717 may be the same as the operation in the accumulation period 411 to the accumulation period 413 in
Similar to the operation shown in
Subsequently, an operation after imaging preparation ends (for example, in capturing a moving image) will be described. An operation in a readout period 721 to a readout period 727 may be the same as the operation in the readout period 712 to the readout period 718 and a description thereof will be omitted.
Similar to the operation shown in
For example, as shown in
The driving circuit 210 reads out the imaging offset signals based on the electric charges accumulated in the second pixel and the electric charges accumulated in the third pixel by selecting the second pixel row and the third pixel row during the third selection period. The driving circuit 210 selects no third pixel row during the first selection period, and selects no first pixel row during the third selection period. The image generation circuit 113 corrects the radiation signal read out during the second selection period using the long-time offset signal (first offset signal), the short-time offset signal (second offset signal), the imaging offset signal (third offset signal) read out during the first selection period, and the imaging offset signal (third offset signal) read out during the third selection period.
After that, the image generation circuit 113 generates the radiation image X′ by correcting the radiation image X using the thus generated long-time offset image S, short-time offset image T, and imaging offset image U. The correction processing of the radiation image X may be the same as the correction processing 400 shown in
In the above-described fifth embodiment, the pixel array 200 includes only the pixels P to be used to generate a radiation image. Instead of this, the pixel array 200 may include pixels to be used for the purpose other than generation of a radiation image, like pixels to be used for automatic exposure control.
Embodiment(s) of the present disclosure can also be realized by a computer of a system or apparatus that reads out and executes computer executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be referred to more fully as a ‘non-transitory computer-readable storage medium’) to perform the functions of one or more of the above-described embodiment(s) and/or that includes one or more circuits (e.g., application specific integrated circuit (ASIC)) for performing the functions of one or more of the above-described embodiment(s), and by a method performed by the computer of the system or apparatus by, for example, reading out and executing the computer executable instructions from the storage medium to perform the functions of one or more of the above-described embodiment(s) and/or controlling the one or more circuits to perform the functions of one or more of the above-described embodiment(s). The computer may comprise one or more processors (e.g., central processing unit (CPU), micro processing unit (MPU)) and may include a network of separate computers or separate processors to read out and execute the computer executable instructions. The computer executable instructions may be provided to the computer, for example, from a network or the storage medium. The storage medium may include, for example, one or more of a hard disk, a random-access memory (RAM), a read only memory (ROM), a storage of distributed computing systems, an optical disk (such as a compact disc (CD), digital versatile disc (DVD), or Blu-ray Disc (BD)™), a flash memory device, a memory card, and the like.
While the present disclosure has been described with reference to exemplary embodiments, it is to be understood that the present disclosure is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2023-097247, filed Jun. 13, 2023, Japanese Patent Application No. 2023-191126, filed Nov. 8, 2023, Japanese Patent Application No. 2023-191127, filed Nov. 8, 2023, and Japanese Patent Application No. 2024-011258, filed Jan. 29, 2024, which are hereby incorporated by reference herein in their entirety.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-097247 | Jun 2023 | JP | national |
| 2023-191126 | Nov 2023 | JP | national |
| 2023-191127 | Nov 2023 | JP | national |
| 2024-011258 | Jan 2024 | JP | national |
