This application claims priority of Taiwanese Application No. 098103653, filed on Feb. 5, 2009.
1. Field of the Invention
The invention relates to modulation techniques, more particularly to a transmitter having a radio frequency modulating circuit.
2. Description of the Related Art
For real-time high-resolution image transmission with a maximum frame rate of 10 frames/sec, a data transmission rate of up to 10 Mbps is required in a wireless ultrasound capsule endoscope system.
However, when enhancement of the transmission rate of the data stream is required, baseband bandwidth for the in-phase and quadrature sequences increases, thereby resulting in higher operating frequencies of the D/A converters 92 and the filters 93. As a result, power consumption of the D/A converters 92 and the filters 93 increase. Therefore, there is a trade-off between the data transmission rate and power consumption in the conventional transmitter 900. Furthermore, the conventional transmitter 900 has a plurality of analog circuit components that are sensitive to variations of process, operational voltage and temperature such that operating stability of the conventional transmitter 900 is easily interfered.
Therefore, an object of the present invention is to provide a transmitter having a radio frequency modulating circuit that can overcome the aforesaid drawbacks of the prior art.
According to one aspect of the present invention, a transmitter comprises:
a phase shift keying (PSK) modulating circuit adapted for modulating a data stream to be transmitted into a modulated data sequence;
a radio frequency modulating circuit including
an antenna coupled to the power amplifier for transmission of the phase-modulated output amplified by the power amplifier.
According to another aspect of the present invention, there is provided a radio frequency modulating circuit adapted for modulating a data sequence into a phase-modulated output. The radio frequency modulating circuit comprises:
at least one phase multiplexer that includes
a conversion amplifier coupled to the phase followers of the phase multiplexer, and operable in accordance with the complementary-level carrier signals of a conducting one of the phase followers so as to output the phase-modulated output corresponding to the data sequence; and
a power amplifier coupled to the conversion amplifier for receiving the phase-modulated output therefrom, and amplifying power of the phase-modulated output.
Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which:
a to 3d are timing diagrams illustrating respectively four different carrier signals (P0, P90, P180, P270) generated by a frequency synthesizer of the first preferred embodiment;
Before the present invention is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure.
Referring to
The PSK modulating circuit 1 is adapted for modulating a data stream to be transmitted into a modulated data sequence in a known manner. In this embodiment, the PSK modulating circuit 1 is an offset quadrature phase shift keying (OQPSK) modulating circuit. The modulated data sequence includes two complementary-level in-phase sequences (φ,
) and two complementary-level quadrature sequences (φ
0
φ
). Each of the complementary-level in-phase sequences (φ
1
) and the complementary-level quadrature sequences (φ
0
) has a one-bit width, and a transmission rate of 7.5 MHz equal to half of that of the data stream.
The frequency synthesizer 4, such as a multiphase local oscillator, is adapted to receive an oscillating signal, and generates four different carrier signals (P0, P90, P180, P270), as shown in
The radio frequency modulating circuit 2 includes a phase multiplexer 21 coupled to the PSK modulating circuit 1 and the frequency synthesizer 4, a conversion amplifier 22 coupled to the phase multiplexer 21, and a power amplifier 23 coupled to the conversion amplifier 22.
As shown in 1
) and the complementary-level quadrature sequences (φ
0
) from the PSK modulating circuit 1, and is operable to enable conduction of one of the phase followers (DIFF_P) therethrough in response to the complementary-level in-phase sequences (φ
1
) and the complementary-level quadrature sequences (φ
0
) received thereby.
The conversion amplifier 22 is coupled to the phase followers (DIFF_P) of the phase multiplexer 2, and is operable in accordance with the complementary-level carrier signals (P0, 180), (P90, P270) of a conducting one of the phase followers (DIFF_P) so as to output a phase-modulated output corresponding to the data stream.
The power amplifier 23 receives the phase-modulated output from the conversion amplifier 22, and amplifies power of the phase-modulated output.
The antenna 5 is coupled to the power amplifier 23 for transmission of the phase-modulated output amplified by the power amplifier 23, as shown in FIG. 2.
In this embodiment, each phase follower (DIFF_P) of the phase multiplexer 21 of the radio frequency modulating circuit 2 includes a differential pair of first and second transistors having gates for receiving respectively the corresponding pair of the complementary-level carrier signals (P0, 180), (P90, P270). The selector 211 includes first, second and third selecting units (DIFF_C1, DIFF_C2, DIFF_C3). Each of the first and second selecting units (DIFF_C1, DIFF_C2) is coupled to two corresponding ones of the phase followers (DIFF_P), and is operable in response to the complementary-level quadrature sequences (φ0
). Each of the first and second selecting units (DIFF_C1, DIFF_C2) includes a differential pair of transistors having gates for receiving respectively the complementary-level quadrature sequences (φ
0
), drains coupled respectively to the two corresponding ones of the phase followers (DIFF_P), and sources coupled to each other. The third selecting unit (DIFF_C3) is coupled between a reference node (n) and the first and second selecting units (DIFF_C1, DIFF_C2), and is operable in response to the complementary-level in-phase sequences (φ
1
). The third selecting unit (DIFF_C3) includes a differential pair of transistors having gates for receiving respectively the complementary-level in-phase sequences (φ
1
), drains coupled respectively to the first and second selecting units (DIFF_C1, DIFF_C2), and sources coupled to the reference node (n). One of the first and second selecting units (DIFF_C1, DIFF_C2) coupled to the conducting one of the phase followers (DIFF_P) is operable to establish electrical connection between the conducting one of the phase followers (DIFF_P) and the third selecting unit (DIFF_C3) therethrough in response to the complementary-level quadrature sequences (φ
0
). The third selecting unit (DIFF_C3) is operable to establish electrical connection between the reference node (n) and said one of the first and second selecting units (DIFF_C1, DIFF_C2) therethrough in response to the complementary-level in-phase sequences (φ
1
) such that the conducting one of the phase followers (DIFF_P) is connected to the reference node (n) through said one of the first and second selecting units (DIFF_C1, DIFF_C2) and the third selecting unit (DIFF_C3). In this embodiment, the reference node (n) is coupled to ground through a current source.
In this embodiment, the conversion amplifier 22 includes a first current mirror (CM1) coupled to drains of the first transistors of the phase followers (DIFF_P), a second current mirror (CM2) coupled to drains of the second transistors of the phase followers (DIFF_P), and a third current mirror (CM3) coupled among the first and second current mirrors (CM1, CM2) and ground.
When the first transistor of the conducting one of the phase followers (DIFF_P) conducts in response to the respective one of the complementary-level carrier signals (P0, 180), (P90, P270), the first current mirror (CM1) is operable so that the phase-modulated output outputted by the conversion amplifier 22 has a high level. When the second transistor of the conducting one of the phase followers (DIFF_P) conducts in response to the other one of the complementary-level carrier signals (P0, 180), (P90, P270), the second current mirror (CM2) is operable so that the phase-modulated output outputted by the conversion amplifier 22 has a low level.
For example, when φ1:0
=00, the selector 211 is operable such that a leftmost phase follower (DIFF_P) of
1:0
=00, the level of the phase-modulated output follows that of the carrier signal (P0).
Similarly, when φ1:0
=01, the level of the phase-modulated output follows that of the carrier signal (P90). When φ
1:0
=11, the level of the phase-modulated output follows that of the carrier signal (P180). When φ
1:0
=10, the level of the phase-modulated output follows that of the carrier signal (P270).
It is noted that each of the first, second and third selecting units (DIFF_C1, DIFF_C2, DIFF_C3) and the phase followers (DIFF_P) is embodied as a differential pair. Since a difference between high and low levels of each of the sequences (φ1:0
), generated by the PSK modulating circuit 1 is large enough to trigger one transistor of a respective one of the first, second and third selecting units (DIFF_C1, DIFF_C2, DIFF_C3) into conduction and to cut off the other transistor of the same, the selector 211 is capable of effective conduction of one of the phase followers (DIFF_P) therethrough. Furthermore, since a difference between high and low levels of each of the carrier signals (P0, P90, P180, P270) generated by the frequency synthesizer 4 is large enough to trigger only one of the first and second transistors of a respective one of the phase followers (DIFF_P) into conduction at any time, the level of the phase-modulated output can accurately follow a corresponding one of the carrier signals (P0, P90, P180, P270). Therefore, the radio frequency modulating circuit 2 can operate with a high data transmission rate. Moreover, since such a differential pair has a relatively small operating current that is lower than 0.4 mA in this embodiment, the radio frequency modulating circuit 2 has relatively low power consumption.
Since the PSK modulating circuit 1 is an OQPSK modulating circuit in this embodiment, transition points of the in-phase sequence (φ1
) and the quadrature sequence (φ
0
) are staggered. In other words, at any time, transition of at most one of the in-phase sequence (φ
1
) and the quadrature sequence (φ
0
) occurs. For example, if φ
1:0
generated currently by the PSK modulating circuit 1 is “01”, a next transition will be “01”, “00” or “00” rather than “10”, as shown in
However, in other embodiments, the PSK modulating circuit 1 can be a QPSK modulating circuit, and the in-phase sequence (φ1
) and the quadrature sequence (φ
0
) may have the same transition point. That is, if φ
1:0
generated currently by the PSK modulating circuit 1 is “01”, the next transition will be “01”, “00”, “11” or “10”, as shown in
1
), and only the complementary-level carrier signals (P0, P180) are generated by the frequency synthesizer (not shown).
The radio frequency modulating circuit 2′ of the second preferred embodiment differs from that of the first preferred embodiment in that the phase multiplexer 21′ includes two of the phase followers (DIFF_P) and that the selector 211′ includes a differential pair of transistors. Each phase follower (DIFF_P) operates in accordance with the carrier signals (P0, P180) received thereby. The transistors of the selector 211′ have gates coupled to the PSK modulating circuit for receiving respectively the complementary-level in-phase sequences (φ1
) therefrom, drains coupled respectively to the phase followers (DIFF_P), and sources coupled to each other. One of the transistors of the selector 211′ coupled to the conducting one of the phase followers (DIFF_P) conducts in response to the respective one of the complementary-level in-phase sequences (φ
1
) received thereby.
In this embodiment, the radio frequency modulating circuit 2″ includes a parallel connection of a number (K+1) of the phase multiplexers 21 coupled to the conversion amplifier 22, where K=2Y−1, and Y is a positive integer. For example, Y is 3, and K is 7. The selector of a first one of the phase multiplexers 21 is coupled to the PSK modulating circuit for receiving the sequences (φ1:0
) therefrom.
The radio frequency modulating circuit 2″ further includes a series connection of a number (K) of shift registers 24. Each shift register 24 has an input end and an output end. The output end of a jth one of the shift registers 24 is coupled to the selector of a (j+1)th one of the phase multiplexers 21, where 1≦j≦K. Each shift register 24 receives an input signal through the input end thereof, and subsequently outputs the input signal received thereby to the selector of a corresponding one of the phase multiplexers through the output end thereof after a time delay. The sequences (φ1:0
) from the PSK modulating circuit serve as the input signal received by a first one of the shift registers 24.
In this embodiment, the PSK modulating circuit is an OQPSK modulating circuit, and K=7. A transmission rate of the sequences (φ1:0
) generated by the PSK modulating circuit is 7.5 MHz (=1/T). It is noted that a reciprocal of the time delay is equal to (K+1) times a switching frequency of the sequences (φ
1:0
). Therefore, the operating frequency of each shift register 24 is (K+1)/T=8/T=60 MHz. The greater the number K, the less will be the variation of the phase of the phase-modulated output within each time delay.
The shift registers 24 and the phase multiplexers 21 constitute a finite impulse response (FIR) architecture that can achieve averaging phase variation effect to reduce a phase variation rate of the phase-modulated output, thereby reducing transmission bandwidth.
In sum, since the radio frequency modulating circuit 2, 2′, 2″ directly receives the sequences (φ1:0
) each being in a digital format, the digital-to-analog converters 92 and the filters 93 in the conventional transmitter 900 can be omitted. Therefore, the transmitter 100 of the present invention has lower power consumption and is less sensitive to variations of process, operating voltage and temperature. Furthermore, the phase multiplexer 21, 21′ permits a high data transmission rate, and reduces linearity requirement for the power amplifier 23.
While the present invention has been described in connection with what are considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
Number | Date | Country | Kind |
---|---|---|---|
098103653 | Feb 2009 | TW | national |