Radio frequency (RF) transmitters, such as those included in mobile wireless telephone handsets (also referred to as cellular telephones) and other portable radio transceivers, generally include a power amplifier. The power amplifier is typically the final stage of the transmitter circuitry. In some types of transmitters, achieving linear power amplification is of great importance. However, various factors can hamper linear operation. For example, in a transmitter of the type generally included in some types of mobile wireless telephone handsets, where the power amplifier receives the output of an upconversion mixer, the relatively large signal that such a mixer typically outputs can drive the power amplifier into nonlinear operation. Increasing power amplifier current is one technique for promoting linear operation in such a transmitter, but it does not work well in all instances.
As illustrated in
It would be desirable to promote transconductance amplifier linearity in a manner that does not consume excessive current, degrade amplifier noise performance, or sacrifice bias voltage gain controllability.
Embodiments of the invention relate to a power amplifier circuit comprising an amplifier MOSFET and a predistorter MOSFET. The amplifier MOSFET has a gate terminal coupled to a first bias voltage and coupled to an input voltage signal via a linear coupling capacitance. (The term “coupled” as used herein means connected via zero or more intermediate elements.) The amplifier MOSFET source and drain terminals, which provide the amplifier output current signal, are coupled to a reference voltage, such as ground or a supply voltage, and a current source or sink. The predistorter MOSFET is connected between the gate terminal of the amplifier MOSFET and a second bias voltage signal. The source and drain terminals of the predistorter MOSFET are connected together so that it provides a nonlinear capacitance at the gate terminal of the amplifier MOSFET.
The gate-source voltage of the amplifier MOSFET is the input voltage signal capacitively divided between the input linear coupling capacitance and the combined non-linear capacitances of the amplifier MOSFET and predistorter MOSFET. As a result, the gate-source voltage of the amplifier MOSFET is nonlinear or predistorted. This predistortion promotes cancellation of the distortion or nonlinearity contributed by the amplifier MOSFET.
Other systems, methods, features, and advantages of the invention will be or become apparent to one with skill in the art upon examination of the following figures and detailed description.
The invention can be better understood with reference to the following figures. The components within the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts throughout the different views.
As illustrated in
The gate terminal of amplifier MOSFET 36 is coupled to a first bias voltage signal 40 (V_BIAS) via an RF choke 42. The gate terminal of amplifier MOSFET 36 is also coupled to input voltage signal 34 via a linear coupling capacitance 44. The source terminal of amplifier MOSFET 36 is connected to ground. The drain terminal of amplifier MOSFET 36 is connected to current source circuitry, which is not shown for purposes of clarity but is indicated by the ellipsis (“ . . . ”) symbol.
The source and drain terminals of predistorter MOSFET 38 are connected together, thereby effectively defining a (nonlinear) capacitance. Predistorter MOSFET 38 is connected between the gate terminal of amplifier MOSFET 36 and a second bias voltage signal 46 (V_BIAS_PMOS) such that the gate terminal of predistorter MOSFET 38 is connected to the gate terminal of amplifier MOSFET 36, and the source and drain terminals of predistorter MOSFET 38 are connected to second bias voltage signal 46. This biasing of predistorter MOSFET 38 causes it to provide a nonlinear capacitance at the gate terminal of amplifier MOSFET 36.
Second bias voltage signal 46 and the size of predistorter MOSFET 38 are selected so that the combination of the nonlinear capacitance of predistorter MOSFET 38 and the non-linear capacitance of amplifier MOSFET 36 defines a capacitance that behaves inversely to the manner in which the input capacitance of amplifier MOSFET 36 alone behaves. Note, however, that the nonlinear capacitance of predistorter 38 does not simply cancel out the nonlinear capacitance of amplifier MOSFET 36. Rather, gate-source voltage of amplifier MOSFET 36 is the input voltage signal 34 capacitively divided between linear coupling capacitance 44 and the combined nonlinear capacitances of predistorter MOSFET 38 and amplifier MOSFET 36. As a result, the gate-source voltage of amplifier MOSFET 36 is nonlinear or predistorted. The predistortion cancels out the distortion or nonlinearity of amplifier MOSFET 36. The effect can be better understood with reference to the following equations.
In prior transconductance amplifier circuits such as amplifier driver stage 14 shown in
V—GS26=V_IN*[C28/(C28+C26GG)], (1)
where V_GS26 is the gate-source voltage of amplifier MOSFET 26, C28 is the capacitance of coupling capacitor 28, and C26GG is the capacitance of amplifier MOSFET 26 at its gate terminal;
I_OUT=Gm26*V—GS26=Gm26*V_IN*[C28/(C28GG+C26GG)], (2)
where Gm26 is the transconductance of amplifier MOSFET 26; and
Gmeff=Gm26*[C28GG/(C28GG+C26GG)], (3)
where Gmeff is the effective transconductance of amplifier driver stage 14.
From equation (3), it can be seen that the multiplication of a nonlinear transconductance and a nonlinear capacitive division, where the nonlinearities are unrelated to each other, results in a combined nonlinear effective transconductance (Gmeff).
In contrast, in the exemplary transconductance amplifier circuit 30 described above with reference to
I_OUT=Gm36*V—GS36=Gm36*V_IN*[C44/(C44+C36GG+C38GG)], (4)
where Gm36 is the transconductance of amplifier MOSFET 36, V_GS36 is the gate-source voltage of amplifier MOSFET 36, C44 is the linear capacitance of coupling capacitor 44, C36GG is the nonlinear capacitance of amplifier MOSFET 36 at its gate terminal, and C38GG is the nonlinear capacitance of predistorter MOSFET 38 at its gate terminal; and
Gmeff=Gm36*[C44/(C44+C36GG+C38GG)], (5)
where Gmeff is the effective transconductance of amplifier circuit 30.
From equation (5), it can be seen that the multiplication of a nonlinear transconductance and a nonlinear capacitive division, where the nonlinearities are adjusted to cancel each other out, results in a linear effective transconductance (Gmeff). The nonlinear capacitance of predistorter MOSFET 38 can be adjusted by selecting the size of predistorter MOSFET 38 and the value of second bias voltage 46. The total nonlinear capacitance of predistorter MOSFET 38 and the total nonlinear capacitance of amplifier MOSFET 36 should be made similar to each other, i.e., having similar nonlinear characteristics. The combination of the size of predistorter MOSFET 38 and the value of second bias voltage 46 that results in the greatest reduction in nonlinear operation of amplifier circuit 30 and results in the total nonlinear capacitance of predistoter MOSFET 38 and the total nonlinear capacitance of amplifier MOSFET 36 being similar to each other can be determined empirically or by any other suitable means. Empirical evaluations can be made through circuit simulations, i.e., modeling the circuit through software means on a suitable workstation computer (not shown), using commonly available simulator software. In a simulation, second bias voltage 46 and the length and width of predistorter MOSFET 38 can be swept through ranges of values with respect to one another, and how linearly or nonlinearly amplifier circuit 30 behaves in response can be observed and the optimal values noted. Through such means, persons skilled in the art to which the invention relates can quickly and easily determine suitable values for one or both of the size of predistorter MOSFET 38 and second bias voltage 46. As an example, amplifier MOSFET 36 could be 4.80 micrometers wide and 0.24 micrometers long; predistorter MOSFET 38 could be 6.72 micrometers wide and 0.24 micrometers long; and second bias voltage 46 could be 650 millivolts. First bias voltage 40 can be, for example, 1.1 volts.
An alternative amplifier circuit 48 is illustrated in
The gate terminal of amplifier MOSFET 54 is coupled to a first bias voltage signal 58 (V_BIAS) via an RF choke 60. The gate terminal of amplifier MOSFET 54 is also coupled to input voltage signal 52 via a linear coupling capacitance 62. The source terminal of amplifier MOSFET 54 is connected to a supply voltage (VCC). The drain terminal of amplifier MOSFET 54 is connected to a current sink circuit, which is not shown for purposes of clarity but is indicated by the ellipsis (“ . . . ”) symbol.
The source and drain terminals of predistorter MOSFET 56 are connected together, thereby effectively defining a (nonlinear) capacitance. Predistorter MOSFET 56 is connected between the gate terminal of amplifier MOSFET 54 and a second bias voltage signal 64 (V_BIAS_NMOS) such that the gate terminal of predistorter MOSFET 56 is connected to the gate terminal of amplifier MOSFET 54, and the source and drain terminals of predistorter MOSFET 56 are connected to second bias voltage signal 64. This biasing of predistorter MOSFET 56 causes it to provide a nonlinear capacitance at the gate terminal of amplifier MOSFET 54.
Second bias voltage signal 64 and the size of predistorter MOSFET 56 are selected so that the combination of the nonlinear capacitance of predistorter MOSFET 56 and the non-linear capacitance of amplifier MOSFET 54 defines a capacitance that behaves inversely to the manner in which the input capacitance of amplifier MOSFET 54 alone behaves. The predistortion cancels out the distortion or nonlinearity of amplifier MOSFET 54.
Another alternative amplifier circuit 66 is illustrated in
The gate terminal of amplifier MOSFET 72 is coupled to a first bias voltage signal 76 (V_BIAS) via an RF choke 78. The gate terminal of amplifier MOSFET 72 is also coupled to input voltage signal 70 via a linear coupling capacitance 80. The source terminal of amplifier MOSFET 72 is connected to ground. The drain terminal of amplifier MOSFET 72 is connected to a current source circuit, which is not shown for purposes of clarity but is indicated by the ellipsis (“ . . . ”) symbol.
The source and drain terminals of predistorter MOSFET 74 are connected together, thereby effectively defining a (nonlinear) capacitance. Predistorter MOSFET 74 is connected between the gate terminal of amplifier MOSFET 72 and a second bias voltage signal 82 (V_BIAS_NMOS) such that the gate terminal of predistorter MOSFET 74 is connected to second bias voltage signal 82, and the source and drain terminals of predistorter MOSFET 74 are connected to the gate terminal of amplifier MOSFET 72. This biasing of predistorter MOSFET 74 causes it to provide a nonlinear capacitance at the gate terminal of amplifier MOSFET 72.
Second bias voltage signal 82 and the size of predistorter MOSFET 74 are selected so that the combination of the nonlinear capacitance of predistorter MOSFET 74 and the non-linear capacitance of amplifier MOSFET 72 defines a capacitance that behaves inversely to the manner in which the input capacitance of amplifier MOSFET 72 alone behaves. The predistortion cancels out the distortion or nonlinearity of amplifier MOSFET 72.
The following equations apply to the embodiment shown in
I_OUT=Gm72*V—GS72=Gm72*V_IN*[C80/(C80+{C72GG+(C74DD+C74SS)})], (6)
where Gm36 is the transconductance of amplifier MOSFET 36, V_GS36 is the gate-source voltage of amplifier MOSFET 36, C44 is the linear capacitance of coupling capacitor 44, C72GG is the nonlinear capacitance of amplifier MOSFET 72 at its gate terminal, C74DD is the nonlinear capacitance of predistorter MOSFET 36 at its drain terminal, and C74ss is the nonlinear capacitance of predistorter MOSFET 38 at its source terminal; and
Gmeff=Gm72*[C80/(C80+{C72GG+(C74DD+C74SS)})], (7)
where Gmeff is the effective transconductance of amplifier circuit 66.
From equation (7), it can be seen that the multiplication of a nonlinear transconductance and a nonlinear capacitive division, where the nonlinearities are adjusted to cancel each other out, results in a linear effective transconductance (Gmeff). The nonlinear capacitance of predistorter MOSFET 74 can be adjusted by selecting the size of predistorter MOSFET 74 and/or the value of second bias voltage 82.
Still another alternative amplifier circuit 84 is illustrated in
The gate terminal of amplifier MOSFET 90 is coupled to a first bias voltage signal 94 (V_BIAS) via an RF choke 96. The gate terminal of amplifier MOSFET 90 is also coupled to input voltage signal 88 via a linear coupling capacitance 98. The source terminal of amplifier MOSFET 90 is connected to a supply voltage (VCC). The drain terminal of amplifier MOSFET 90 is connected to a current drain circuit, which is not shown for purposes of clarity but is indicated by the ellipsis (“ . . . ”) symbol.
The source and drain terminals of predistorter MOSFET 92 are connected together, thereby effectively defining a (nonlinear) capacitance. Predistorter MOSFET 92 is connected between the gate terminal of amplifier MOSFET 90 and a second bias voltage signal 100 (V_BIAS_PMOS) such that the gate terminal of predistorter MOSFET 92 is connected to second bias voltage signal 100, and the source and drain terminals of predistorter MOSFET 92 are connected to the gate terminal of amplifier MOSFET 90. This biasing of predistorter MOSFET 92 causes it to provide a nonlinear capacitance at the gate terminal of amplifier MOSFET 90.
Second bias voltage signal 100 and the size of predistorter MOSFET 92 are selected so that the combination of the nonlinear capacitance of predistorter MOSFET 92 and the non-linear capacitance of amplifier MOSFET 90 defines a capacitance that behaves inversely to the manner in which the input capacitance of amplifier MOSFET 90 alone behaves. The predistortion cancels out the distortion or nonlinearity of amplifier MOSFET 90.
Improved linearity in a transconductance amplifier of the type described above is illustrated in
As illustrated in
As illustrated in
While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention. Accordingly, the invention is not to be restricted except in light of the following claims.
This application is a continuation of International Application No. PCT/US2009/054023, filed Aug. 17, 2009, the benefit of the filing date of which is hereby claimed and the specification of which is incorporated herein by this reference.
Number | Name | Date | Kind |
---|---|---|---|
7110718 | Szczeszynski et al. | Sep 2006 | B1 |
7200370 | Behzad | Apr 2007 | B2 |
7408408 | Kang et al. | Aug 2008 | B2 |
20030193371 | Larson et al. | Oct 2003 | A1 |
20040000952 | Lautzenhiser et al. | Jan 2004 | A1 |
20070052479 | Wang | Mar 2007 | A1 |
20070182485 | Ko | Aug 2007 | A1 |
20070285162 | Vitzilaios et al. | Dec 2007 | A1 |
20080030274 | Busking | Feb 2008 | A1 |
20080136529 | Liao et al. | Jun 2008 | A1 |
20080180175 | Arai | Jul 2008 | A1 |
20080211585 | Karoui et al. | Sep 2008 | A1 |
20080211858 | Mackey et al. | Sep 2008 | A1 |
20090243727 | Bockelman et al. | Oct 2009 | A1 |
20090251222 | Khorram | Oct 2009 | A1 |
20100156539 | Ha et al. | Jun 2010 | A1 |
20100182057 | Mei | Jul 2010 | A1 |
Number | Date | Country |
---|---|---|
101999207 | Mar 2011 | CN |
2004248161 | Sep 2004 | JP |
2008-283407 | Nov 2008 | JP |
WO 2009145957 | Dec 2009 | WO |
Entry |
---|
Cheng-Chi Yen et al, “A 0.25-μm 20-dBm 2.4-GHz CMOS Power Amplifier with an Integrated Diode Linearizer,” IEEE Microwave and Wireless Components Letters, vol. 13, No. 2, dated Feb. 2003. |
International Search Report re International Application No. PCT/US2009/054023, mailed May 4, 2010, in 3 pages. |
International Preliminary Report on Patentability and Written Opinion re International Application No. PCT/US2009/054023, issued Feb. 21, 2012 in 5 pages. |
Supplementary European Search Report, re Application No. EP 09 84 8548, dated Nov. 6, 2013, in 9 pages. |
Number | Date | Country | |
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20120149316 A1 | Jun 2012 | US |
Number | Date | Country | |
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Parent | PCT/US2009/054023 | Aug 2009 | US |
Child | 13397917 | US |