This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-005681, filed on Jan. 15, 2008 and the prior Japanese Patent Application No. 2008-246660, filed on Sep. 25, 2008; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a radio frequency switch circuit.
2. Background Art
A multi-port radio frequency switch circuit such as an SP5T (single-pole 5-throw) switch is used in multi-mode multi-band wireless equipment. In this case, multi-stage series connected through FETs are provided between an antenna terminal and five RF terminals, and multi-stage series connected shunt FETs are provided between each RF terminal and the ground.
For example, for conduction between the first RF terminal and the antenna terminal, the through FETs and shunt FETs are controlled as follows. The n-stage series connected through FETs between the first RF terminal and the antenna terminal are turned on, and the n-stage series connected shunt FETs between the first RF terminal and the ground are turned off. At the same time, the through FETs between the other RF terminals and the antenna terminal are all turned off, and the shunt FETs between the other RF terminals and the ground are all turned on.
This off-state of n-stage series connected transistors is likely to cause harmonic distortion and higher-order intermodulation distortion based on the nonlinearity of off-capacitance with respect to voltage. In GSM (Global System for Mobile Communications) and UMTS (Universal Mobile Telecommunications System), these distortions need to be reduced to below the system requirements.
JP-T-2005-515657 discloses a technique related to a switch circuit and a method of switching radio frequency signals for use in wireless applications, based on the SOI (silicon-on-insulator) or other technology. This technique provides an RF switch circuit including a first and second switching transistor grouping and a first and second shunting transistor grouping, which allows easy integration.
However, even if this technique is used, it is not easy to reduce harmonic distortion and higher-order intermodulation distortion to meet the requirements of GSM and UMTS without increasing the chip size of the radio frequency switch circuit.
According to an aspect of the invention, there is provided a radio frequency switch circuit including: an antenna terminal; a first and second RF terminal; a first through transistor placed between the antenna terminal and the first RF terminal; a second through transistor placed between the antenna terminal and the second RF terminal; a first shunt transistor placed between ground and the first RF terminal; a second shunt transistor placed between the ground and the second RF terminal; and a distortion compensation circuit including a reverse parallel connected MOS capacitor whose capacitance around 0 volts has voltage dependence that is convex to the minus direction, the distortion compensation circuit being operable to compensate for voltage dependence of off-capacitance around 0 volts of the first and second through transistor and the first and second shunt transistor that is convex to the plus direction, electrical connection between the antenna terminal and the first and second RF terminal being switchable.
According to an aspect of the invention, there is provided a radio frequency switch circuit including: an antenna terminal; a first and second RF terminal; a first through transistor placed between the antenna terminal and the first RF terminal; a second through transistor placed between the antenna terminal and the second RF terminal; a first shunt transistor placed between ground and the first RF terminal; a second shunt transistor placed between the ground and the second RF terminal; and a distortion compensation circuit including a reverse parallel connected MOS capacitor and placed at least one of between the antenna terminal and the ground and between the ground and one of the first and second RF terminal, electrical connection between the antenna terminal and the first and second RF terminal being switchable.
According to an aspect of the invention, there is provided a radio frequency switch circuit including: an antenna terminal; a first and second RF terminal; a first through transistor placed between the antenna terminal and the first RF terminal; a second through transistor placed between the antenna terminal and the second RF terminal; a first shunt transistor placed between ground and the first RF terminal; a second shunt transistor placed between the ground and the second RF terminal; and a distortion compensation circuit including a reverse parallel connected MOS capacitor, at least one of the first through transistor, the second through transistor, the first shunt transistor, and the second shunt transistor being connected parallel to the distortion compensation circuit, and electrical connection between the antenna terminal and the first and second RF terminal being switchable.
Embodiments of the invention will now be described with reference to the drawings.
In this embodiment, a distortion compensation circuit 50 is placed between the antenna terminal 10 and the ground. The distortion compensation circuit 50 is composed of a reverse connected MOS capacitor and compensates for nonlinear distortion based on the voltage dependence of off-capacitance Coff in the off-state of FETs. The distortion compensation circuit 50 is described later in detail.
In this example, through FETs (through transistors) 30 placed between the antenna terminal 10 and the first RF terminal (hereinafter RF1 terminal) 20 are turned on, shunt FETs (shunt transistors) 40 placed between the RF1 terminal and the ground are turned off, through FETs placed between the antenna terminal 10 and each of the RF terminals (RF2, RF3, RF4, RF5) except the RF1 terminal are turned off, and shunt FETs placed between the ground and the RF terminals except the RF1 terminal are turned on. Then, conduction can be established between the RF1 terminal and the antenna terminal 10. Normally, switching is performed so that the antenna terminal 10 is electrically connected to one of the RF1-RF5 terminals.
In the case where the FET is a MOSFET, this switching of electrical connection can be controlled by a gate voltage applied from a control signal line to each MOSFET. The gate of the through FET, Tij (i=1, . . . , m, j=1, . . . , n) is connected to a control signal line Conia (i=1, . . . , m) via a high resistance. The gate of the shunt FET, Sij (i=1, . . . , m, j=1, . . . , q) is connected to a control signal line Conib (i=1, . . . , m) via a high resistance. Each control signal line is connected to a control circuit, not shown.
The control circuit illustratively includes a decoder, a negative voltage generation circuit, and a drive circuit. Power consumption can be reduced by using a CMOS structure for the through MOSFETs, the shunt MOSFETs, and the control circuit constituting the radio frequency switch circuit. However, in the conventional bulk CMOS structure, there is a high diffusion capacitance with respect to the Si substrate, and the conductive substrate causes radio frequency transmission loss. Hence, the operation of the radio frequency switch circuit is unsatisfactory. Use of the SOI process is more preferable because it enables rapid operation of MOSFETs.
The through FETs 30 placed between the RF1 terminal and the antenna terminal 10 are configured as n-stage series connected MOSFETs (T1j: j=1, . . . , n). In general, the through FETs placed between the i-th RF terminal and the antenna terminal 10 are n-stage series connected MOSFETs (Tij: i=1, . . . , m, j=1, . . . , n). It is noted that with regard to Tij connected to different RF terminals, the number of series connected stages does not need to be totally uniform.
Likewise, the shunt FETs placed between the i-th RF terminal and the ground are q-stage series connected MOSFETs (Sij: i=1, . . . , m, j=1, . . . , q). Again, the number of series connected stages does not need to be totally uniform. The shunt FETs -can improve isolation of radio frequency signals between the conducting RF terminal and the non-conducting RF terminal.
In an off-state MOSFET, which can be regarded as a nonlinear capacitance, the nonlinearity increases with the increase of the drain-source voltage. Hence, signal distortion due to nonlinearity can be reduced by the n-stage series connection of through MOSFETs (Tij) to decrease the amplitude of voltage applied to one MOSFET by a factor of n, as compared with using one MOSFET. Likewise, signal distortion can be reduced by the q-stage series connection of shunt MOSFETs (Sij). In this figure, the number of series connected stages, n and q, is set to 8, but the invention is not limited thereto. Furthermore, an on-state MOSFET can be regarded as a nonlinear resistance, and again, the nonlinearity increases with the increase of the drain-source voltage.
It is preferable to provide a high resistance (not shown) in parallel between the source and drain electrode of each of the MOSFETs (Tij and Sij) because the operation can be made uniform across the plurality of MOSFETs.
The fully depleted SOI, in which the thickness of the SOI layer 64 is smaller than the channel depletion depth and the channel portion is depleted, is more preferable because rapid operation can be achieved. It is noted that the MOSFET may have a p-channel structure.
In
In the SOI layer 64, the neighborhood of the directly underlying portion of the gate electrode 70 is a back gate. A parasitic diode 76 occurs between the back gate and the source region 68, and a parasitic diode 78 occurs between the back gate and the drain region 72. That is, even in the fully depleted type, in the off-state, the gate electrode 70 is negatively biased, and hence the channel is in the accumulation state. Thus, in the off-state, holes occur in the channel layer, and the parasitic diode 76, 78 occurs between the source and the channel and between the drain and the channel. These parasitic diodes 76, 78 have an off-capacitance Coff, which exhibits nonlinearity with respect to the bias voltage.
Next, the off-distortion compensation circuit 50 is described.
Preferably, the resistance Rj is e.g. approximately 10 kΩ to several ten kΩ, because it enables p reverse parallel connected MOSFETs to be operated uniformly. The MOSFETs constituting the distortion compensation circuit 50, the through MOSFETs (Tij), the shunt MOSFETs (Sij), and the resistances Rj can be integrated on the same substrate. They are series connected and parallel connected by interconnect layers, and a small, one-chip radio frequency switch circuit can be implemented.
On the other hand, the voltage dependence of the off-capacitance Coff of the MOSFET with respect to the drain-source voltage Vds is maximized around 0 V and has nonlinearity that is convex to the plus direction (upward). Thus, in a desired power region, the nonlinearity of the off-capacitance Coff of the MOSFET can be compensated by using the downward convex nonlinearity of the distortion compensation circuit 50 placed between the antenna terminal 10 and the ground.
In this embodiment, in the MOSFET constituting the distortion compensation circuit 50, the gate oxide film thickness Tox is 9 nm, the gate length Lg is 0.25 μm, and the threshold voltage Vth is 0.35 V, like in the through MOSFET and the shunt MOSFET. On the other hand, the gate width Wg3 is 4 μm, which is different from the gate width Wg1 (3 mm) of the through MOSFET and the gate width Wg2 (0.6 mm) of the shunt MOSFET. The number of series connected stages, p, is set to 8, which is equal to the number of series connected stages of through MOSFETs and shunt MOSFETs, n and q, but the invention is not limited thereto. Preferably, the gate width Wg3 and the number of series connected stages p are optimally adapted to the requirements of the radio frequency switch circuit. It is noted that the reverse connected MOS capacitance can be implemented by connecting the drain and the source of the MOSFET as in
In the case where a disturbance wave f2 exists near the transmit wave having a frequency of f1, the third intermodulation product having a frequency of 2f1-f2 or 2f2-f1 occurs near the frequency f1 and f2, causes interference, and decreases the communication quality. Hence, this case is unfavorable.
In the case where there are five RF terminals as in
In this case, at both ends of on-state T1j (j=1, . . . , n), off-state S1j, T2j, T3j, T4j, T5j are placed between them and the ground. That is, in the multi-port radio frequency switch circuit, there are a large number of off-state MOSFETs electrically connected to the antenna terminal and the RF terminals electrically connected to the antenna terminal 10. Hence, it can be considered that the off-capacitance Coff is dominant in harmonic distortion and higher-order intermodulation distortion.
Furthermore, because the transmit power is sufficiently higher than the receive power, the harmonic distortion and the higher-order intermodulation distortion are higher in the case of transmitting. Moreover, the drain and the source of the MOSFET are normally left-right symmetric with respect to the center line of the gate, and there is little distortion in even orders. Hence, it is practical to aim at reducing third-order distortions such as the third harmonic distortion in
The dashed line in
On the other hand, the third intermodulation distortion IMD3 of the comparative example indicated by the dashed line is −99 dBm at the worst value. The UMTS requirement dictates that, for example, the third intermodulation distortion IMD3 is −108 dBm or less for a transmit power of 20 dBm and a disturbance power of −15 dBm. Thus, the comparative example does not satisfy the UMTS requirement.
To reduce the third intermodulation distortion IMD3, it may be contemplated to increase the number of series connected stages of through MOSFETs, n, and the number of series connected stages of shunt MOSFETs, q, to reduce the bias voltage applied per MOSFET. In this case, to prevent the insertion loss from increasing, the loss in the conducting state needs to be kept low by increasing the gate width Wg in accordance with the increase of the number of series connected stages n, q. However, this method entails the increase of the chip size of the radio frequency switch circuit, and hence limits the reduction of signal distortion.
If the charge Q(V) accumulated in the off-capacitance Coff can be expressed as a low-order approximation up to the third order using Taylor expansion with respect to the bias voltage V, it should be easy to satisfy both the GSM requirement and the UMTS requirement described above. For example, as a limit satisfying the GSM requirement, consider a radio frequency switch circuit having a harmonic distortion of −43 dBm at a transmit power of 33 dBm. In this case, assuming that the slope of the third harmonic distortion (dBm) with respect to the input power (dBm) is 3, the third harmonic distortion can be determined to be −82 dBm at a transmit power of 20 dBm.
From this, the third intermodulation distortion IMD3 can be calculated by the following formula (in the case where no reflecting wave exists):
IMD3=−82−{20−(−15)}=−117 (dBm)
If a disturbance wave (1.76 GHz) of −15 dBm inputted to the antenna terminal is totally reflected by the duplexer, IMD3 is deteriorated to −111 dBm, but it should still satisfy the UMTS requirement.
However, in practice, as shown in
In this embodiment, the distortion compensation circuit 50 can be used to compensate for nonlinearity in the voltage dependence of off-capacitance Coff and reduce the third harmonic distortion and the third intermodulation distortion. The size of the MOSFET constituting the distortion compensation circuit 50 can be made as small as approximately 0.1% of the size of the MOSFET (Tij and Sij) constituting the radio frequency switch circuit, and the chip size can be kept small.
Thus, in
Furthermore, the distortion compensation circuit 50 may be placed between any of the RF terminals and the ground. In this case, placing the distortion compensation circuit 50 between the ground and the RF terminal connected to the UMTS transceiver circuit facilitates satisfying the UMTS requirement.
As an alternative method, it may be contemplated to compensate for unwanted harmonic distortion due to the nonlinear capacitance of off-FETs by using the nonlinear impedance of on-FETs. If the level shift circuit and the active circuit used in this method are integrated into the radio frequency switch circuit, the chip size is increased, and the manufacturing process is complicated. In contrast, this embodiment realizes a simple configuration of the distortion compensation circuit based on passive circuits using a MOS capacitor, which can advantageously simplify the manufacturing process while preventing the chip size from increasing.
It is noted that the distortion compensation circuit 50, 51 is not limited to the first to third embodiment. The gate width Wg and the threshold voltage Vth of the MOSFET constituting the distortion compensation circuit 50, 51 can be varied, and the distortion compensation circuit 50, 51 can be suitably placed at one or more of the antenna terminal 10 and the RF terminals.
The UMTS (2 GHz band) transceiver circuit 96 includes a duplexer 96c for splitting transmit/receive signals, a transmit amplifier 96a, and a receive amplifier 96b. By the duplexer 96c, the receive signal from the RF5 terminal is carried to the receive amplifier 96b, and the transmit signal from the transmit amplifier 96a is carried to the RF5 terminal. Using the distortion compensation circuit 50, a radio frequency switch circuit 5 with reduced signal distortion can be realized without increasing the chip size. This illustratively serves to realize a GSM mobile phone with reduced third harmonic distortion and a UMTS mobile phone with reduced third intermodulation distortion, increases the transmission quality of wireless equipment, and facilitates downsizing.
A transistor ST and a distortion compensation circuit 52 are parallel connected between the terminal P4 and the terminal Q4. The distortion compensation circuit 52 includes a first MOS capacitor 52a in which MOSFETs having a MOS capacitance are parallel connected to each other in reverse direction, and a second MOS capacitor 52b in which MOSFETs are parallel connected to each other in reverse direction. The transistor ST is series connected and illustratively constitutes the through transistor Tij and the shunt transistor Sij.
If the transistor ST is an N-channel MOSFET, its threshold voltage Vth can be set to generally 0.1 V, for example. The threshold voltage Vth of the MOSFET (Ma1, Mb1) constituting the first MOS capacitor 52a is set to generally 0.2 V, and the threshold voltage Vth of the MOSFET (Ma2, Mb2) constituting the second MOS capacitor 52b is set to generally 0.6 V. Furthermore, the gate electrode of the transistor ST is connected to a control terminal via a resistance Rg of generally 30 kΩ. Conduction can be established between the terminal P4 and the terminal Q4 by setting the voltage of the control terminal to be higher than the threshold voltage Vth of the MOSFET, e.g., to 3 V. The path between the terminal P4 and the terminal Q4 can be interrupted by setting the voltage of the control terminal to be lower than the threshold voltage Vth, e.g., to −2 V.
It is assumed that the voltage dependence of the off-capacitance Coff of the transistor ST is generally the same as that shown in
With the source region and the drain region being grounded, the gate voltage minimizing the gate capacitance is shifted to the plus side with the increase of the channel (B+) concentration NA as 1×1017 cm−3, 2×1017 cm−3, and 4×1017 cm−3.
In this embodiment, the channel concentration NA is varied to control differently the threshold voltage Vth of the MOSFET constituting the first MOS capacitor 52a and the threshold voltage Vth of the MOSFET constituting the second MOS capacitor 52b. Thus, the characteristics of MOS capacitors having different gate voltage dependences can be combined to further facilitate compensating for the nonlinearity of the off-capacitance Coff of the transistor ST in a desired power range. Furthermore, if the size of the MOS capacitor is varied, it is easier to suitably control the amount of compensation for the off-capacitance Coff.
On the other hand, as in
This embodiment provides an SP5T switch. With regard to the through transistors Tij (i=1, . . . , m, j=1, . . . , n), for example, the threshold voltage Vth is generally 0.1 V, Wg1=4 mm, Lg=0.25 μm, and n=8. The distortion compensation circuit 52 has the configuration of
This distortion compensation circuit 52 is parallel connected between the drain and the source of each of the eight MOSFETs constituting Tij (j=1, . . . , 8), for example. In each distortion compensation circuit 52, the resistance RDij (i=1, . . . , m, j=1, . . . , n) connected parallel to the first MOS capacitor 52a and the second capacitor 52b can keep generally constant the associated source-drain DC bias of Ti1, . . . , Tin in the off-state. The gate electrode of Tij is connected to the associated control terminal via an associated high resistance RGij (i=1, . . . , m, j=1, . . . , n) so that the connection between the ANT terminal 10 and a desired RF terminal is controllable.
In this case, the through transistors are a series connection of transistors with n=8 and can be operated at a higher input power Pin than with n=1. Thus, for example, the third harmonic distortion is −44 dBm at an input power Pin of 35 dBm. On the other hand, if the distortion compensation circuit is not connected, the third harmonic distortion is −38 dBm, which is reduced by 6 dB in this embodiment. Furthermore, if the distortion compensation circuit consists only of a MOSFET having a threshold voltage Vth of generally 0.6 V as in
In the case where the shunt transistors Sij are turned off, the distortion compensation circuit can be connected parallel to each of the series connected transistors constituting the shunt transistors Sij. In this figure, the number of series connected stages is equal to n for both the through transistors Tij and the shunt transistors Sij, but the invention is not limited thereto.
In this figure, the distortion compensation circuit 53 uses at least two MOSFETs having different threshold voltages Vth. A first MOS capacitor made of MOSFETs that are parallel connected to each other in reverse direction and have a first threshold voltage, a second MOS capacitor made of MOSFETs that have a second threshold voltage, and a high resistance RKj (j=1, . . . , p) are parallel connected. It is noted that two or more MOS capacitors having different threshold voltages may be included.
The distortion compensation circuit 53 is provided between the antenna terminal 10 and the ground and can be a p-stage series connection of the above parallel circuits. It is possible to set p=n. The high resistance RKj can keep generally constant the gate-source voltage of the MOSFET constituting the p-stage series connected MOS capacitors.
In this case, the third harmonic distortion is −44 dBm at an input power Pin of 35 dBm, which is lower than −38 dBm in the case of no distortion compensation circuit and −40 dBm in the case of one threshold voltage. It is noted that the distortion compensation circuit 53 may be placed between any of the RF terminals and the ground.
In this variation shown in
The first to third, fifth, and sixth embodiment are described with reference to the SP5T switch. However, the invention is not limited thereto, but is applicable to a radio frequency switch circuit generally represented by SPnT (n≧2).
The embodiments of the invention have been described with reference to the drawings. However, the invention is not limited to these embodiments. The size, shape, material, layout and the like of the transistor, MOSFET, MOS capacitor, resistance, SOI, and distortion compensation circuit constituting the radio frequency switch circuit can be variously modified by those skilled in the art, and such modifications are also encompassed within the scope of the invention as long as they do not depart from the spirit of the invention.
Number | Date | Country | Kind |
---|---|---|---|
2008-005681 | Jan 2008 | JP | national |
2008-246660 | Sep 2008 | JP | national |