Patent Grant
7299427
The present application incorporates patent application titled “Interface for Rapid Prototyping System” by Curtis Settles, patent application Ser. No. 10/231,641, filed Aug. 30, 2002, now U.S. Pat. No. 7,212,961, by reference in its entirety.
The present invention generally relates to the field of integrated circuit design, and particularly to a system, method and apparatus for a rapid prototyping and designing an integrated circuit.
Designers of integrated circuits, and especially application specific integrated circuits, are confronted with increased complexity as the number of functions provided by the circuits increase. Faster speeds, greater numbers of components, increased size of the circuit, routing issues, software development, and the like, have all contributed to the increase in integrated circuit complexity. However, as this complexity has increased, there has not been a corresponding increase in methods and systems designed to embrace this complexity. Rather designers are confronted with outdated methodologies that while sufficient for previous designs, may not take into account the issues experienced with the higher complexity devices.
For example, ASIC designs are typically late in design and therefore late to market. Much of this delay is caused by difficulty in testing the design in a system environment early enough, and the need to “spin” silicon because of inadequate system tests.
Therefore, it would be desirable to provide a system and method for rapid prototyping of an integrated circuit.
Accordingly, the present invention is directed to a system and method for rapid prototyping. In a first aspect of the present invention, a system for prototyping an integrated circuit includes a motherboard and a plurality of daughter cards. The motherboard has a plurality of connectors suitable for receiving daughter cards, the plurality of connectors being communicatively coupled to the plurality of daughter cards over a bus matching an ASIC AMBA bus environment. The plurality of daughter cards is communicatively coupled to the motherboard utilizing the plurality of connectors. The motherboard and plurality of daughter cards are configured as an integrated circuit emulation platform for at least one of testing software and system integration of an integrated circuit emulated by the motherboard and the plurality of daughter cards.
In an additional aspect of the present invention, a method for prototyping an integrated circuit includes selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The at least one daughter card and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard and the at least one daughter card is tested.
In a further aspect of the present invention, a system for prototyping an integrated circuit includes a motherboard and a plurality of daughter cards. The motherboard has a plurality of connectors suitable for receiving daughter cards and includes multi-ported memory capability as a shared resource to the plurality of connectors of the motherboard. The plurality of daughter cards are communicatively coupled to the motherboard utilizing the plurality of connectors. The motherboard and plurality of daughter cards are configured as an integrated circuit emulation platform for at least one of testing software and system integration of an integrated circuit emulated by the motherboard and the plurality of daughter cards.
In another aspect of the present invention, a system for prototyping an integrated circuit includes a motherboard and a plurality of daughter cards. The motherboard has a plurality of connectors suitable for receiving daughter cards having a common advanced high-performance bus (AHB). The plurality of daughter cards is communicatively coupled to the motherboard utilizing the plurality of connectors. The motherboard and plurality of daughter cards are configured as an integrated circuit emulation platform for at least one of testing software and system integration of an integrated circuit emulated by the motherboard and the plurality of daughter cards.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
The numerous advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying figures in which:
Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings.
Referring generally now to
ASIC designs are typically late in design and therefore late to market. Much of this delay is caused by difficulty in testing the design in a system environment early enough, and the need to “spin” silicon because of inadequate system tests. However, though use of the present invention, a development system is provided which allows a design to be prototyped in FPGA and system software integrated prior to tape out of the first silicon, increasing the probably that the first silicon meets the desired requirements.
For instance, when designing an integrated circuit, both hardware and software may be developed to provide the desired functionality. Because of this co-development, an interdependency may be created between such hardware and software development so that one process may not continue until a corresponding part of the other process is developed, such as the development of a software architecture in conjunction with register transfer level (RTL) development. For instance, previously, the development of an integrated circuit and corresponding software may go through a variety of stages, including testing, verification, and the like before a working product could be produced, an example of such a process is shown in
However, through use of the present invention, a rapid prototyping system and method is provided which enables the circuit to be designed in an efficient and timesaving manner with reduced revisions, which may result in a time saving of several months, as shown in
Rapid Prototyping System
Referring now to
In this way, a standardized advanced microcontroller bus architecture (AMBA) based rapid prototyping vehicle may be provided. The system may be a configurable FPGA-based system which is extendable to support multiple cores and interfaces. Preferably, the system is processor independent and is thus suitable for supporting multi-instruction processing system (MIPS), advanced RISC machine (ARM), ZSP, and the like. The system may also support a common mechanical and electrical form factor and specification so that the system is customizable to meet application specific needs and extensions, which may be designed in an efficient and intuitive manner by a circuit designer. Thus, the system of the present invention may enable the ready and efficient prototyping of integrated circuits, and even the wide range of functionality desired in application specific integrated circuits.
The present invention enables rapid prototyping and reductions in development and integration time. For instance, the present invention may provide an early hardware debugging and software development platform. Additionally, as previously mentioned the present invention provides a custom CPU option due to processor independence and enables multi-processor system prototyping and debugging. Thus, the present invention may be configured to add customer logic and application specific functions. Further, the present invention demonstrates FPGA prototyping methodology flow for ASIC IP.
Referring now to
A plurality of daughter cards 310, 312, 314 & 316 are communicatively coupled to the multi-ported memory controller 302 through advanced high-performance bus interfaces 318, 320, 322 & 324. For example, a motherboard may include daughter card (DC) slots which have 32-bit AHB interfaces, which support four AHB masters, four AHB slaves and four APB slaves. The daughter cards 310, 312, 314 & 316 may each include a mezzanine card 326, 328, 330 & 332 to provide an interface.
The advanced high-performance bus interfaces 318, 320, 322 and 324 are communicatively coupled over a common system bus 334, which may include an advanced high-performance bus, for communication between the daughter cards 310, 312, 314 & 316. A peripherals bus, such as an advanced peripheral bus (APB) 336, may also be provided to link peripherals to the daughter cards 310, 312, 314 and 316.
Although four daughter cards are shown, it should be apparent that a wide number of daughter cards may be utilized in conjunction with the present invention without departing from the spirit and scope thereof. Moreover, although an advanced high-performance bus (AHB) is described, a variety of bus architectures are contemplated by the present invention, such as DDR FPGA and the like.
Motherboards
A view of a motherboard 400 of an embodiment of the present invention is shown in
As described with regards to
Referring now to
An additional embodiment of a motherboard 600 of the present invention is shown in
Referring now to
The daughter card slots 702 are also communicatively coupled to the multi-layer bus matrix 704 utilizing the AHB master, as well as to a multi-ported controller FPGA 712. The multi-ported control FPGA 712 is coupled to two 32 bit DDR memory banks and a 32 bit SDRAM bank, plus a syncflash bank. An APB peripheral FPGA is also included, which is coupled to the multi-layer bus matrix 704, as well as the daughter card slots 702 through the APB slave.
In this embodiment, the motherboard 700 has full 64-bit support. For instance, the combination of master and expansion connector supports 64-bit master, and the AHB slave and APB connectors may be combined to support a 64-bit AHB slave, a second 64-bit AHB master, and the like. Additionally, the APB connector may be used as a second 32-bit AHB slave.
Further, by providing a multi-layer AHB, all masters may talk to all slaves. A variety of other changes may be made to the motherboard 700 without departing from the spirit and scope of the present invention. For instance, common AHB FPGAs may be replaced with high speed CPLDs, EBIU and APB FPGAs may be combined into one Virtex-II, DDR Dram may use standard DIMMS, common memory and multi-ported (non DDR) memory may be included on the daughter cards for maximum flexibility, and the like as contemplated by a person of ordinary skill in the art. An additional block diagram illustrating a multi-ported system is shown in
Daughter Cards
Implementing IP in a FPGA daughter card may be accomplished with a minimum of effort through use of the present invention. Daughter card connection may be made standard AHB master, slave and APB, which are identical to an ASIC. The IP hierarchy may be extracted from the AHB bus down. Additionally, an FPGA specific top level may be added for bus connections, such as I/O pads, clocks, and the like, which may be implemented as a library function. Further, FPGA specific I/O may be added as needed for mezzanine interface. Partitions design across multiple FPGAs through use of the present invention. AHB RTLs may be prototyped in FPGAs as shown in
Daughter cards of the present invention may support a variety of functionality as desired to enable rapid prototyping. For example, an ARM922 daughter card may be provided which leverages an ARM922 test chip and provided full hardware support for JTAG based debugging. The ARM922 daughter card may include an AHB master interface to the motherboard, and operate as a standalone daughter card. An ARM 946/966 daughter card may also be provided having similar functionality but leverages an ARM946/966 test chip.
A daughter card may also be configured as a general purpose FPGA daughter card. This daughter card may include a general purpose FPGA to provide a wide range of desired functionality. Preferably, the interconnect will support AHB masters, AHB slaves and APB slaves. Additionally, connectors may be provided to allow a mezzanine card to be attached to provide a physical interface for further customization. A ZSP daughter card may also be provided with an interconnection which will support AHB masters, AHB slaves and APB slaves and connectors to a mezzanine card to allow
Mezzanine cards may also be provided to enable physical level interfaces for daughter cards. For example, a telephony mezzanine card may be provided which contains TDM port to a voice codec and subscriber line interface circuits. The telephony mezzanine card may be utilized with the ZSP daughter card for an additional or other voice CODEC, echo cancellation, and other voice processing as contemplated by a person of ordinary skill in the art. The telephony card may also include a message processing unit (MPU) interface to control SLAC devices. Additionally, an Ethernet mezzanine card may also be provided to provide an Ethernet connection. The Ethernet mezzanine card may include 10/100 Ethernet ports and be used with general purpose FPGA daughter card as previously described. Use with the General Purpose FPGA daughter card may require Ethernet controller logic.
A motherboard of the present invention may support a variety of features. For example, the motherboard may include a power connector (2×25 pin 0.1 header) suitable for supporting +5, +3.3, +2.5, +1.8, +1.5, −12 and −5 V. The motherboard may also include a joint test action group (JTAG) connector (2×25 pin 0.1 header). The connector may support daisy chaining and for debugging JTAP signals, such as TDI, TDO, RTCK, TCK, TMS, nSRST, nTRST, DBGACK, and the like (DBGACK goes to APB FPGA to stop cntr, watchdog, and the like). The connector may support a 4-bit MB revision number; 2-bit slot ID; 8-bit jumper settings such as master only, slave only, and the like; FPGA present to inform reset circuitry of initialized device; FPGA done to inform reset circuitry that initialization is complete; and the like as contemplated by a person of ordinary skill in the art.
Communication
To achieve communication between devices utilizing the AHB, AHB master MUXs are provided. For instance, referring again to
An ApArbiter is located in APB FPGA. A critical path is provided by HCLK to HMAST out of APB FPGA across the motherboard to common AHB interface FPGAs, which is preferably slower than control signal delays. For RTL changes, the ApArbiter outputs unregistered HMAST. Common AHB Interface FPGAs register the compare of HMAST[3:2] to slot ID, and actually register the enable of the IOB. Thus, timing problems are eliminated.
A centralized decoder may be utilized in APB FPGA for HSEL generation. For example, the decoder may generate 24 HSELs. Additional embodiments contemplate one copy of decoder distributed to all motherboard FPGAs, thereby allowing syntheses to use what it needs. Further, the decoder may be register based, so there is no need to change RTL to remap the system.
The configuration of an APB bridge may be provided in an number of ways. For example, a main APB bridge may be provided in an APB FPGA. The bridge may generate 16 daughter card PSELs on peripherals on the FPGA. A unidirectional data bus is provided to the daughter card slots from the APB FPGA. A secondary bridge is provided in the common memory FPGA, which connects ApSdramCtrl to the AHB bus.
Connectors which may be utilized in embodiments of the present invention are shown in
Mapping an ASIC Utilizing the Rapid Prototyping System
Much of the delays and problems caused in bringing ASIC designs to market result from the difficulty in testing the design in a system environment early enough, and the need to “spin” silicon because of inadequate system tests. However, though use of the present invention, a development system is provided which allows a design to be prototyped in FPGA and system software integrated prior to tape out of the first silicon, increasing the probably that the first silicon meets the desired requirements.
For example, referring now to
To provide the processing for the prototype, three processor daughter cards 1020, 1022 & 1024 are utilized. Additional, a FPGA card is utilized to act as the Ethernet controller 1026. The cards 1020, 1022, 1024 & 1026 are communicatively coupled over a system bus, such as an advanced high performance bus (AHB) 1028 having an AHB arbiter 1030. A peripherals bus 132, such as an advanced peripherals bus, is provided for connecting the peripherals 1008. A bridge 134 links the system bus 1028 to the peripherals bus 1032. In this way, the system 1000 of the present invention may be utilized to prototype a design for an ASIC and thereby enable system software to be integrated prior to producing the design in silicon, thereby increasing the probability that the first silicon device produced will function as intended.
Thus, the present invention provides for a variety of advantages over the prior art. Concurrent multi-processing allows for prototyping multi-processor system such as dual ARM, ARM and ZSP, and the like, including support for multi-core debugging. Multi-ported memory environment allows prototyping of more than one master device, processor or bus master DMA type controller, accessing memory at the same time. AMBA bus connections matching the ASIC methodology flow allows a designer to take the RTL directly from an ASIC design, add a library file for FPGA I/O and synthesize directly into a FPGA. Processors and peripherals may be prototyped using either test silicon or FPGA. Common AHB bus allows prototyping of system where the peripherals and non-multi-ported memory on the motherboard are shared by any or all masters in the system. Additionally, a system may be made application specific by providing a needed subset of the features previously mentioned in the discussion.
It is believed that the system and method of the present invention and many of its attendant advantages will be understood by the forgoing description. It is also believed that it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages. The form herein before described being merely an explanatory embodiment thereof. It is the intention of the following claims to encompass and include such changes.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4656592 | Spaanenburg et al. | Apr 1987 | A |
| 4775942 | Ferreri et al. | Oct 1988 | A |
| 5036473 | Butts et al. | Jul 1991 | A |
| 5274765 | Le Gallo | Dec 1993 | A |
| 5339262 | Rostoker et al. | Aug 1994 | A |
| 5515514 | Dhuey et al. | May 1996 | A |
| 5604888 | Kiani-Shabestari et al. | Feb 1997 | A |
| 5804986 | Jones | Sep 1998 | A |
| 5818728 | Yoeli et al. | Oct 1998 | A |
| 5818729 | Wang et al. | Oct 1998 | A |
| 5887145 | Harari et al. | Mar 1999 | A |
| 6011730 | Sample et al. | Jan 2000 | A |
| 6138183 | Tien et al. | Oct 2000 | A |
| 6226756 | Mueller | May 2001 | B1 |
| 6230307 | Davis et al. | May 2001 | B1 |
| 6266724 | Harari et al. | Jul 2001 | B1 |
| 6289376 | Taylor et al. | Sep 2001 | B1 |
| 6321366 | Tseng et al. | Nov 2001 | B1 |
| 6347395 | Payne et al. | Feb 2002 | B1 |
| 6356109 | Furuta et al. | Mar 2002 | B1 |
| 6381662 | Harari et al. | Apr 2002 | B1 |
| 6389379 | Lin et al. | May 2002 | B1 |
| 6459136 | Amarilio et al. | Oct 2002 | B1 |
| 6496517 | Gehman et al. | Dec 2002 | B1 |
| 6571370 | Kim | May 2003 | B2 |
| 6621325 | Hart et al. | Sep 2003 | B2 |
| 6651225 | Lin et al. | Nov 2003 | B1 |
| 6785873 | Tseng | Aug 2004 | B1 |
| 6798784 | Dove et al. | Sep 2004 | B2 |
| 6842865 | Nee et al. | Jan 2005 | B2 |
| 6893268 | Harari et al. | May 2005 | B1 |
| 6898657 | Smith | May 2005 | B2 |
| 7129860 | Alvarez et al. | Oct 2006 | B2 |
| 7130942 | Gemelli et al. | Oct 2006 | B2 |
| 7137011 | Harari et al. | Nov 2006 | B1 |
| 20010056480 | Taylor et al. | Dec 2001 | A1 |
| 20020116168 | Kim | Aug 2002 | A1 |
| 20020131765 | DeKeyser et al. | Sep 2002 | A1 |
| 20030046478 | Pertry et al. | Mar 2003 | A1 |
| 20040015633 | Smith | Jan 2004 | A1 |
| 20040243386 | Stolowitz et al. | Dec 2004 | A1 |
| 20050031097 | Rabenko et al. | Feb 2005 | A1 |
| 20050055192 | Traut | Mar 2005 | A1 |
| 20050091029 | Traut | Apr 2005 | A1 |
| 20050102125 | Tseng | May 2005 | A1 |
| 20050182838 | Sheets et al. | Aug 2005 | A1 |
| 20050193091 | Taylor et al. | Sep 2005 | A1 |
| 20050204082 | Thomas et al. | Sep 2005 | A1 |
| 20060241921 | Willis | Oct 2006 | A1 |
| 20070016704 | Harari et al. | Jan 2007 | A1 |
| Number | Date | Country |
|---|---|---|
| 61166667 | Jul 1986 | JP |
| 2001134522 | May 2001 | JP |
| 01202397 | Jul 2001 | JP |
| 02202886 | Jul 2002 | JP |
| WO 8803679 | May 1988 | WO |
| WO 9525310 | Sep 1995 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20040044876 A1 | Mar 2004 | US |
