BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram illustrating a voltage-controlled oscillating device according to an embodiment of the present invention.
FIG. 2 is a timing diagram illustrating the operation of generating the oscillating signal of the voltage-controlled oscillating device in FIG. 1.
FIG. 3 is a diagram illustrating a phase lock loop that utilizing voltage-controlled oscillating device in FIG. 1.
DETAILED DESCRIPTION
Please refer to FIG. 1. FIG. 1 illustrates a voltage-controlled oscillating device 200 according to an embodiment of the present invention. The voltage-controlled oscillating device 200 comprises a regulating circuit 202, a biasing circuit 204, and an oscillator 206. When the voltage-controlled oscillating device 200 operates in a low supply voltage device and outputs an oscillating signal, the regulating circuit 202 provides a full range input control signal and generates a regulated voltage signal to voltage-controlled oscillating device 200 linearly. The biasing circuit 204 converts the regulated voltage signal into a current biased signal of the oscillator 206 to provide the power of the oscillator 206. Then, the oscillator 206 adjusts an oscillating frequency of an output oscillating signal Fosc according to the current biased signal that is provided by the biasing circuit 204. In this embodiment, the oscillator 206 is a current controlled oscillator (CCO).
In this embodiment, the biasing circuit 204 comprises a full range input amplifier 208. A prior art full range input amplifier 208 is a rail-to-rail output transconductance amplifier (rail-to-rail OTA), a first input terminal of the full range input amplifier 208 is coupled to a control voltage Vctrl, wherein the control voltage Vctrl has a full range input in order to provide a wider control range when operating in a low voltage supply apparatus (e.g., 0V to Vdd). Furthermore, the biasing circuit 204 further comprises a voltage adjusting circuit that comprises a plurality of P-type transistor M1, M2 and a resistor 210. The gate terminal of the P-type transistor M1 is coupled to the output terminal of the full range input amplifier 208, the drain terminal of the P-type transistor M1 is coupled to the second input terminal of the full range input amplifier 208, and the transistor 210 is coupled to the source terminal of the P-type transistor M1. Therefore, the voltage adjusting circuit is utilized to feedback a feedback voltage into the second input terminal of the full range input amplifier 208, and to adjust the feedback voltage according to an output signal at the output terminal of the full range input amplifier 208. Moreover, because the first input terminal and the second input terminal are coupled to the negative input terminal and the positive terminal of the full range input amplifier 208, respectively, therefore when the control voltage Vctrl increases, the voltage over transistor 210 also increases. Meanwhile, the voltage at the output terminal of the full range input amplifier 208 is decreased to turn on the P-type transistor M1 to provide the current that flows through the resistor 210. Accordingly, the current flow through the resistor 210 and the control voltage Vctrl have a linear relationship. In other words, if the resistance of the resistor 210 is R, then the current that flows through the resistor 210 is Vctrl/R. On the other hand, the P-type transistor M2 is utilized as a biasing circuit, the gate terminal coupled to the output terminal of the full range input amplifier 208, and the drain terminal coupled to the oscillator 206 to provide a current biasing signal I that required by the oscillator 206. The current biasing signal I that is generated by the biasing circuit (i.e., P-type transistor M2) is K*Vctrl/R because the size of the P-type transistor M2 is k times that of the P-type transistor M1, and because both consist of the same biasing condition. Accordingly, an output frequency and the input signal also have a linear relationship. Please note that, in this embodiment of the present invention, k=1.
The oscillator 206 is coupled to the biasing circuit 204 for generating a current biasing signal I according to the oscillating signal Fosc. In this embodiment of the present invention, the oscillator 206 comprises a latch circuit 222 and a single-to-differential circuit 226. The latch circuit 222 comprises two NOR gates, which include a first input terminal I1, a second input terminal I2, a first output terminal O1, and a second output terminal O2, wherein the second output terminal O2 is utilized to output the oscillating signal Fosc; the single-to-differential circuit 226 is utilized to convert the output signal at the first output terminal O1 of the latch circuit 222 into a first differential output signal V1p, and a second differential output signal V1n according to the current biasing signal I; and the first and the second differential output signals V1p, V1n are then feedback to the second input terminal I2 and the first input terminal I1.
Please refer to FIG. 1. FIG. 1 illustrates a single-to-differential circuit 226. The single-to-differential circuit 226 comprises a first transistor capacitor 218, in which the gate terminal is coupled to the output of a first inverter 212, and the drain and the source terminals are coupled to a ground; a second transistor capacitor 220, in which the gate terminal is coupled to the output of a second inverter 214; the first inverter 212 is coupled to the first output terminal O1 of the latch circuit 222, the first transistor capacitor 218, and the biasing circuit 204; the second inverter 214 is coupled to the second transistor capacitor 220, and the biasing circuit 204; a third inverter 216 is coupled between the first output terminal O1 and the second inverter 214. Accordingly, the configuration is capable of preventing the circuit from oscillating when in a common mode. Furthermore, the chip area will increase in size substantially if utilizing the analog semiconductor processing to implement a capacitor, but the chip area will decrease substantially in size if utilizing the N-type transistor capacitor to implement the capacitor. However, the capacitance will decrease tremendously right before enter to strong inversion (e.g., both Vgs and Vgd smaller that Vtn) mode whenever the N-type transistor capacitor is utilized, thus the nonlinear characteristic of the N-type transistor capacitor will affect the voltage-controlled oscillating device 200 to perform a nonlinear transform function of the control voltage that is below Vtn. Accordingly, this embodiment of the present invention utilizes a Native NMOS to implement the transistor capacitor of the voltage-controlled oscillating device 200. The Native NMOS can be implemented under the CMOS process, and without an extra optical mask and manufacturing step. Moreover, this embodiment of the present invention also can utilize a depleted NMOS to implement the transistor capacitor of the voltage-controlled oscillating device 200. The depleted NMOS is an NMOS that is implemented within a N-well, thus the equivalent Vth is approximated to (or smaller than) 0V. When the Native NMOS is utilized, the supply voltage will not affect the characteristic of the capacitor, and the capacitance will be almost fixed. Furthermore, the chip area that is utilized by the Native NMOS is as small as the chip area that is utilized by the depleted NMOS.
Accordingly, when the current biasing signal I is generated, if the output signal of the first output terminal O1 of the latch circuit 222 is a high level signal, the high level signal will pass through the first inverter 212 to discharge the first transistor capacitor 218; at the same time, the high level signal will pass through the second inverter 214 and the third inverter 216 to charge the second transistor capacitor 220. The lowering time of the voltage level at the second input terminal I2 is faster that the rising time of the voltage level at the first input terminal I1 that will consequently result the second output terminal O2 of the latch circuit 222 be lowered into a low level voltage because the discharging time of the present embodiment is designed to be far smaller that the charging time. After discharging for a while, when the voltage of the first input terminal I1 is rising to a high level voltage, the voltage of the first output terminal O1 of the latch circuit 222 will then be lowered into the low level voltage. Then, the single-to-differential circuit 226 executes a reversed charging and discharging operation; accordingly, the second output terminal O2 of the latch circuit 222 is generating an oscillating signal Fosc. Furthermore, when the capacitance of the first transistor capacitor 218 is equal to the capacitance of the second transistor capacitor 220, then the charging current is fixed at Vctrl/R. Accordingly, the charging time is also fixed and not varying with time and supply voltage. However, the discharging current is not limited, if the discharging current is designed to be much larger that the charging current, then the duty cycle of the oscillating signal Fosc will be approximated 50% according to the charging and discharging operation between the first and the second inverter 212, 214 as shown in FIG. 1. The operation of the generating oscillating signal Fosc by the oscillator 206 is shown in FIG. 2.
Furthermore, a third input terminal I3 can be coupled to the latch circuit 222 for receiving an enable signal EN; the third input terminal I3 is capable of instantly deactivating/activating the latch circuit 222 for controlling the output of the oscillating signal Fosc. When the enable signal EN is at a high level, the oscillator 206 outputs the oscillating signal Fosc, otherwise the oscillator 206 does not output the oscillating signal Fosc. Please refer to FIG. 1. In FIG. 1, the enable signal EN is first transmitted to an inverter 224, then coupled to an input terminal of a NOR gate; thus in this way to control the NOR gate is also capable of controlling the operation of the voltage-controlled oscillating device 200. The related timing diagram is shown in FIG. 2. In FIG. 2, the enable signal EN is at a low voltage level in T1 through T2, thus in the time interval between T1 and T2, the first differential output signal V1p and the second differential output signal V1n will sustain the voltage level of time T1 and not vary to the other voltage level. In other words, the oscillator 206 will not generate the oscillating signal. Please note that, the above mentioned deactivate/activate latch circuit 222 is not provided as a limitation to the configuration that is shown in FIG. 1 but only by way of example. Furthermore, to couple the enable signal EN to another NOR gate of latch circuit 222 is also included in the spirit of the present invention, and the latch circuit 222 can be implemented by two NAND gates or by two NOR gates. Accordingly, the voltage-controlled oscillating device 200 with the enable signal EN is capable of performing a clock and data recovery phase lock loop (CDR PLL).
Please refer to FIG. 3. FIG. 3 illustrates a diagram of embodiment of a phase lock loop 300 utilizing the voltage-controlled oscillating device 200 of the present invention. The phase lock loop 300 comprises a phase/frequency detector 302 for generating a group of adjusting signals UP, Down according to the frequency of a reference signal Fref and the frequency of a oscillating signal Fout; a charge pump circuit 304 for generating a control signal according to adjusting signals UP, Down; a loop filter 306 for performing a filtering of the control signal; voltage-controlled oscillating device 200 for generating oscillating signal Fout according to the filtered control signal. The voltage-controlled oscillating device 200 comprises a regulating circuit 202 for converting the control signal Vctrl into an output voltage Vo; a biasing circuit 204 for generating a control current I according to the output voltage Vo, wherein the control current I varies linearly according to the output voltage Vo; and an oscillator 206 for generating the oscillating signal Fout according to the control current I; and a divider 310 for dividing the frequency of the oscillating signal and feeding back the frequency of the oscillating signal as a feedback to a phase/frequency detector 302. Additionally, the regulating circuit 202 comprises a full range input amplifier 208 for generating the output voltage Vo according to the control signal Vctrl; and a feedback circuit comprises a transistor M1 coupled to an output terminal of the full range input amplifier 208 for determining the output voltage Vo. The oscillator 206 comprises a single-to-differential circuit 226 for generating a differential signal according to the control current I; and latch circuit 222 for generating the oscillating signal Fout according to the differential signal. Finally, the oscillating signal Fout is passed through a divider 310 to feedback into a phase/frequency detector 302 for performing a phase locking operation. Because the voltage-controlled oscillating device 200 of the phase lock loop 300 is an embodiment of the present invention, the detailed circuit and operation was described above, thus further description is omitted in this embodiment. Furthermore, the locking operation of the phase lock loop 300 are well known by those having average skill in this art, therefore the well known details are omitted in this embodiment for the sake of brevity.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Application
20070241823
