The present disclosure relates to power converting technology. More particularly, the present disclosure relates to a power converter and a converting method.
With development of technology, various power converters have been applied to various circuitry. A power converter has a control circuit for generating a pulse width modulation signal based on a feedback signal related to an output signal that the power converter outputs. The power converter also has a ramp generator circuit for generating a ramp signal, and the control circuit adjusts the duty of the pulse width modulation signal according to the ramp signal. In some related approaches, the ramp generator circuit is implemented by active elements and does not utilize the output signal to generate the ramp signal. Thus, the output impedance of the power converters in these related approaches is higher such that the transient response of the power converters is poor.
Some aspects of the present disclosure provide a power converter. The power converter includes a power stage circuit, a ramp generator circuit, and a control circuit. The power stage circuit is configured to generate an output signal according to an input signal and a control signal. The ramp generator circuit is configured to generate a ramp signal according to the control signal, the input signal, and the output signal. The control circuit is configured to generate the control signal according to the output signal, a reference signal, and the ramp signal.
Some aspects of the present disclosure provide a converting method. The converting method includes following operations: generating, by a power stage circuit, an output signal according to an input signal and a control signal; generating, by a ramp generator circuit, a ramp signal according to the control signal, the input signal, and the output signal; and generating, by a control circuit, the control signal according to the output signal, a reference signal, and the ramp signal.
The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
In the present disclosure, “connected” or “coupled” may refer to “electrically connected” or “electrically coupled.” “Connected” or “coupled” may also refer to operations or actions between two or more elements.
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The control circuit 130 is configured to generate a control signal CS, which is a pulse width modulation (PWM) signal. The power stage circuit 110 is configured to generate an output signal VO according to an input signal VIN and the control signal CS. As illustrated in
A first terminal of the switch MP is configured to receive the input signal VIN, a second terminal of the switch MP is coupled to the node Lk and a control terminal of the switch MP is configured to receive the control signal CS. A first terminal of the switch MN is coupled to a ground terminal GND, a second terminal of the switch MN is coupled to the node LX, and a control terminal of the switch MN is configured to receive the control signal CS. The control signal CS is used to control the switch MP and the switch MN to be turned on or turned off. For example, when the control signal CS has a first logic level (e.g., high logic level), the switch MP is turned off and the switch MN is turned on, and a voltage at the node LX is generated in response to the input signal VIN. When the control signal CS has a second logic level (e.g., low logic level), the switch MP is turned on and the switch MN is turned off, and the voltage at the node LX is generated in response to a ground voltage at the ground terminal GND.
The filter circuit 111 is coupled to the node LX and is configured to output the output signal VO. To be more specific, the filter circuit 111 includes an inductor LS, a resistor RLS, a capacitor CO, and a resistor RCO. A first terminal of the inductor LS is coupled to the node LX and a second terminal of the inductor LS is coupled to a first terminal of the resistor RLS. A second terminal of the resistor RLS is configured to output the output signal VO and is coupled to a first terminal of the capacitor CO. A second terminal of the capacitor CO is coupled to a first terminal of the resistor RLS, and a second terminal of the resistor RLS is coupled to the ground GND.
As described above, the control signal CS is used to control the switch MP and the switch MN to be turned on or turned off. In other words, a duty cycle of the control signal CS can determine turned-on time of the switch MP and turned-on time of the switch MN so as to output the output signal VO. The output signal VO is substantially equal to a product of the input signal VIN and the duty cycle (e.g., 30%) of the control signal CS.
The ramp generator circuit 120 is configured to generate a ramp signal VPSR according to the control signal CS, the input signal VIN, and the output signal VO.
The control circuit 130 is configured to generate the control signal CS according to the output signal VO, a reference signal VREF, and the ramp signal VPSR. As illustrated in
A first input terminal of the error amplifier circuit 131 is configured to receive the output signal VO, and a second input terminal of the error amplifier circuit 131 is configured to receive the reference signal VREF. The error amplifier circuit 131 generates an error amplifying signal VO according to the output signal VO and the reference signal VREF.
A first input terminal of the comparator circuit 132 is configured to receive the error amplifying signal VO, and a second input terminal of the comparator circuit 132 is configured to receive the ramp signal VPSR. The comparator circuit 132 compares the error amplifying signal VO with the ramp signal VPSR to generate a comparison signal VCOMP.
The control signal generator circuit 133 generates the control signal CS according to the comparison signal VCOMP. To be more specific, the control signal generator circuit 133 includes an AND gate 1331, an on-time controller 1332, an off-time controller 1333, a delay circuit 1334, and an OR gate 1335.
A first input terminal of the AND gate 1331 is configured to receive the comparison signal VCOMP, and a second input terminal of the AND gate 1331 is configured to receive an off-time control signal VTOFF. The AND gate 1331 performs an AND operation on the comparison signal VCOMP and the off-time control signal VTOFF to generate a logic signal LS.
The on-time controller 1332 is configured to receive the logic signal LS and generate an on-time control signal VTON according to the logic signal LS. The on-time controller 1332 is triggered by rising edges and can determine a width of a logic value 1.
In addition, the off-time controller 1333 is configured to receive the on-time control signal VTON and generate an off-time control signal VTOFF according to the on-time control signal VTON. The off-time controller 1333 is triggered by falling edges and can determine a width of a logic value 0.
The delay circuit 1334 is configured to receive the comparison signal VCOMP and delay the comparison signal VCOMP for a delay time to generate a delay signal VCOMP_B. The delay circuit 1334 can prevent noise.
A first input terminal of the OR gate 1335 is configured to receive the delay signal VCOMP_B, and a second input terminal of the OR gate 1335 is configured to receive the on-time control signal VTON. The OR gate 1335 performs an OR operation on the delay signal VCOMP_B and the on-time control signal VTON to generate the control signal CS.
The implementations and operations of the ramp generator circuit 120 will be described in following paragraphs.
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In some conventional approaches, ramp generator circuits are implemented by circuits of active elements and do not utilize the output signal to generate the ramp signal. Thus, the output impedance of the power converters in these related approaches is higher such that the transient response of the power converters is poor.
Compared to the aforementioned conventional approaches, the ramp generator circuit 120 in the present disclosure is implemented by passive impedance circuit (without amplifying operation, without voltage-voltage conversion operation, without voltage-current conversion operation) and utilizes the output signal VO to generate the ramp signal VPSR. Thus, the power converter 100 has a better transient response and low power consumption. Then, the control circuit 130 can detect the output signal VO to generate the error amplifying signal VC, and then extend on-time of the logic signal LS to generate the control signal CS so as to control the switches MP and MN.
Reference is made to
In operation S810, the power stage circuit 110 generates the output signal VO according to the input signal VIN and the control signal CS. As illustrated in
In operation S820, the ramp generator circuit 120 generates the ramp signal VPSR according to the control signal CS, the input signal VIN, and the output signal VO. The ramp generator circuit 120 can be implemented by the ramp generator circuit 120A in
In operation S830, the control circuit 130 generates the control signal CS according to the output signal VO, the reference signal VREF, and the ramp signal VPSR. As illustrated in
Based on the descriptions above, the power converter in the present disclosure has a better transient response and low power consumption.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
This application claims priority to U.S. Provisional Application Ser. No. 63/152,323, filed Feb. 22, 2021, which is herein incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
7245113 | Chen et al. | Jul 2007 | B2 |
7751471 | Chu et al. | Jul 2010 | B2 |
9601997 | Yan et al. | Mar 2017 | B2 |
10097079 | Cheng et al. | Oct 2018 | B1 |
10833661 | Archibald | Nov 2020 | B1 |
20100007318 | Faerber | Jan 2010 | A1 |
20140292300 | Yan et al. | Oct 2014 | A1 |
20150137776 | Thomas et al. | May 2015 | A1 |
20190260284 | Inc | Aug 2019 | A1 |
20200228018 | Wiktor et al. | Jul 2020 | A1 |
20210045212 | Lai et al. | Feb 2021 | A1 |
Number | Date | Country |
---|---|---|
0709948 | May 1996 | EP |
2985900 | Feb 2016 | EP |
201214935 | Apr 2012 | TW |
201328141 | Jul 2013 | TW |
I547083 | Aug 2016 | TW |
201909536 | Mar 2019 | TW |
202030959 | Aug 2020 | TW |
Number | Date | Country | |
---|---|---|---|
20220271661 A1 | Aug 2022 | US |
Number | Date | Country | |
---|---|---|---|
63152323 | Feb 2021 | US |