Claims
- 1. A circuit configuration, comprising:
an integrated circuit; a random number generator configuration provided on said integrated circuit; said random number generator configuration including a first clock generator circuit for generating a first signal having one of a first frequency and a first frequency range with a first mean value, and said random number generator configuration including a second clock generator circuit for generating a second signal having one of a second frequency and a second frequency range with a second mean value, said first and second clock generator circuits generating said first and second signals such that one of said second frequency and said second mean value is smaller than one of said first frequency and said first mean value; said first clock generator circuit having a first voltage supply, said second clock generator circuit having a second voltage supply; said random number generator configuration including a generator configured to sample said first signal with said second signal and configured to generate at least one random number in dependence of a sampling result; and said random number generator configuration having at least one isolation measure selected from the group consisting of said first and second generator circuits being spaced apart from one another by a maximum spacing distance on said integrated circuit, said first and second voltage supplies being isolated from one another, and at least one guard ring-being placed around each of said first and second clock generator circuits.
- 2. The circuit configuration according to claim 1, wherein:
said first and second clock generator circuits are spaced apart from one another by the maximum spacing distance on said integrated circuit; said first and second voltage supplies are isolated from one another; and at least one guard ring is placed around each of said first and second clock generator circuits.
- 3. The circuit configuration according to claim 1, wherein:
said integrated circuit has diagonally opposite corner regions; and said first and second clock generator circuits are respectively disposed in said diagonally opposite corner regions of said integrated circuit.
- 4. The circuit configuration according to claim 1, including at least one RC element, said first and second voltage supplies being isolated by said at least one RC element.
- 5. The circuit configuration according to claim 1, including two RC elements, each of said first and second voltage supplies being isolated by a respective one of said RC elements.
- 6. The circuit configuration according to claim 1, including an RC element for isolating said first clock generator circuit, said RC element having a decoupling frequency corresponding to one of said second frequency and said second mean value of said second frequency range of said second signal of said second clock generator circuit.
- 7. The circuit configuration according to claim 1, including an RC element for isolating said second clock generator circuit, said RC element having a decoupling frequency corresponding to one of said first frequency and said first mean value of said first frequency range of said first signal of said first clock generator circuit.
- 8. The circuit configuration according to claim 1, including at least one voltage regulator, said first and second voltage supplies being isolated by said at least one voltage regulator.
- 9. The circuit-configuration according to claim 1, wherein said first clock generator circuit generates a signal with a variable frequency as said first signal.
- 10. The circuit configuration according to claim 1, wherein said second clock generator circuit generates a signal with a variable frequency as said second signal.
- 11. The circuit configuration according to claim 1, wherein said first and second clock generator circuits generate said first and second signals such that said second signal has a frequency at least ten times lower than said first signal.
- 12. The circuit configuration according to claim 11, wherein said first and second clock generator circuits generate said first and second signals such that said second signal has a frequency at least one hundred times lower than said first signal.
- 13. The circuit configuration according to claim 1, wherein said generator generates a sequence of random numbers.
- 14. The circuit configuration according to claim 1, wherein said generator includes an equalizing circuit for compensating a non-constant power.
- 15. The circuit configuration according to claim 1, wherein said generator includes an equalizing circuit for providing a weighting during a random number generation.
- 16. The circuit configuration according to claim 1, wherein said generator includes an equalizing circuit with a linear feedback shift register.
- 17. The circuit configuration according to claim 1, wherein:
at least one of said first and second clock generator circuits has at least one voltage-coupled oscillator and a further oscillator; and said at least one voltage-coupled oscillator has a control input, said further oscillator has a signal output connected to said control input of said at least one voltage-coupled oscillator.
- 18. The circuit configuration according to claim 17, wherein said further oscillator is a voltage-coupled oscillator having a control input supplied with a constant voltage.
- 19. The circuit configuration according to claim 17, wherein at least one of said first and second clock generator circuits has a plurality of voltage-coupled oscillators connected in series to one another such that each of said voltage-coupled oscillators, except for a last one of said voltage-coupled oscillators, has a control output connected to a control input of a respective next one of said voltage-coupled oscillators.
Priority Claims (1)
Number |
Date |
Country |
Kind |
100 03 472.1 |
Jan 2000 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of copending International Application No. PCT/DE01/00111, filed Jan. 12, 2001, which designated the United States and was not published in English.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/DE01/00111 |
Jan 2001 |
US |
Child |
10208468 |
Jul 2002 |
US |