BRIEF DESCRIPTION OF THE FIGURES OF THE DRAWINGS
FIG. 1 is a schematic diagram of a prior art current mirror.
FIG. 2 is a schematic diagram of a current mirror employing a body bias generator.
FIG. 3 is a schematic diagram a body bias generator.
FIG. 4 is a flow diagram of a design process used in semiconductor design, manufacturing, and/or test of the embodiments disclosed herein.
DETAILED DESCRIPTION OF THE INVENTION
A preferred embodiment of the invention is now described in detail. Referring to the drawings, like numbers indicate like parts throughout the views. As used in the description herein and throughout the claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise: the meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.”
As shown in FIG. 2, one embodiment of a current mirror circuit 100 employs a reference transistor 12 to draw a reference current (iref) from a current source 10. There is a voltage drop (vref) across the current source 10. The reference voltage (nbias) at the gate of the reference transistor 12 is used to bias the gates of subsequent transistors 14 (only one of which is shown in this example for the sake of clarity) that then draw a current corresponding to the current flowing through the reference transistor 12. Each subsequent transistor 14 regulates the current lowing through a circuit load 16 so as to correspond to the reference current (iref).
A ratioed body bias feedback unit 110 is responsive to the reference voltage (nbias) and generates a body bias voltage (bbias) that is coupled to the body of the reference transistor 12 and the body of each mirror transistor 14. The ratioed body bias feedback unit 110 is configured to adjust the body bias voltage in relationship to the common voltage (e.g. Vgg in the example shown) so that the reference transistor 12 and the mirror transistor 14 each have a threshold voltage within a predefined range. The ratioed body bias feedback unit 110 senses the reference voltage (nbias) and generates a body bias voltage (bbias) that biases the reference transistor 12 body and the mirror transistor 14 body so as to maintain the threshold voltage of the reference transistor 12 and each mirror transistor 14 within a predetermined range.
As shown in FIG. 3, one embodiment of the ratioed body bias feedback unit 110 electrically couples the gate bias input voltage (nbias) at the source of the reference transistor 12 (shown in FIG. 2) to the gate of a first n-type transistor 114. The first n-type transistor 114 has a drain coupled to a common voltage (Vgg), a source, a body, and a gate that is coupled to the gate of the reference transistor 12 (shown in FIG. 2). A first p-type transistor 112 has a source coupled to a voltage Supply (Vdd), a drain coupled to the source of the first n-type transistor 114, a body coupled to the voltage supply (Vdd) and a gate coupled to the source of the first n-type transistor 114. A second n-type transistor 118 has a drain coupled to the common voltage (Vgg), a source coupled to the body of the first n-type transistor 114, a body coupled to the body of the first n-type transistor 114 and a gate coupled to the body of the first n-type transistor 114. A second p-type transistor 116 has a drain coupled to the body of the first n-type transistor 114, a source coupled to the voltage supply (Vdd), a body coupled to the voltage supply (Vdd) and a gate coupled to the source of the first n-type transistor 114.
In the embodiment shown, the first p-type transistor 112 and the first n-type transistor 114 each have a size selected so that the first n-type transistor 114 draws a current (Iref/2) that is a first fraction (one-half in the embodiment shown) of the reference current (Iref in FIG. 2). The second p-type transistor 116 and the second n-type transistor 118 each have a size so that the second n-type transistor 118 draws a current (Iref/8) that is a second fraction (one-eighth in the embodiment shown), less than the first fraction, of the reference current. Because the current drawn by the second n-type transistor 118 is a fraction of the current drawn by the first n-type transistor 114, the ratioed body bias feedback unit 110 is inherently stable and the body bias voltage (bbias) always closes on the reference voltage (nbias). It should be noted that the relative proportions for the fractional currents given for (Iref/2) and (Iref/8) are exemplary only: other proportions could be used and still achieve workable results—so long as the second n-type transistor 118 is configured to draw a current that is a fraction of the current drawn by the first n-type transistor 114, the body bias feedback unit 110 will be a stable feedback system.
FIG. 4 shows a block diagram of an example design flow 300. Design flow 300 may vary depending on the type of IC being designed. For example, a design flow 300 for building an application specific IC (ASIC) may differ from a design flow 300 for designing a standard component. Design structure 320 is preferably an input to a design process 310 and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure 320 comprises circuit 100 (shown in FIG. 2) in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure 320 may be contained on one or more machine readable medium. For example, design structure 320 may be a text file or a graphical representation of circuit 100. Design process 310 preferably synthesizes (or translates) circuit 100 into a netlist 380, where netlist 380 is, for example, a list of wires, transistors, logic gates, control circuits, J/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist 380 is resynthesized one or more times depending on design specifications and parameters for the circuit.
Design process 310 may include using a variety of inputs; for example, inputs from library elements 330 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 340, characterization data 350, verification data 360, design rules 370, and test data files 385 (which may include test patterns and other testing information). Design process 310 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 310 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.
Design process 310 preferably translates an embodiment of the invention as shown in FIG. 2, along with any additional integrated circuit design or data (if applicable), into a second design structure 390. Design structure 390 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g., information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). Design structure 390 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown in FIG. 2. Design structure 390 may then proceed to a stage 395 where, for example, design structure 390: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
The above described embodiments, while including the preferred embodiment and the best mode of the invention known to the inventor at the time of filing, are given as illustrative examples only. It will be readily appreciated that many deviations may be made from the specific embodiments disclosed in this specification without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be determined by the claims below rather than being limited to the specifically described embodiments above.
Patent Application
20080072181
