This invention relates generally to the field of Semiconductor Integrated Circuit design, and more specifically to a design implementation of Rational Ratio Multiplier (RRM).
As Semiconductor Integrated Circuits become more complex and the implementation of complex SoCs (with SoC standing for System On a Chip) become widely used, there are many different blocks and interfaces inside the chip which require different and accurate clock frequencies.
Using a dedicated clock source such as crystal or PLL per each required clock frequency isn't optimal for both power and area of the silicon, thus there is a need to use one fast frequency clock source and to have a clock divider which can divide the fast clock source frequency to any required sub-frequency with good accuracy. In order to get to an accurate clock frequency, this divider needs to make a rational divide and for this there is a need to use a Rational Ratio Multiplier (RRM) which can give an accurate division and also a good duty cycle such that any logic which relies also on the falling edge of the clock can still operate.
This invention shows an optimized implementation of an RRM with close to 50% duty cycle for giving different rational ratios of N/D in which D>N.
Standard 1/D Divider Implementation—
This simple divider will divide the clock by the 1/D ratio with a duty cycle of 50% when D is even, and with one input-clock cycle width difference when D is odd. The divider uses a counter which counts from 1 to D (box 101 in
1/D Divider Implementation with 50% Duty Cycle—
This divider will divide the clock by the 1/D ratio with a duty cycle of 50% even when the D is odd by working on both rising and falling edges of the input clock. The divider uses a counter which counts from 1 to D (box 201 in
Because the two T-FFs are working one on the rising edge of the input clock and the other on the falling edge of the input clock, we get a 50% duty cycle even when D is odd and not like the 1/D implementation in
The disadvantage of the 1/D divider is that it can't give an accurate frequency on the output as it can support only division by D of the input clock frequency and not by N/D as the RRM implementation does.
RRM Implementation Using Clock Qualifier Approach—
This RRM implementation creates a qualified clock pulse of the input clock at the multiplication ratio of N/D. The high pulse width of this RRM remains always one cycle of the input clock and if any logic in the design is working with the falling edge of the output clock it will be required to meet the timing constraints of the input clock which is faster than the timing constraint of the output clock.
The RRM is programmed by receiving the value of N (box 300 in
Whenever the adder result is greater than D, the clock qualifier (box 308 in
To get an RRM which can work on any fractional ratio and give close to 50% duty cycle, a new implementation is proposed which performs this accurate clock multiplication.
This invention may be used by any system which requires an accurate clock multiplication using a rational fraction ratio and requires an output clock with close to 50% duty cycle so any negative edge logic which uses this clock can work with timing constraint of the output clock.
This invention has been described as including various operations. Many of the processes are described in their most basic form, but operations can be added to or deleted from any of the processes without departing from the scope of the invention.
RRM Implementation with Optimized Duty Cycle—
The RRM implementation under this invention generates an output clock with cycle time which is the multiplication of the input clock by the fraction rational ratio of N/D while D>N.
The duty cycle of the resulted output clock is close to 50% with a difference of only one half a cycle of the input-clock between the high period and the low period of output clock.
The implementation under this invention is programmed by receiving the value of N (box 400 in
In addition to the above, this invention includes a counter which counts from 1 to the sum of low period+high period (box 407 in
Connected to this counter are 4 T-FF's which 2 of them are sampling on the rising edge of input clock and the other two on the falling edge of input clock. These FF's are toggling when the counter equals to the following values:
When N isn't equal to 1 (this means that the implementation isn't a 1/D implementation) then the output clock is generated by a XOR (box 414 in
When N is equal to 1 (this means that the implementation is a 1/D implementation), the output clock is generated either by a XOR of the first T-FF with the fourth T-FF (box 416 in
The last multiplexer on the output (box 418 in
Number | Name | Date | Kind |
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6956923 | Younis | Oct 2005 | B1 |
8497708 | Mukherjee | Jul 2013 | B2 |
Number | Date | Country | |
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20230216506 A1 | Jul 2023 | US |