Claims
- 1. A test system for system on chips (SOC), wherein said SOC has a plurality of cores such that at least one of said plurality of cores is adapted to use a test protocol independent of a communication fabric used in the SOC.
- 2. The test system of claim 1, wherein one of said plurality of cores is adapted to use multiple test schemes.
- 3. The test system of claim 1, wherein a first one of said plurality of cores and a second one of said plurality of cores are from different vendors.
- 4. The test system of claim 3, wherein the system is adapted to use a uniform SOC-level test strategy for said plurality of cores.
- 5. The test system of claim 1, wherein a first one of said plurality of cores is adapted to use a first test scheme and a second one of said plurality of cores is adapted to use a second test scheme different from said first test scheme.
- 6. The test system of claim 1, wherein no delay is added to paths in the SOC.
- 7. The test system of claim 1, wherein test application time of a first one of said plurality of cores overlap a test application time of a second one of said plurality of cores.
- 8. A system-on-chip (SOC)with an embedded test protocol architecture, said SOC comprising:
at least one embedded core; a communication fabric that connects said at least one embedded core; at least one test server; and at least one test client connected to said at least one embedded core and connected to the communication fabric.
- 9. The SOC of claim 8, wherein said at least one embedded core connects to the communication fabric using bus interface logic.
- 10. The SOC of claim 8, wherein said test server is implemented as an embedded core.
- 11. The SOC of claim 8, wherein said test server is implemented on an on-chip processor core.
- 12. The SOC of claim 9, wherein the bus interface logic connects only to inputs and outputs of said at least one embedded core.
- 13. The SOC of claim 8, wherein said test client is connected only to test ports of the embedded core.
- 14. The SOC of claim 13, wherein said test client delivers test data to the embedded core by using the test ports.
- 15. The SOC of claim 8, wherein the communication fabric is a bus.
- 16. The SOC of claim 15 wherein the test server operates as a sole bus master.
- 17. The SOC of claim 8 wherein said at least one test server and said at least one test client are adapted to exchange information using a fixed-format packet.
- 18. The SOC of claim 17, wherein the packet is variable sized.
- 19. The SOC of claim 17, wherein the SOC is adapted to transmit the packet using multiple bus transactions.
- 20. The SOC of claim 17, wherein the packet comprises a header and a payload.
- 21. The SOC of claim 20, wherein the test client treats all data received after a header as payload until it receives another header.
- 22. A test client for use with a system-on-chip (SOC) with an embedded test protocol, said client comprising:
a bust interface block that generates communication signals required to plug the test client into a communication fabric of the SOC; a core interface block that converts test data into serial data streams; and a controller block that interprets received test packets.
- 22. The test client of claim 21, wherein the test core interface block converts responses from embedded cores of the SOC into packets.
- 23. The test client of claim 22 wherein the controller block further comprises a decoder for interpreting received test packets and a finite state machine that provides necessary signals to control the core interface block and the bus interface block.
- 24. A test system for a circuit board, wherein said circuit board has a plurality of cores such that at least one of said plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board.
- 25. The test system of claim 24, wherein one of said plurality of cores is adapted to use multiple test schemes.
- 26. The test system of claim 24, wherein said first core and second core are from different vendors.
- 27. The test system of claim 24, wherein the system is adapted to use a uniform circuit board-level test strategy for said plurality of cores.
- 28. The test system of claim 24, wherein a first one of said plurality of cores is adapted to use a first test scheme and a second one of said plurality of cores is adapted to use a second test scheme different from said first test scheme.
- 29. The test system of claim 24, wherein no delay is added to paths in the SOC.
- 30. The test system of claim 24, wherein test application time of a first one of said plurality of cores overlap a test application time of a second one of said plurality of cores.
Related Applications
[0001] This Application claims priority from co-pending U.S. Provisional Application Serial No. [Sughrue Mion, PLLC, Attorney Docket No. P8329, inventors Wang, Chakradhar and Balakrishnan,] filed Mar. 1, 2002, which is incorporated in its entirety by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60361057 |
Mar 2002 |
US |