Claims
- 1. A system for returning data, comprising:
a storage array operable to store data received from at least one data source; a bypass circuit communicatively coupled with said storage array and operable to simultaneously stage data received from said at least one data source; and a read data storage (RDS) controller communicatively coupled with said storage array and said bypass circuit and operable to select a data return path of minimum latency from a plurality of data return paths for returning data selected from one of said storage array and said bypass circuit, based at least in part on at least one tag associated with each of said at least one data source, to a requesting device.
- 2. The system of claim 1, wherein at least one tag relates to data requested by said requesting device and comprises an address and a critical word received from a Bus Interface Block (BIB).
- 3. The system of claim 1, wherein at least one tag is associated with data received from said at least one data source and comprises a memory data tag signal associated with one of said at least one data source and a controller critical word.
- 4. The system of claim 1, further comprising a critical word multiplexer operable to receive said data from said at least one data source and format said data into a format requested by said requesting device.
- 5. The system of claim 4, wherein said critical word multiplexer is operable to provide formatted data to at least one of said storage array and said bypass circuit.
- 6. The system of claim 1, wherein said storage array comprises a plurality of storage cells of equal width.
- 7. The system of claim 1, wherein said bypass circuit comprises a plurality of staging areas, each of said plurality of staging areas operable to stage data prior to the data being provided to said requesting device.
- 8. The system of claim 1, wherein said RDS controller comprises at least one finite state machine operable to determine based at least in part on said at least one tag whether to provide data to said requesting device from said storage array or from said bypass circuit.
- 9. The system of claim 1, wherein said RDS controller comprises at least one finite state machine operable to write data from said at least one data source into a correct location of said storage array.
- 10. The system of claim 9, wherein said at least one finite state machine is further operable to update a data valid vector of said RDS controller upon completion of a write operation to facilitate determination of said data return path of said plurality of data return paths.
- 11. The system of claim 1, wherein said RDS controller comprises at least one finite state machine operable to determine a location in said storage array from which to return data to said requesting device.
- 12. The system of claim 11, wherein said at least one finite state machine is further operable to determine said data return path of minimum latency.
- 13. The system of claim 1, wherein said RDS controller comprises a finite state machine operable to notify another finite state machine to advance a data word in a current cache line to said requesting device.
- 14. The system of claim 1, wherein said bypass circuit comprises at least one staging register operable to receive data from a critical word multiplexer.
- 15. The system of claim 1, wherein said bypass circuit comprises at least one staging register operable to receive data from said storage array.
- 16. The system of claim 1, wherein said at least one data source comprises a memory module.
- 17. A method for returning data, comprising:
receiving a request for data from a requesting device; receiving data from at least one data source; storing said received data in a storage array; simultaneously staging said received data in a bypass circuit; selecting a data return path of minimum latency from a plurality of data return paths for returning said data; and providing data from one of said storage array and said bypass circuit to said requesting device via said selected data return path of minimum latency based at least in part on at least one tag associated with each of said at least one data source.
- 18. The method of claim 17, further comprising associating at least one tag with data requested by said requesting device, said at least one tag comprising an address and a critical word received from a Bus Interface Block (BIB).
- 19. The method of claim 17, further comprising associating at least one tag with data received from said at least one data source, said at least one tag comprising a memory data tag signal associated with one of said at least one data source and a controller critical word.
- 20. The method of claim 17, further comprising formatting said data into a format requested by said requesting device prior to said providing step.
- 21. The method of claim 17, further comprising determining based at least in part on said at least one tag whether to provide data to said requesting device from said storage array or from said bypass circuit.
- 22. The method of claim 17, further comprising writing data from said at least one data source into a correct location of said storage array.
- 23. The method of claim 17, further comprising updating a data valid vector upon completion of a write operation to facilitate selection of said data return path of said plurality of data return paths.
- 24. The method of claim 17, further comprising determining a location in said storage array from which to return data to said requesting device.
- 25. A system for returning data, comprising:
means for storing said data received from at least one data source; means for simultaneously staging said data received from said at least one data source; means for selecting a data return path of minimum latency from a plurality of data return paths for returning said data; and means for providing data to a requesting device from one of said means for storing and said means for simultaneously staging, via said selected data return path of minimum latency based at least in part on at least one tag associated with each of said at least one data source.
- 26. The system of claim 25, further comprising means for receiving a request for said data.
- 27. The system of claim 25, further comprising means for receiving data from at least one data source.
- 28. The system of claim 25, wherein said means for storing comprises a storage array.
- 29. The system of claim 25, wherein said means for simultaneously staging comprises a bypass circuit.
- 30. The system of claim 25, further comprising means for associating at least one tag with data requested by said requesting device, said at least one tag comprising an address and a critical word received from a Bus Interface Block (BIB).
- 31. The system of claim 25, further comprising means for associating at least one tag with data received from said at least one data source, said at least one tag comprising a memory data tag signal associated with one of said at least one data source and a controller critical word.
RELATED APPLICATIONS
[0001] This patent application claims the benefit of Provisional Patent Application Serial No. 60/360,346, entitled Synchronizing Controller and Bypass Mechanism for Read Data Return Path, filed on Feb. 27, 2002, the disclosure of which is incorporated herein by reference. This patent application is related to co-pending U.S. patent application Ser. No. 09/827,766, entitled “Memory Controller with Support for Memory Modules Comprised of Non-Homogeneous Data Width RAM Devices,” filed Apr. 7, 2001, co-pending U.S. patent application, Ser. No. 10/189,839, entitled “System and Method for Multi-Modal Memory Controller System Operation,” filed Jul. 5, 2002, and co-pending U.S. patent application, Ser. No. 10/189,825, entitled “Method and System for Optimizing Pre-Fetch Memory Transactions,” filed Jul. 5, 2002, the disclosures of which are incorporated herein by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60360346 |
Feb 2002 |
US |