Reading analog memory cells using built-in multi-threshold commands

Abstract

A method for data storage includes storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values. The memory has at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number. After storing the data, the first data bits are read from the memory cells by executing at least the second built-in command.

Description

FIELD OF THE INVENTION

The present invention relates generally to memory devices, and particularly to methods and systems for retrieving data from multi-level analog memory cells.

BACKGROUND OF THE INVENTION

Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible storage values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal storage value that corresponds to the desired bit or bits.

Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.

Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.

Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24^th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.

Analog memory cells are commonly read by comparing their storage values to one or more read thresholds. Some known methods and systems read analog memory cells using multiple read thresholds. For example, PCT International Publication WO 2007/132457, whose disclosure is incorporated herein by reference, describes a method for operating a memory device. The method includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells of the memory device. Second analog values are then read from the respective memory cells. A distortion present in the second analog values is estimated, and error correction metrics are computed responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data. In some embodiments, the error correction metrics are computed by combining multiple instances of the second storage values, which are obtained by using respective different sets of read thresholds.

PCT International Publication WO 2008/053472, whose disclosure is incorporated herein by reference, describes a method for operating a memory. The method includes storing data, which is encoded with an ECC, in analog memory cells of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values.

The two PCT Publications cited above are assigned to the assignee of the present patent application and were published after the priority date of the present patent application.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a method for data storage, including:

storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; and

after storing the data, reading the first data bits from the memory cells by executing at least the second built-in command.

In some embodiments, reading the first data bits by executing at least the second built-in command includes reading multiple instances of the first data bits using the respective second thresholds. In an embodiment, the multiple instances of the first data bits are processed so as to adjust the first thresholds. Additionally or alternatively, the multiple instances of the first data bits are processed so as to cancel interference in the analog memory cells. Further additionally or alternatively, storing the data includes encoding the data with an Error Correction Code (ECC), and the method includes processing the multiple instances of the first data bits so as to compute soft decoding metrics for decoding the ECC.

In a disclosed embodiment, reading the first data bits by executing at least the second built-in command includes making an attempt to read the first data bits using the first built-in command, and reverting to read the first data bits using the second built-in command responsively to a failure of the attempt.

In another embodiment, each of the analog memory cells further stores a third data bit, the memory has a third built-in command for reading the third data bits of the memory cells by comparing the storage values of the memory cells to a third number of third thresholds, such that the third number is larger than the second number, and reading the first data bits includes executing both the second and the third built-in commands.

In yet another embodiment, storing the data includes writing to the memory cells nominal storage values selected from a group of possible nominal storage values corresponding to the respective programming levels, and executing at least the second built-in command includes positioning the second thresholds between a pair of the nominal storage values that are adjacent to one another in the group of the possible nominal storage values. In still another embodiment, the storage values of the memory cells that assume a given programming level are distributed over a range, and executing at least the second built-in command includes positioning at least one of the second thresholds within the range. In an embodiment, the second built-in command reads the second data bits independently of the first data bits.

There is additionally provided, in accordance with an embodiment of the present invention, a method for data storage, including:

storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to one or more first thresholds, and a second built-in command for reading the second data bits of the memory cells independently of the first data bits by comparing the storage values of the memory cells to a plurality of second thresholds; and

after storing the data, reading the first data bits from the memory cells by executing at least the second built-in command.

There is also provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

an interface, which is operative to communicate with a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; and

a processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command.

There is further provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

a memory including multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; and

a processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command.

There is additionally provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

an interface, which is operative to communicate with a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to one or more first thresholds, and a second built-in command for reading the second data bits of the memory cells independently of the first data bits by comparing the storage values of the memory cells to a plurality of second thresholds; and

a processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command.

There is also provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

a memory including multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to one or more first thresholds, and a second built-in command for reading the second data bits of the memory cells independently of the first data bits by comparing the storage values of the memory cells to a plurality of second thresholds; and

a processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command.

The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;

FIG. 2 is a graph showing storage value distributions and read thresholds in a group of multi-level analog memory cells, in accordance with an embodiment of the present invention;

FIG. 3 is a graph showing read thresholds used for reading data from multi-level analog memory cells, in accordance with an embodiment of the present invention;

FIG. 4 is a flow chart that schematically illustrates a method for reading data from multi-level analog memory cells, in accordance with an embodiment of the present invention;

FIG. 5 is a graph showing storage value distributions and read thresholds in a group of multi-level analog memory cells, in accordance with another embodiment of the present invention;

FIG. 6 is a flow chart that schematically illustrates a method for reading data from multi-level analog memory cells, in accordance with an embodiment of the present invention; and

FIGS. 7-9 are graphs showing storage value distributions and read thresholds in a group of multi-level analog memory cells, in accordance with alternative embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Overview

In many MLC device configurations, different bits are read from the memory cells using respective, different sets of read thresholds. For example, in an eight-level MLC configuration, each memory cell stores three bits, which are referred to as a Least Significant Bit (LSB), a Central Significance Bit (CSB) and a Most Significant Bit (MSB). In a common reading scheme, the LSB is read using a single threshold, the CSB is read using a set of two thresholds, and the MSB is read using a different set that includes four thresholds.

Some MLC devices support composite built-in read commands for reading a certain bit from a group of memory cells. For example, in the 3 bits/cell configuration described above, the memory device may support three built-in commands (e.g., “read the LSBs from the group of cells X,” “read the CSBs from the group of cells X,” and “read the MSBs from the group of cells X,”). Typically, the threshold values to be used by the memory device are specified in the command. In response to receiving one of these commands, the memory device automatically sets the appropriate read thresholds for reading the requested bit, performs the appropriate threshold comparison operations and outputs the read results.

When using such built-in commands, the entire operation sequence for reading a given bit (which often involves multiple read operations that use multiple thresholds) is triggered by a single instruction. Thus, the use of built-in commands reduces the memory access overhead and the communication throughput to and from the memory device, in comparison with single-threshold read commands.

In various situations and applications, there is a need to re-read a given bit in a group of memory cells multiple times using multiple different thresholds. Reading a given bit using different thresholds may be carried out, for example, in order to adjust or optimize the read threshold values, in order to estimate and cancel interference and/or in order to compute soft metrics for decoding an Error Correction Code (ECC) that encodes the data. Embodiments of the present invention that are described hereinbelow provide highly-efficient methods and systems for re-reading analog memory cells using different thresholds, by utilizing built-in multiple-threshold commands supported by the memory device.

In some embodiments, a Memory Signal Processor (MSP) stores data in a memory device, which comprises an array of multi-bit analog memory cells. The memory device supports one or more built-in read commands for reading respective data bits from the cells. Each built-in read command uses a respective set of one or more read thresholds.

In order to read a given bit using multiple thresholds, the MSP sends the memory device a built-in read command specifying the desired multiple thresholds. The memory device executes the command, and thus re-reads the given bit using the desired multiple thresholds. Using this technique, the MSP re-reads a given bit multiple times by issuing only a single instruction, rather than using multiple single-threshold commands. As a result, the number of memory access operations performed by the MSP and the data throughput over the interface between the memory device and the MSP are reduced considerably. Typically, the re-reading functionality is transparent to the memory device and may be applied to legacy memory devices.

In some embodiments, the command issued for re-reading a given bit has a number of thresholds that is higher than the number of thresholds normally used for reading this bit. For example, the memory device typically comprises a built-in command that is predefined for reading the LSB using a single threshold. When using the disclosed methods, the LSB can be read four times from a group of cells by (1) issuing a built-in read command that is predefined for reading the MSB, and (2) specifying the four desired re-reading thresholds in the command.

In some embodiments, the MSP initially reads a given bit using the built-in command that is predefined for reading this bit, and reverts to a built-in command having a higher number of thresholds if the initial reading attempt fails. In some embodiments, the multiple thresholds used for re-reading are positioned between adjacent programming levels. Alternatively, one or more of the thresholds can be positioned within a storage value interval that is occupied by a programming level. This sort of threshold setting is useful, for example, for obtaining statistical information regarding the storage value distribution.

System Description

FIG. 1 is a block diagram that schematically illustrates a memory system 20, in accordance with an embodiment of the present invention. System 20 can be used in various host systems and devices, such as in computing devices, cellular phones or other communication terminals, removable memory modules (“disk-on-key” devices), Solid State Disks (SSD), digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved.

System 20 comprises a memory device 24, which stores data in a memory cell array 28. The memory cell array comprises multiple analog memory cells 32. In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array 28 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and CTF Flash cells, PCM, NROM, FRAM, MRAM and DRAM cells. Memory cells 32 comprise Multi-Level Cells (MLC, also referred to as multi-bit cells), each storing multiple data bits.

The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values or storage values. Although the embodiments described herein mainly address threshold voltages, the methods and systems described herein may be used with any other suitable kind of storage values.

System 20 stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values to the cell.

Memory device 24 comprises a reading/writing (R/W) unit 36, which converts data for storage in the memory device to storage values and writes them into memory cells 32. In alternative embodiments, the R/W unit does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells. The R/W unit typically (although not necessarily) programs the cells using an iterative Program and Verify (P&V) process, as is known in the art. When reading data out of array 28, R/W unit 36 converts the storage values of memory cells 32 into digital samples having a resolution of one or more bits. Data is typically written to and read from the memory cells in groups that are referred to as pages. Memory device 24 comprises one or more page buffers 38, which are used for caching data pages during data storage and retrieval.

The storage and retrieval of data in and out of memory device 24 is performed by a Memory Signal Processor (MSP) 40. MSP 40 comprises an interface 44 for communicating with memory device 24, and a signal processing unit 48, which processes the data that is written into and read from device 24. In some embodiments, unit 48 produces the storage values for storing in the memory cells and provides these values to R/W unit 36. Alternatively, unit 48 provides the data for storage, and the conversion to storage values is carried out by the R/W unit internally to the memory device. In some embodiments, unit 48 encodes the data for storage using an Error Correction Code (ECC) or Error Detection Code (EDC), and decodes the ECC or EDC of the data retrieved from the memory.

MSP 40 communicates with a host 52, for accepting data for storage in the memory device and for outputting data retrieved from the memory device. MSP 40, and in particular unit 48, may be implemented in hardware. Alternatively, MSP 40 may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements.

The configuration of FIG. 1 is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits and debugging circuits, have been omitted from the figure for clarity.

In the exemplary system configuration shown in FIG. 1, memory device 24 and MSP 40 are implemented as two separate Integrated Circuits (ICs). In alternative embodiments, however, the memory device and MSP may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC). Further alternatively, some or all of the MSP circuitry may reside on the same die on which the memory array is disposed. Further alternatively, some or all of the functionality of MSP 40 can be implemented in software and carried out by a processor or other element of the host system, or by a suitable memory controller. In some implementations, a single MSP 40 may be connected to multiple memory devices 24. In yet another embodiment, some or all of the MSP functionality may be carried out by a separate unit, referred to as a memory extension, which acts as a slave of memory device 24.

Typically, the MSP (or any other controller or processor that carries out some or all of the methods described herein) comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on tangible media, such as magnetic, optical, or electronic memory.

In a typical configuration, memory cells 32 of array 28 are arranged in a grid having multiple rows and columns, commonly referred to as word lines and bit lines, respectively. The array is typically partitioned into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Word lines are typically erased in blocks, referred to as erasure blocks, which are erased simultaneously.

The storage values read from memory cells 32 often vary from the nominal values, such as because of programming inaccuracies, reading inaccuracies and various distortion mechanisms. Thus, the storage values of the cells in a given programming level are distributed over a certain range in accordance with a certain statistical distribution. Typically, R/W unit 36 reads data from cells 32 by comparing the storage values of the cells to one or more read thresholds, in order to determine the programming level assumed by each cell. Such read operations are applied simultaneously to a group of memory cells within a certain word line.

Memory cells 32 comprise Multi-Level Cells (MLC), with each cell 32 storing two or more bits of data. For N bits/cell memory cells, each programming level represents a certain combination of N bit values. Determining the programming level assumed by a given cell is therefore equivalent to decoding the N data bits stored in the cell.

FIG. 2 is a graph showing storage value distributions and read thresholds in a group of multi-level analog memory cells 32, in accordance with an embodiment of the present invention. The example of FIG. 2 refers to an array of eight-level multi-level cells, with each cell storing three bits of data. The eight programming levels are denoted L1 . . . L8, and each level represents a unique combination of three bit values. For example, as marked in the figure, level L1 represents “111” data, level L2 represents “110” data, etc. In the notation used throughout this patent application, the left-most bit in the triplet is referred to as BIT1, the next bit is referred to as BIT2, and so on.

The storage values in each programming level are distributed in accordance with a certain statistical distribution 60. In some cases, such as when the level of distortion in the cells is particularly high, adjacent distributions 60 may overlap one another. R/W unit reads the data from the memory cells by comparing their storage values to a set of read thresholds 64A . . . 64G.

Although the description that follows refers mainly to the eight-level cell configuration of FIG. 2, the methods and systems described herein can be used with any other suitable kind of memory cells (e.g., four-level or sixteen-level cells), with any other suitable mapping of bit combinations to programming levels, and with any other suitable threshold arrangement.

Built-In Multi-Threshold Read Commands

In some embodiments, R/W unit 36 reads each bit of memory cells 32 (e.g., BIT1, BIT2 and BIT3 in FIG. 2) using a certain subset of the read thresholds. In the configuration of FIG. 2, for example, BIT1 is read by comparing the storage values to threshold 64D. As can be seen in the figure, all programming levels whose storage values are lower than threshold 64D have BIT1=“1”, and all programming levels whose storage values are higher than this threshold have BIT1=“0”. BIT2 is read by comparing the storage values of the cells to two thresholds 64B and 64F. Storage values falling between the two thresholds indicate that BIT2=“0”, and storage values falling below threshold 64B or above threshold 64F indicate that BIT2=“1”. Similarly, BIT3 is read by comparing the storage values of the cells to four read thresholds 64A, 64C, 64E and 64G.

Some memory devices support built-in read commands for retrieving given bits from a group of memory cells. In such memory devices, the R/W unit automatically sets the appropriate read thresholds for reading the requested bit, performs the appropriate threshold comparison operations, processes the comparison results (interim read results) to determine the bit values of the cells, and sends the bit values (final read results) to the MSP or controller.

For example, in the configuration of FIGS. 1 and 2, memory device 24 supports three built-in read commands—a first command for reading BIT1 from a group of memory cells, a second command for reading BIT2 from a group of memory cells, and a third command for reading BIT3 from a group of cells. In order to retrieve a certain bit from a certain group of memory cells, the MSP (or other controller) sends one of these commands to memory device 24. In response to receiving the request, R/W unit 36 in memory device 24 sets the (one or more) thresholds associated with the requested bit, performs the appropriate comparison operations, processes the interim read results of each cell, and returns the final read results to the MSP. In the present example, each built-in command reads a certain bit (e.g., BIT1, BIT2 or BIT3) independently of other bits of the memory cells.

The use of such built-in read commands is advantageous over simpler commands that perform only a single threshold comparison since it (1) reduces the number of memory device access operations and (2) reduces the amount of data transferred from the memory device to the MSP considerably. For example, reading BIT3 from a group of 8192 cells using single-threshold read commands would cause 4.8192=32768 interim read results to be transferred to the MSP. The MSP would then process these 32768 results (four single-threshold read results for every cell), to produce the requested 8192 final read results. Using built-in multi-threshold read commands, on the other hand, the 32768 interim read results are obtained and processed internally to the memory device, and only the final 8192 read results are transferred to the MSP. Using single-threshold read commands, the memory device is accessed seven times. Using the built-in multi-threshold commands, on the other hand, the memory device is accessed only once.

Efficient Multi-Threshold Reading Schemes Using Built-In Read Commands

In various situations and applications, MSP 40 performs multiple re-read operations of a given bit in a group of memory cells, using multiple different thresholds. Embodiments of the present invention, which are explained and demonstrated below, provide methods and systems that perform such re-read operations efficiently, by utilizing the built-in multiple-threshold commands supported by the memory device.

MSP 40 may re-read a given bit (i.e., read multiple instances of the given bit) with different thresholds for various purposes. For example, distributions 60 may drift, widen or otherwise change over time, such as because of aging or interference. When distributions 60 change, the optimal positions of the read thresholds often change, as well. In some embodiments, the MSP re-reads a given bit using multiple thresholds, and processes the multiple read results of this bit to optimize the threshold positions. Such techniques are described, for example, in PCT International Publications WO 2007/132457 and WO 2008/053472, cited above.

As another example, the MSP may re-read a given bit in a group of memory cells with different thresholds in order to cancel cross-coupling interference from other cells. In some embodiments, the MSP selects the least-interfered read results on a cell-by-cell basis. Some cross-coupling cancellation methods, which use multiple read results that are obtained using multiple read thresholds, are described in PCT International Publications WO 2007/132457 and WO 2008/053472, cited above.

As yet another example, the MSP may employ an ECC scheme that uses soft decoding metrics. In these embodiments, the MSP computes soft metrics of a given bit in a group of memory cells, and decodes the ECC using the soft metrics. The MSP computes the soft metrics by re-reading the bits in question using multiple different thresholds, and processes the multiple read results to produce the metrics. Soft metric computation techniques of this sort are described, for example, in PCT International Publications WO 2007/132457 and WO 2008/053472, cited above.

FIG. 3 is a graph showing read thresholds 68 used for reading data from multi-level analog memory cells 32, in accordance with an embodiment of the present invention. In the example of FIG. 3, system 20 performs re-read operations using a set of seven thresholds 68, which are positioned between programming levels L4 and L5. This scenario may occur, for example, when the MSP attempts to optimize the position of the read threshold that differentiates between levels L4 and L5, or when the MSP computes soft ECC decoding metrics.

In some embodiments, the MSP instructs R/W unit 36 to perform the seven re-read operations using the built-in multi-threshold read operations supported by the memory device. In the present example, the MSP sends three read commands to the memory device:

• • A BIT1 read command specifying a single threshold (denoted “BIT1 TH” in the figure).
  • A BIT2 read command specifying two thresholds (denoted “BIT2 THRESHOLDS” in the figure), one threshold on either side of the BIT1 threshold.
  • A BIT3 read command specifying four thresholds (denoted “BIT3 THRESHOLDS” in the figure), interleaved among the BIT1 and BIT2 thresholds.

By executing these three multi-threshold read commands, the R/W unit compares the storage values of the cells to seven thresholds and transfers three sets of read results to the MSP. The read results can be used by the MSP for adjusting threshold positions, for performing interference cancellation, for computing soft metrics or for any other purpose.

In the present example, the built-in commands supported by the memory device are predefined to read BIT1 using a single threshold, BIT2 using two thresholds and BIT3 using four thresholds. In the process described above, however, BIT1 is read using the built-in commands that are predefined for reading BIT2 and BIT3. These commands have a higher number of thresholds than the number that is predefined for reading BIT1.

In some embodiments, the values of the thresholds to be used are specified as part of the built-in read command. Alternatively, the values can be provided to the memory device in a separate command that is sent adjacently to the built-in read command, or using any other suitable means.

FIG. 4 is a flow chart that schematically illustrates the method described above for reading data from multi-level analog memory cells, in accordance with an embodiment of the present invention. The method begins with system 20 storing data in multi-level analog memory cells 32 of array 28, at a storage step 70. In the present example, cells 32 comprise eight-level (3 bits/cell) MLC, as shown in FIG. 2.

At some point in time, MSP 40 initiates a process of reading BIT1 from a group of memory cells 32 using multiple thresholds. The process may be initiated in order to adjust read threshold positions, in order to cancel cross-coupling interference, in order to compute soft metrics, or for any other reason.

The MSP sets the values of the read thresholds in the BIT1, BIT2 and BIT3 built-in read commands, at a threshold setting step 74. The MSP positions the seven thresholds to fall between programming levels L4 and L5, as shown in FIG. 3 above. The MSP sends the three commands to the memory device.

R/W unit 36 in memory device 24 executes the three commands. The R/W unit executes the BIT1 command at a first bit reading step 78, the BIT2 command at a second bit reading step 82, and the BIT3 command at a third bit reading step 86. The BIT1, BIT2 and BIT3 commands use one, two and four thresholds, respectively. Since, as noted above, each read command reads a given bit independently of the other bits, steps 78-86 can be executed in any order.

Device 24 sends the BIT1 read results produced by the three built-in read operations (which comprise results originating from seven thresholds) to the MSP, at a result reporting step 90. The MSP applies the desired processing (e.g., threshold adjustment, cross-coupling interference cancellation or soft metric computation) to the returned read results.

Increasing the Number of Thresholds in Response to Decoding Failure

In some embodiments, the MSP initially reads a given bit using the built-in command that is originally predefined for reading this bit, and reverts to a command having a higher number of thresholds if the initial reading attempt fails. The command that the MSP reverts to comprises a command that is originally predefined for reading another bit of the memory cells, and is referred to herein as an alternative command.

The MSP may use any suitable criteria for determining read failures, such as a failure to decode an ECC that decodes the retrieved data, an error indication of an EDC, an intolerable error level in the reconstructed data or a distortion level that exceeds a certain tolerable level.

In some embodiments, the MSP sets the thresholds of the alternative command to fall in the vicinity of the threshold used in the initial unsuccessful attempt. For example, the MSP may apply the method of FIGS. 3 and 4 above in a gradual manner. In this implementation, the MSP first reads BIT1 using the single “BIT1 TH” threshold. If the initial attempt fails, the MSP re-reads BIT1 using the BIT2 read command, specifying the two “BIT2 THRESHOLDS” shown in FIG. 3. If this attempt fails too, the MSP re-reads BIT1 once again using the four BIT3 thresholds. At all stages, the read thresholds are positioned between programming levels L4 and L5, as shown in FIG. 3.

In some embodiments, the MSP comprises logic (in hardware or software) for converting the read results of one built-in command to the format of another built-in command, so that the read results can be interpreted correctly. For example, when reading BIT1 using the BIT2 built-in command, the MSP may comprise logic for separating the read results of the BIT2 read command into two single-bit read results having two different thresholds, so as to appear to subsequent processes as read results of two BIT1 read commands.

As another example, the MSP may comprise logic that generates, in response to the read results of the BIT2 read command, a BIT1-equivalent stream having different thresholds for different cells. As noted above, using different thresholds for different cells is useful, for example, in interference cancellation processes. Alternatively, the MSP may carry out interference cancellation computations directly on the read results of the BIT1 and BIT2 built-in commands.

In some embodiments, one or more of the thresholds in the alternative command are set to fall in the vicinity of the initial threshold, while one or more other thresholds are set to fall in any other suitable region of the storage value axis. Unlike the previous example, in which the number of thresholds was increased to improve the reading performance of BIT1, in the present embodiment the added threshold or thresholds are used to sample the storage value distribution at an additional point. The additional thresholds may be positioned between programming levels and thus assist in subsequently reading other bits from the memory cells. Alternatively, the additional thresholds may be positioned within the distribution of a given programming level, and therefore improve the statistical information of the MSP regarding this distribution.

FIG. 5 is a graph showing storage value distributions and read thresholds in a group of multi-level analog memory cells, in accordance with another embodiment of the present invention. In the present example, the MSP initially attempts to read BIT1 using the BIT1 read command. The initial read attempt uses an initial threshold 94. As can be seen in the figure, the initial threshold is not positioned properly, since it falls inside the distribution of level L5 instead of between levels L4 and L5. Therefore, this initial attempt is likely to fail.

Upon a failure of the initial attempt, the MSP makes a second attempt to read BIT1. In the second attempt, the MSP instructs the R/W unit to use the BIT2 read commands that compares the storage values of the cells to two thresholds 98. In the example of FIG. 5, one of thresholds 98 is set between levels L4 and L5 by correcting the non-optimal position of threshold 94. The second threshold 98 is set to the middle of the distribution of level L6. The MSP may use the read results corresponding to the second threshold for constructing histograms or other statistical functions of the storage values of the cells, for obtaining better resolution in future read operations, or for any other purpose.

FIG. 6 is a flow chart that schematically illustrates a method for reading data from multi-level analog memory cells 32, in accordance with an embodiment of the present invention. The method demonstrates the features of (1) reading a given bit using a built-in command that is originally predefined for reading another bit, and (2) reverting to this built-in command only upon a failure in the default reading process.

The method of FIG. 6 begins with system 20 reading BIT1 from a group of memory cells 32 using a single threshold, at an initial reading step 100. Referring to FIG. 5 above, BIT1 is initially read using threshold 94 by executing the built-in BIT1 read command.

The MSP then checks whether the initial read attempt was successful, at a success checking step 104. As noted above, the success criterion may depend on successful ECC or EDC decoding, on distortion measurement or on any other factor. If the initial attempt was successful, the MSP reconstructs the read data, outputs the result and terminates, at a termination step 108.

Otherwise, i.e., if the initial read attempt failed, the system re-reads BIT1 using the built-in BIT2 read command. The MSP specifies two thresholds for this command, at a threshold setting step 112. The two thresholds comprise (1) a corrected or adjusted threshold for reading BIT1, and (2) a second threshold positioned within another distribution. The first threshold is used for re-reading BIT1, while the second threshold is used for improving the statistical knowledge of the MSP regarding the storage value distributions in the memory cells. Referring to FIG. 5, the built-in BIT2 read command uses thresholds 98.

The MSP sends the command to the memory device, and R/W unit 36 executes the command, at an execution step 116. The R/W unit sends the read results to the MSP. The MSP reconstructs the data, outputs the result and terminates at step 108.

Additional Examples

The principles of the present invention can be used to define and execute various sequences of read operations that use the built-in read commands supported by the memory device. Such read sequences may improve the reading speed and/or quality under different scenarios.

FIG. 7 is a graph showing storage value distributions and read thresholds in a group of multi-level analog memory cells, in accordance with yet another embodiment of the present invention. In the present example, the MSP initially reads BIT1 using a single threshold 120, by sending the built-in BIT1 read command to the memory device. As can be seen in the figure, threshold 120 is positioned incorrectly, and therefore the initial read attempt is likely to fail. In a second read operation, the MSP reads BIT2 using the built-in BIT2 read command, which uses two thresholds 124. In this case too, thresholds 124 are positioned incorrectly and the read attempt fails.

In response to the two failures, the MSP makes a third attempt to read both BIT1 and BIT2 by issuing a single BIT3 read command, which uses four thresholds 128. Thresholds 128 are positioned so that the results of the BIT3 command, when combined with the results of the failed BIT1 and BIT2 commands, enable successful decoding of BIT1 and BIT2. This scheme is thus able to decode BIT1 and BIT2 after a failure by issuing only a single additional read command. In comparison with known methods, this scheme provides smaller read latency and less communication throughput between the MSP and the memory device.

FIG. 8 is a graph showing storage value distributions and read thresholds in a group of multi-level analog memory cells, in accordance with another embodiment of the present invention. The example of FIG. 8 demonstrates a scenario in which BIT1 and BIT2 are read successfully using the respective predefined commands. Reading of BIT3, on the other hand, fails. The single threshold used for reading BIT1 is denoted “I” in the figure. The two thresholds used for reading BIT2 are denoted “II”, and the four thresholds used for reading BIT3 are denoted “III”. The failure in reading BIT3 in this example is caused by the left-most threshold of the BIT3 read command, i.e., the “III” threshold between levels L1 and L2.

In order to adjust this ill-positioned threshold and successfully read BIT3, the MSP carries out a fourth read attempt. The MSP sends another BIT3 read command, this time with four thresholds denoted “IV” in the figure. Two thresholds of the new command are positioned around the failed threshold. Thus, the thresholds of the BIT3 read commands can be adjusted using the additional information obtained by the fourth read attempt.

FIG. 9 is a graph showing storage value distributions and read thresholds in a group of multi-level analog memory cells, in accordance with yet another embodiment of the present invention. The example of FIG. 9 shows a scenario in which the MSP reads BIT1 . . . BIT3 using a sequence of four read commands. The first command comprises a single-threshold command with a threshold denoted “I”. The second command comprises a dual-threshold command with thresholds denoted “II”. The third command comprises a four-threshold command with thresholds denoted “III”. The fourth command comprises another four-threshold command with thresholds denoted “IV”.

In this example, it is known a-priori that the left-most threshold used for reading BIT3 (the threshold between levels L1 and L2) is ill-positioned or unknown. Consequently, the entire read sequence is designed a-priori to provide additional resolution in the vicinity of this threshold. The combined results of the four read attempts enable successful decoding of BIT1 . . . BIT3, regardless of the actual optimal position of the left-most threshold.

Although the embodiments described herein mainly address read operations in solid-state memory devices, the principles of the present invention can also be used for storing and retrieving data in Hard Disk Drives (HDD) and other data storage media and devices.

It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Claims

1. A method for data storage, comprising: storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; andafter storing the data, reading the first data bits from the memory cells by executing at least the second built-in command,wherein reading the first data bits by executing at least the second built-in command comprises reading multiple instances of the first data bits using the respective second thresholds.

2. The method according to claim 1, and comprising processing the multiple instances of the first data bits so as to adjust the first thresholds.

3. The method according to claim 1, and comprising processing the multiple instances of the first data bits so as to cancel interference in the analog memory cells.

4. The method according to claim 1, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), and comprising processing the multiple instances of the first data bits so as to compute soft decoding metrics for decoding the ECC.

5. A method for data storage, comprising: storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; andafter storing the data, reading the first data bits from the memory cells by executing at least the second built-in command,wherein reading the first data bits by executing at least the second built-in command comprises making an attempt to read the first data bits using the first built-in command, and reverting to read the first data bits using the second built-in command responsively to a failure of the attempt.

6. The method according to claim 1, wherein each of the analog memory cells further stores a third data bit, wherein the memory has a third built-in command for reading the third data bits of the memory cells by comparing the storage values of the memory cells to a third number of third thresholds, such that the third number is larger than the second number, and wherein reading the first data bits comprises executing both the second and the third built-in commands.

7. The method according to claim 1, wherein storing the data comprises writing to the memory cells nominal storage values selected from a group of possible nominal storage values corresponding to the respective programming levels, and wherein executing at least the second built-in command comprises positioning the second thresholds between a pair of the nominal storage values that are adjacent to one another in the group of the possible nominal storage values.

8. The method according to claim 1, wherein the storage values of the memory cells that assume a given programming level are distributed over a range, and wherein executing at least the second built-in command comprises positioning at least one of the second thresholds within the range.

9. The method according to claim 1, wherein the second built-in command reads the second data bits independently of the first data bits.

10. A method for data storage, comprising: storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to one or more first thresholds, and a second built-in command for reading the second data bits of the memory cells independently of the first data bits by comparing the storage values of the memory cells to a plurality of second thresholds; andafter storing the data, reading the first data bits from the memory cells by executing at least the second built-in command,wherein reading the first data bits by executing at least the second built-in command comprises reading multiple instances of the first data bits using the respective second thresholds.

11. Apparatus for data storage, comprising: an interface, which is operative to communicate with a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; anda processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command,wherein the processor is coupled to read multiple instances of the first data bits using the respective second thresholds by executing at least the second built-in command.

12. The apparatus according to claim 11, wherein the processor is coupled to process the multiple instances of the first data bits so as to adjust the first thresholds.

13. The apparatus according to claim 11, wherein the processor is coupled to process the multiple instances of the first data bits so as to cancel interference in the analog memory cells.

14. The apparatus according to claim 11, wherein the processor is coupled to encode the stored data with an Error Correction Code (ECC), and to process the multiple instances of the first data bits so as to compute soft decoding metrics for decoding the ECC.

15. Apparatus for data storage, comprising: an interface, which is operative to communicate with a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; anda processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command,wherein the processor is coupled to make an attempt to read the first data bits using the first built-in command, and to revert to read the first data bits using the second built-in command responsively to a failure of the attempt.

16. The apparatus according to claim 11, wherein each of the analog memory cells further stores a third data bit, wherein the memory has a third built-in command for reading the third data bits of the memory cells by comparing the storage values of the memory cells to a third number of third thresholds, such that the third number is larger than the second number, and wherein the processor is coupled to read the first data bits by executing both the second and the third built-in commands.

17. The apparatus according to claim 11, wherein the processor is coupled to store the data by writing to the memory cells nominal storage values selected from a group of possible nominal storage values corresponding to the respective programming levels, and to position the second thresholds, which are used in executing the second built-in command, between a pair of the nominal storage values that are adjacent to one another in the group of the possible nominal storage values.

18. The apparatus according to claim 11, wherein the storage values of the memory cells that assume a given programming level are distributed over a range, and wherein the processor is coupled to position at least one of the second thresholds, which are used in executing the second built-in command, within the range.

19. The apparatus according to claim 11, wherein the second built-in command reads the second data bits independently of the first data bits.

20. Apparatus for data storage, comprising: a memory comprising multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; anda processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command,wherein the processor is coupled to read multiple instances of the first data bits using the respective second thresholds by executing at least the second built-in command.

21. Apparatus for data storage, comprising: an interface, which is operative to communicate with a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to one or more first thresholds, and a second built-in command for reading the second data bits of the memory cells independently of the first data bits by comparing the storage values of the memory cells to a plurality of second thresholds; anda processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command,wherein the processor is coupled to read multiple instances of the first data bits using the respective second thresholds by executing at least the second built-in command.

22. Apparatus for data storage, comprising: a memory comprising multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to one or more first thresholds, and a second built-in command for reading the second data bits of the memory cells independently of the first data bits by comparing the storage values of the memory cells to a plurality of second thresholds; anda processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command,wherein the processor is coupled to read multiple instances of the first data bits using the respective second thresholds by executing at least the second built-in command.

23. A method for data storage, comprising: storing data in a memory that includes analog memory cells, each of which stores one or more data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, such that the data is readable from the memory cells by comparing the storage values to a first number of thresholds; andafter storing the data, issuing to the memory a single read command, which causes the memory to compare the storage values to a second number of thresholds, larger than the first number,wherein issuing the single read command comprises causing the memory to read multiple instances of each of the data bits.

24. The method according to claim 23, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), and comprising processing the read multiple instances of the data bits so as to compute soft decoding metrics for decoding the ECC.

25. Apparatus for data storage, comprising: an interface, which is operative to communicate with a memory that includes analog memory cells, each of which stores one or more data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, such that the data is readable from the memory cells by comparing the storage values to a first number of thresholds; anda processor, which is configured to store data in the memory cells, and, after storing the data, to issue to the memory a single read command, which causes the memory to compare the storage values to a second number of thresholds, larger than the first number,wherein the single read command causes the memory to read multiple instances of each of the data bits.

26. The apparatus according to claim 25, wherein the processor is configured to encode the stored data with an Error Correction Code (ECC), and to process the read multiple instances of the data bits so as to compute soft decoding metrics for decoding the ECC.