Patent Application
20250047276
The present application relates to the field of circuits provided with transistors containing GaN and provided with means for preventing the phenomenon of current collapse in these transistors.
It relates in particular to the circuits provided with HEMT (“High Electron Mobility Transistor”) transistors and applies in particular to the power circuits such as power inverters or DC/DC and DC/AC converters.
The transistors containing GaN of the HEMT type have the advantage in particular of supporting high current densities as well as high voltages in the off state. They have uses in the field of power circuits such as electric energy converters and power inverters.
However, these transistors, and more generally the transistors having a channel structure comprising a layer of GaN, are subject to a phenomenon of current collapse caused by electron traps in their semiconductor structure. Such a phenomenon is mentioned for example in the document by T. Hasan, “Mechanism and Suppression of Current Collapse in AlGaN/GaN High Electron Mobility Transistors” PhD thesis-University of Fukui, Japan 2013.
The origin of such traps can be a consequence of several factors, for example such as crystalline defects, dislocations, or the presence of impurities. Such traps can also be located in the interface between various semiconductor materials and passivation layers. In the transistors containing GaN, the traps are mainly located in the GaN or in the interface between this layer and another wide-bandgap material for example containing AlGaN.
The phenomenon of current collapse significantly affects circuits in particular the power circuits such as converters and power inverters, furthermore when operation at high temperature and at low operating voltage is required. This can even cause thermal breakage of the components.
It is therefore sought to monitor and prevent this phenomenon in the circuits provided with such components.
Thus, an embodiment of the present invention relates to an electronic device provided with transistors containing GaN, comprising a control circuit configured to evaluate the drain source resistance in the on state of at least one first transistor out of said transistors.
The control circuit can be provided:
Advantageously, the evaluation stage of the control circuit is provided with a digital calculation module integrated into a microcontroller or into an integrated circuit having a network of programmable cells and/or includes an analogue divider or an analogue multiplier.
According to an advantageous embodiment, the control circuit can be further provided with a protection circuit, the protection circuit comprising a first comparator to compare the first evaluation signal to a given threshold, the protection circuit being configured to, when the first evaluation signal exceeds the given threshold, emit a deactivation signal so as to maintain said first transistor off.
Thus, besides a simple monitoring of the change in the dynamic drain source resistance, a protection of the transistor containing GaN can be implemented.
The control circuit can be provided with a first gate pilot circuit producing said first control signal, the deactivation signal being emitted at the input of said first gate pilot circuit.
According to one possible embodiment wherein among said transistors at least one second transistor is coupled to the first transistor, a gate of the second transistor being controlled by a second control signal, the second control signal being except for dead times in phase opposition to the first control signal, said circuit branch being arranged between the first transistor and the second transistor so that the load current is the image of the current passing through the second transistor when the second transistor is in the on state, said control circuit may further provided:
Advantageously, the control circuit is provided with a protection circuit and the gate of the second transistor is controlled by a second gate pilot circuit. Advantageously, the protection circuit is provided with a second comparator to compare said second evaluation signal to another given threshold, the protection circuit being further configured to, when the second evaluation signal exceeds said other given threshold, emit a second deactivation signal at the input of a second gate pilot circuit so as to maintain said second transistor off.
According to one possible embodiment, the first switch element is controlled by a measurement triggering signal, the control circuit further comprising a stage for controlling the signal of the first control signal and of the measurement triggering signal to, consecutively to a change in state of the first control signal turning the first transistor on, trigger, after a first determined delay after this change, a state modification of the measurement triggering signal so as to turn the first switch element on and to, consecutively to a new state modification of the measurement triggering signal turning the first switch element on, trigger a new state change of the control signal turning the first transistor off.
Thus, advantageously, a measurement of drain source resistance is carried out on a GaN transistor only when this transistor is turned on.
According to an advantageous embodiment, the first amplifier is powered via an external battery.
According to another aspect the present invention relates to a power electronic device such as a power inverter or a converter provided with a device having transistors as defined above, the first transistor belonging to one arm of the power inverter or a switching cell of the converter or, if necessary, the first transistor and the second transistor belonging to the same arm of the power inverter or to the same switching cell of the converter.
The present invention will be better understood on the basis of the following description and the appended drawings in which:
Identical, similar or equivalent parts of the various drawings carry the same numerical references so as to facilitate the passage from one drawing to the other.
The various parts shown in the drawings are not necessarily on a uniform scale, to make the drawings more readable.
Reference is now made to
The transistors 11, 12 are in this example HEMT transistors belonging to a power electronic device and in particular to a power inverter 5 allowing to generate voltages and alternating currents from a source of electric energy with DC voltage.
The stage 20 allows to carry out a measurement and a monitoring of a power-inverter arm on the basis of drops in drain source voltage in the transistors 11, 12 containing GaN when the latter are placed in the on state.
The transistors 11, 12, the respective dynamic drain source resistances RDS_ON1, RDS_ON2 of which in the on state are monitored, belong here to the same power-inverter arm 5. The transistors 11, 12 operate as complementary switches with typically at least one dead time intended to avoid a simultaneous conduction of these transistors 11, 12 in the arm of the converter.
Thus, outside of the dead times (intervals Tm=t2−t1, T′m=t6−t5 in the chronogram of
The measurement stage 20 of the control circuit allows to obtain the voltage drops in the transistors 11, 12 in the on state as well as a value of the current which passes through the transistors 11, 12 in the on state.
The control circuit can also be provided to, according to the values of measurements of drain source voltage VDS1_ON, VDS2_ON of the transistors in the on state and the current passing through the transistors in the on state, evaluate the dynamic resistance in the on state of the transistors 11, 12.
The control circuit can also be designed to, according to values of dynamic resistance in the on state of the transistors 11, 12, control their respective control signals SG1, SG2.
The measurement stage 20 of the control circuit is provided with a first measurement circuit 21 coupled to the first transistor 11 in order to determine the drain source voltage in the on state VDS1_ON of the first transistor 11. This first measurement circuit 21 is provided here with an operational amplifier Op-Amp1 mounted in differential mode and according to a linear mounting, with an output looping onto its inverting input.
The operational amplifier Op-Amp1 is in particular mounted in differential mode 41 to produce at the output an output voltage Vds1_ON proportional to a difference in potentials between a drain electrode D1 potential of the first transistor 11 placed in the on state and a source electrode S1 potential of the first transistor 11 placed in the on state.
The operational amplifier Op-Amp1 is provided with an input coupled to a drain electrode D1 of the first transistor 11 and with another input coupled to a source electrode S1 of the first transistor 11. In the example illustrated, the source S1 is thus connected to the non-inverting input E+ of the operational amplifier Op-Amp1 while the drain D1 is coupled to the inverting input E− of the amplifier Op-Amp1.
A switch element 31 is arranged between the drain electrode D1 of the first transistor 11 and the input E− of the amplifier Op-Amp1. This switch element 31 is formed in this example by a coupling transistor M1 here of the N type, the gate of which is controlled by a measurement control signal SM1, to activate the coupling transistor M1 during a measurement phase.
In order to avoid a circulation of current from the drain of the first transistor 11 towards the amplifier Op-Amp1, a current-blocking element such as a diode 33 is provided here in parallel with the coupling transistor M1.
The switch element 31 is controlled (change of state in this example at a high potential of the measurement control signal SM1 applied to the gate of the coupling transistor M1 at the time t3) so as to couple the drain electrode D1 of the first transistor 11 to the amplifier consecutively to the first transistor 11 being made conductive (change of state in this example at a high potential of the signal SG1 of the transistor 11 at the time t2). The measurement of drain source voltage is thus carried out while the first transistor 11 is made conductive. When the measurement phase is over, the measurement control signal SM1 is modified (change of state and setting to a low potential of the signal SM1 applied to the gate of the first transistor M1 at the time t4) so as to decouple the drain electrode D1 of the first transistor 11 from the amplifier Op-Amp1. Then, once the measurement phase is over, the control signal SG1 changes state (time t5) so as to deactivate the first transistor 11. The measurement phase and the coupling of the first transistor 11 to the measurement stage 20 are thus only carried out when the first transistor 11 is activated (i.e. placed in the on state).
The measurement control signal SM1 can be produced on the basis of the signal SG1 allowing to control the gate of the first transistor 11, in particular by applying to this signal SG1 an adjustable predetermined delay Tdelay1b when the latter is modified (here goes to a high state) so as to turn on the first transistor 11. When the measurement phase ends, the placing of the first transistor 11 back into the off state is triggered after a predetermined delay Tdelay2a=t5−t4.
These delays Tdelay1b, Tdelay2a are provided in order to not disturb the switching behaviour of the first transistor 11 when its voltage drop is measured. These delays Tdelay1b, Tdelay2a can be approximately respectively ten nanoseconds and several tens of nanoseconds. Thus, the transistor M1 of the measurement stage is activated about ten ns after the activation of the transistor 11 and turned off several tens of ns before the turning off of the transistor 11 is triggered. The control signal SM1 and the delays Tdelay1b. Tdelay2a can be respectively produced and modulated via a digital circuit of the microcontroller type or an FPGA and advantageously the same digital circuit as that producing the signals for controlling the transistors 11, 12.
The current passing through the first transistor 11 when it is made conductive is measured here via a circuit branch 24 coupled to a load R_LOAD. In said branch a load current ILOAD that is an image of a current passing through the first transistor 11 in the on state. This branch 24 is connected to a middle point between the source S1 of the first transistor 11 and the drain D2 of the second transistor 12.
Insofar as the second transistor 12 is made non-conductive in other words is turned off when the first transistor 11 is made conductive, the load current ILOAD is substantially equal or proportional to the current passing through the first transistor in the on state during the phase of measurement of VDS_ON1.
A current sensor 25, for example of the ACS712-30A type, allows to measure the current passing through the load after the middle point S1-D2.
The current sensor 25 allows to evaluate the current ILOAD and consequently the current passing through the first transistor 11 in the on state.
The control circuit is, in this example, provided with a second measurement circuit 22 coupled this time to the second transistor 12 in order to determine the drain source voltage in the on state VDS2_ON of the second transistor 12.
The second measurement circuit 22 is advantageously provided with a configuration similar to that of the first measurement circuit 21 with an operational amplifier mounted in differential mode Op-Amp2 and including an input coupled to an electrode of the second transistor 12 and another input coupled to another electrode of the second transistor 12.
The two operational amplifiers mounted in differential mode Op-Amp1, Op-Amp2 are advantageously provided with a high slew rate, that is to say typically of at least 100V/us.
The two operational amplifiers Op-Amp1 and Op-Amp2 can be powered between V+ and V− and advantageously via an external battery 111. This allows to minimise the disturbances in the measurements.
The second circuit 22 is also provided with its switch element 32. Consecutively to an activation of the second transistor 12 (time to in
The current passing through the second transistor 12 while it is made conductive is measured via the branch 24 by evaluating using the current sensor 25 the load current ILOAD. Insofar as the first transistor 11 is made non-conductive in other words is turned off when the second transistor 12 is made conductive, the load current ILOAD is substantially equal or proportional to the current passing through the second transistor in the on state during the phase of measurement of VDS_ON2.
The measurement phase and the coupling of the second transistor 12 to the measurement stage 20 are thus only carried out when the second transistor 12 is activated (i.e. placed in the on state).
In this exemplary embodiment a measurement of drain source resistance of the first transistor only when the latter is turned on, then a measurement of drain source resistance of the second transistor only when the latter is turned on are alternatingly carried out, the first transistor and the second transistor not being turned on simultaneous but alternatingly.
Advantageously, the coupling transistors M1, M2 allowing during the measurement phases to establish the connection between the GaN transistors 11, 12 and the measurement amplifiers Op-Amp1, Op-Amp2 are transistors of the MOSFET type chosen for their switching rapidity.
In
Advantageously, besides a monitoring of the values of drain source resistance in the on state, it is possible to provide protection of the transistors 11, 12 when these values reach levels that are too high.
The stage 50 can thus also be provided to modify the signals SG1, SG2 for controlling the transistors 11, 12 according to the values of drain source resistance determined.
The stage 50 in particular when it includes a microcontroller or an integrated circuit of the type with a network of programmable cells (FPGA for “Field Programmable Gate Array”) can also be provided to produce the measurement control signals SM1, SM2.
In the specific exemplary embodiment illustrated in
In the specific exemplary embodiment illustrated, the evaluation of the drain source resistances in the on state is carried out using an analogue multiplier 62 receiving at the input the load current ILOAD, the output voltage VDS1_ON of the first amplifier Op-Amp1, the output voltage VDS2_ON of the second amplifier Op-Amp2. The multiplier 62 is capable of producing at the output a first evaluation signal S_eval1 representative of the ratio between said output voltage VDS1_ON of the first amplifier Op-Amp1 and said load current ILOAD, as well as a second evaluation signal S_eval2 representative of the ratio between said output voltage VDS2_ON of the second amplifier Op-Amp2 and said load current ILOAD.
The evaluation signals S_eval1, S_eval2 are here emitted at the input and in particular on the inverting input respectively of a first comparator 64A and of a second comparator 64B. As for the non-inverting inputs of the comparators 64A, 64B, they are respectively set to a fixed potential Vréf_1, Vréf_2 on which the given threshold depends.
According to the result of the comparison with a first fixed potential Vréf_1 (respectively a second fixed potential Vréf_2), the first comparator 64A (respectively the second comparator 64B) is configured to produce a first deactivation signal Sdisable1, (resp. a second deactivation signal Sdisable2) intended for a first gate pilot circuit 71 (resp. for a second pilot circuit 72) so as to deactivate the first transistor 11 (resp. the second transistor 12), the drain source resistance of which in the on state is too high.
The gate pilots 71, 72 are typically provided with a power amplifier and accept at the input a pulse width modulation signal PWM1, PWM2 (PWM for Pulse Width Modulation) coming from a digital circuit as mentioned above.
In this example the evaluation signals S_eval1, S_eval2 representative respectively of the dynamic drain source resistance RDS_ON1 of the first transistor 11 and of the dynamic drain source resistance RDS_ON2 of the second transistor 12 can be digitised and memorized via a monitoring and save circuit 80 provided with an analogue-digital converter stage and with at least one memory. This circuit 80 can be for example formed by a microcontroller or by an FPGA.
A monitoring of dynamic resistance in the on state of each GaN transistor is thus implemented and a saving of the data for analyses later can be carried out. A protection of the transistors 11 and 12 is also carried out in the case in which the critical dynamic resistance values are reached in order to avoid the destruction of components and/or of the system.
In the example described above in relation to
The transistor is made from a semiconductor substrate 502, for example containing silicon, on which a semiconductor block comprising a heterojunction is disposed. The heterojunction is made of a stack comprising a first layer 504 of a III-N semiconductor material having a first forbidden band and a second layer 506 of a III-N semiconductor material having a second forbidden band, larger than said first forbidden band. When the transistor contains GaN, the first layer 504 typically contains GaN while the second layer 506 can, for example, be made of AlGaN.
The transistor further comprises source 507 and drain 508 electric contacts, which are disposed on and in contact with regions of the layer 506. Each of the electric contacts 507 and 508 can be a metal layer or a stack of metal layers. A 2-DEG two-dimensional electron gas can be formed in a channel region located in the first layer 504, typically under the interface between the second layer 506 and the first layer 504.
The transistor further comprises a gate electrode 510 that is disposed in contact and here on a part of the second layer 506 to control the two-dimensional electron gas. The gate electrode 510 is formed by an upper region 511 that contains metal and that is in contact with a lower semiconductor region 512 for example containing p-GaN.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/FR2021/052385 | 12/17/2021 | WO |
