Receive circuit

Abstract

A method and a circuit for decoding a coded signal including a first decoding system capable of receiving the coded signal and of providing a first signal comprising portions considered correct and a second decoding system capable of providing a second signal from the coded signal and from portions considered correct of the first signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a circuit for transmitting coded signals;

FIG. 2 is a diagram of a circuit-for receiving coded signals;

FIG. 3 schematically shows a portion of a digital signal provided by an encoder of “Reed-Solomon”-type;

FIG. 4 is a diagram of an example of a convolutional encoder;

FIG. 5 is a diagram of a simple example of a convolutional encoder;

FIG. 6 is a diagram illustrating the possible state switchings of the flip-flops of the encoder of FIG. 5;

FIG. 7 is a diagram of a lattice showing the method implemented by a Viterbi decoder;

FIG. 8 is a diagram of a portion of a Viterbi decoder corresponding to the encoder of FIG. 5;

FIG. 9 is a diagram of an example of a circuit according to the present invention;

FIG. 10 is a diagram illustrating a method implemented by elements of the circuit of FIG. 9;

FIG. 11 is a diagram of an embodiment of the circuit of FIG. 9;

FIG. 12 is a diagram illustrating the operation of a device of the circuit of FIG. 11;

FIG. 13 is a diagram of another embodiment of the circuit of FIG. 9;

FIG. 14 is a diagram illustrating a signal provided by a device of the circuit of FIG. 13;

FIG. 15 is a diagram of a portion of a decoding device according to the present invention;

FIG. 16 is a conventional diagram of a “dual-channel” receive circuit enabling processing two coded signals;

FIG. 17 is a diagram according to an embodiment of the present invention of a dual-channel receive circuit that can operate as a “single-channel” receive circuit;

FIG. 18 is a diagram according to a second embodiment of the present invention; and

FIG. 19 is a diagram according to another embodiment of the present invention of a dual-channel receive circuit that can operate as a “single-channel” receive circuit.

Claims

1. A receive circuit comprising first and second receive channels enabling receiving first and second distinct modulated and coded signals, the first receive channel comprising a first demodulator capable of receiving the first modulated and coded signal and of providing a coded signal to a first decoding circuit and the second receive channel comprising a second demodulator coupled to a second decoding circuit, the first decoding system being capable of receiving the coded signal and of providing a first decoded signal comprising portions considered correct; characterized in that it further comprises: a delay device having an input connected to the input or the output of the first demodulator;a multiplexer with two inputs and one output, the inputs of the multiplexer being respectively coupled to the delay device and to the input or the output of the second demodulator, the output of the multiplexer being coupled to the input or the output of the second demodulator;a control device comprising means for generating a corrected signal from signals provided by the first decoding circuit and means for controlling the second decoding circuit and/or the second demodulator; anda circuit capable of providing a selection signal controlling the multiplexer and the control device, wherein, when the selection signal is positioned to let through the signal provided by the delay device, the second decoding system and/or the second demodulator are capable of providing a second decoded signal from the coded signal or the first modulated and coded signal and from portions considered correct of the first decoded signal.

2. The decoding circuit of claim 1, wherein the first decoding system comprises a first decoder, a first deinterleave device coupled to the first decoder, and a second decoder coupled to the first deinterleave device, and wherein the second decoding system comprises a third decoder, a second deinterleave device coupled to the third decoder, and a fourth decoder coupled to the second deinterleave device.

3. The decoding circuit of claim 2, wherein the third decoder is coupled to a delay device receiving the coded signal and to the second decoder via an interleave device.

4. The decoding circuit of claim 3, wherein the signal provided by the interleave device is formed of multiplets comprising validity bits indicating whether the multiplets are correct.

5. The decoding circuit of claim 2, wherein the first decoder is a decoder using a Viterbi algorithm, and wherein the second and fourth decoders are error-correction decoders of Reed-Solomon type.

6. The decoding circuit of claim 2, wherein the third decoder comprises a set of registers storing a periodically-updated metric, and control means capable of forcing the content of the registers to a determined value according to the values of the signal provided by the first decoding system.

7. The decoding circuit of claim 6, wherein the control means detect the correct multiplets of the first signal and control the positioning of the registers for each sequence of n consecutive bits belonging to correct multiplets.

8. The decoding circuit of claim 3, wherein the third decoder comprises an encoder coupled to the interleave device and a multiplexer which respectively receives on first and second inputs the signal provided by the delay device and the signal provided by the encoder and provides a signal to a fifth decoder, the multiplexer being controlled by a control device acting according to the validity of the signal supplying the encoder.