Patent Application
20130101056
Example embodiments relate generally to integrated circuits for signal transfer, and more particularly to a receiver circuit and a system including a p-type sense amplifier.
Receiver circuits are implemented, in general, with an n-type sense amplifier that senses an input signal using n-channel metal oxide semiconductor (NMOS) transistors. The sensitivity of the n-type sense amplifier may be degraded depending on the pattern of the input signal. Furthermore the n-type sense amplifier may not sense the input signal at all in the worst a worst case.
Some example embodiments provide a receiver circuit for enhancing sensitivity to an input signal that swings within a relatively narrow range near a ground voltage, for example, under 1V.
Some example embodiments provide a system including a transmitter circuit for transferring an input signal that swings within a relatively narrow range near a ground voltage and a receiver circuit for sensing the input signal with enhanced sensitivity.
According to example embodiments, a receiver circuit includes a first p-channel metal oxide semiconductor (PMOS) transistor, an input circuit and an amplifier. The first PMOS transistor applies a power supply voltage to a power node in response to a clock signal. The input circuit is coupled to the power node to receive the power supply voltage, and the input circuit includes a plurality of PMOS transistors configured to generate a first sensing signal in response to an input signal and configured to generate a second sensing signal in response to at least one reference signal. The amplifier is configured to amplify the first sensing signal and the second sensing signal and to generate a first output signal representing a first of two binary values, and to generate a second output signal representing a second of the two binary values opposite to the first binary values.
According to example embodiments, a system includes a transmitter circuit including a transmission driver configured to drive a first node in response to a pull up signal and a pull down signal, and a receiver circuit configured to receive an input signal at a terminal that is coupled to the first node through a signal line. The receiver circuit includes a switching p-channel metal oxide semiconductor (PMOS) transistor configured to apply a power supply voltage to a power node in response to a clock signal, an input circuit coupled to the power node to, and configured to receive the power supply voltage, the input circuit including a plurality of PMOS transistors configured to generate a first sensing signal and a second sensing signal in response to the input signal and at least one reference signal, the first sensing signal corresponding to the input signal, the second sensing signal corresponding to the at least one reference signal, and an amplifier configured to amplify the first sensing signal and the second sensing signal, and to generate a first output signal and a second output signal opposite to the first output signal.
According to example embodiments, a semiconductor device includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first amplifier. The first PMOS transistor is configured to apply a power supply voltage to a first node in response to a first clock signal. The second PMOS transistor is coupled to the first node and is configured to generate a first sensing signal at a second node in response to an input signal. The third PMOS transistor is coupled to the first node and is configured to generate a second sensing signal at a third node in response to a first reference signal. The first amplifier is configured to amplify the first and second sensing signals, and configured to generate first and second output signals in response to the first and second sensing signals, respectively. The first output signal has a voltage representing a first binary values and the second output signal has a voltage representing a second binary values, opposite of the first binary values.
Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Unless indicated otherwise, these terms are used to distinguish one element, component, region, layer and/or section from another. Thus, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms such as “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be noted that in some alternative implementations, the functions/acts noted in the blocks may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to
The switching circuit 110 may include a switching p-channel metal oxide semiconductor (PMOS) transistor PMS. The switching PMOS transistor PMS applies a power supply voltage VDDQ to a power node NP in response to a clock signal CLK. The switching PMOS transistor PMS is turned off during a first half-cycle corresponding to logic high level of the clock signal CLK to float the power node NP. The switching PMOS transistor PMS is turned on during a second half-cycle corresponding to logic low level of the clock signal CLK to apply the power supply voltage VDDQ to the power node NP. Accordingly the p-type sense amplifier 100 may repeat the sensing operation during the first half-cycle and the floating operation during the second half-cycle.
The input circuit 130 is coupled to the power node NP to receive the power supply voltage VDDQ. The input circuit 130 includes a plurality of PMOS transistors PMI and PMR that generate a first sensing signal DI and a second sensing signal DIB in response to an input signal DIN and at least one reference voltage VREF, such that the first sensing signal DI corresponds to the input signal DIN and the second sensing signal DIB corresponds to the at least one reference voltage VREF.
The amplifier 150 amplifies the first sensing signal DI and the second sensing signal DIB to generate a first output signal Q and a second output signal QB. The first output signal Q may have a first of two binary values (i.e., a logic high level and a logic low level) and the second output signal QB may have a second of two binary values opposite to the first binary values.
The receiver circuit RX may further include a ground termination circuit 200 coupled between a ground voltage VSSQ and a reception node NR receiving the input signal DIN. The ground termination circuit 200 may include at least one resistor Rt. For example, the input signal DIN may swing between a low voltage level VOL (Hereinafter, or VIL) and a high voltage level VOH (Hereinafter, or VIH), as will be described with reference to
In some example embodiments, the input circuit 130 may generate the second sensing signal DIB based on the one reference voltage VREF as illustrated in
For example, when the one reference voltage VREF is used, the input circuit 130 may include an input PMOS transistor PMI and a reference PMOS transistor PMR.
The input PMOS transistor PMI is coupled between the power node NP and a first node N1 generating the first sensing signal DI, and a gate of the input PMOS transistor PMI receives the input signal DIN. The reference PMOS transistor PMR is coupled between the power node NP and a second node N2 generating the second sensing signal DIB, and a gate of the reference PMOS transistor PMR receives the reference voltage VREF. The reference voltage VREF may have an average voltage level VA of the low voltage level VOL and the high voltage level VOH of the input signal DIN.
Referring to
The transmitter circuit TX includes a transmission driver 350 that drives a transmission node NT in response to a pull up signal PU and a pull down signal PD. The transmitter circuit TX may further include a pre-driver (PREDR) 310 that outputs the pull up signal PU and the pull down signal PD based on a transmission signal DT. The pull up signal PD and the pull down signal PD are signals transitioning complementarily between a logic high level and a logic low level.
The receiver circuit RX receives an input signal DIN at a reception node NR that is coupled to the transmission node NT through the transmission line TL. As described with reference to
As illustrated in
The conventional transmission driver includes a PMOS transistor as a pull up driver and an NMOS transistor as a pull down driver. The hole mobility, that is, the carrier mobility of the PMOS transistor is smaller than the electron mobility, that is, the carrier mobility of the NMOS transistor, the PMOS transistor has the lower operation speed and the larger occupation size than the NMOS transistor.
Accordingly, by implementing the NMOS transistor NMU as the pull up driver of the transmission driver 350 as illustrated in
Referring to
Ipu=k1*(VDDQ−VOH)r1=>k1*(Vth)r1 Expression 1
The pull up current Ipu is increased as the high voltage level VOH at the reception node NR is increased and the pull up current Ipu reaches k1*(Vth)r1. The high voltage level VOH of the input signal DIN may be determined as Ipu*Rt depending on the pull up current Ipu and the termination resistor Rt. The high voltage level VOH may be increased by increasing at least one of the pull up current Ipu and the termination resistor Rt. The amount of the pull up current Ipu and the resistance value of the termination resistor Rt may be determined properly considering the integrity characteristic of the signals transferred through the transmission line TL. The amount of the pull up current Ipu may be changed according to the variations of the manufacturing process, the operational voltage and the operational temperature, and the amount of the pull up current Ipu may be determined by adjusting the width of the pull up PMOS transistor NMU.
Referring to
The termination current Irt flows through the termination resistor Rt to the ground voltage VSSQ and at the same time the pull down currents Ipd flows through the pull down NMOS transistor NMD to the ground voltage VSSQ when the pull down NMOS transistor is turned on. As a result, the voltage at the reception node NR, that is, the low voltage level VOL reaches the ground voltage VSSQ. The pull down current Ipd may be determined depending on VOL−VSSQ as Expression 2, where k2 and r2 are values determined based on the characteristics of the pull down NMOS transistor NMD.
Ipd=k2*(VOL−VSSQ)r2=>0 Expression 2
The pull down NMOS transistor NMD is turned off when the low voltage level is decreased below the threshold voltage of the pull down NMOS transistor NMD. Even though the pull down current Ipd becomes zero at the low voltage level VOL higher than the ground voltage VSSQ, the low voltage level VOL reaches the ground voltage VSSQ (e.g., 0V) ultimately due to the termination current Irt.
For example, the reference voltage VREF may have the average voltage level VA of the ultimate high voltage level VOL and the ultimate low voltage level VOL.
Referring to
The latch circuit 153 is coupled between the power supply voltage VDDQ and a ground node NG. The latch circuit 153 includes a latch node NQ and an inversion latch node NQB generating the first output signal Q and the second output signal QB, respectively. The latch circuit 153 may be implemented with two inverters including two PMOS transistors PM3 and PM4 and two NMOS transistors NM3 and NM4, where the inputs and outputs of the inverters are cross-coupled.
The switching circuit 154 may include a switching NMOS transistor NMS. The switching NMOS transistor NMS applies the ground voltage VSSQ to the ground node NG in response to an inverted clock signal CLKB. The switching NMOS transistor NMS is turned off during the first half-cycle corresponding to logic low level of the inverted clock signal CLKB to float the ground node NG. The switching NMOS transistor NMS is turned on during the second half-cycle corresponding to logic high level of the inverted clock signal CLKB to apply the ground voltage VSSQ to the ground node NG. Accordingly the receiver circuit RX may repeat the sensing operation during the first half-cycle and the floating operation during the second half-cycle.
The pull down circuit 151 may include a first NMOS transistor NM1 and a second NMOS transistor NM2. The first NMOS transistor NM1 is coupled between the ground voltage VSSQ and the first node N1 receiving the first sensing signal DI and a gate of the first NMOS transistor NM1 receives the clock signal CLK. The second NMOS transistor NM2 is coupled between the ground voltage VSSQ and the second node N2 receiving the second sensing signal DIB and a gate of the second NMOS transistor NM2 receives the clock signal CLK.
The voltage-current conversion circuit 152 may include a first PMOS transistor PM1 and a second PMOS transistor PM2. The first PMOS transistor PM1 is coupled between the power supply voltage VDDQ and the latch node NQ, and a gate of the first PMOS transistor PM1 receives the first sensing signal DI. The second PMOS transistor PM2 is coupled between the power supply voltage VDDQ and the inversion latch node NQB, and a gate of the second PMOS transistor PM2 receives the second sensing signal DIB. The voltage-current conversion circuit 152 applies the currents corresponding to the first and second sensing signals DI and DIB to the latch node NQ and the inversion latch node NQB, respectively.
Referring to
The post-amplifier 170 may amplify the first output signal Q and the second output signal QB to generate a third output signal OUT that swings fully between the power supply voltage VDDQ and the ground voltage VSSQ. As the frequency of the clock signal CLK is increased, the first and second output signals Q and QB may not swing fully as illustrated in
The post-amplifier 170 may include a driving circuit 171, a latch circuit 172 and an output circuit 173. The driving circuit 171 may include transistors NM1, NM2, PM1 and PM2 and a MOS capacitor MC that are coupled as illustrated in
Referring
Referring to
The latch circuit 156 is coupled between the first node N1 receiving the first sensing signal DI, the second node N2 receiving the second sensing signal DIB and the ground voltage VSSQ. The latch circuit 156 may include a latch node Q and an inversion latch node QB generating the first output signal Q and the second output signal QB, respectively. The latch circuit 153 includes a latch node NQ and an inversion latch node NQB generating the first output signal Q and the second output signal QB, respectively. The latch circuit 156 may be implemented with two inverters including two PMOS transistors PM1 and PM2 and two NMOS transistors NM1 and NM2, where the inputs and outputs of the inverters are cross-coupled.
The pull down circuit 157 may include a first NMOS transistor NM3 and a second NMOS transistor NM4. The first NMOS transistor NM3 is coupled between the ground voltage VSSQ and the latch node Q, and a gate of the first NMOS transistor NM3 receives the clock signal CLK. The second NMOS transistor NM4 is coupled between the ground voltage VSSQ and the inversion latch node QB, and a gate of the second NMOS transistor NM4 receives the clock signal CLK.
Referring to
The input circuit 130a is coupled to the power node NP to receive a power. The input circuit 130a includes a plurality of PMOS transistors PMI1, PMR1, PMI2 and PMR2 that generate a first sensing signal DI and a second sensing signal DIB in response to an input signal DIN and a plurality of reference voltages VREF1 and VREF2, such that the first sensing signal DI corresponds to the input signal DIN and the second sensing signal DIB corresponds to the reference voltages VREF1 and VREF2.
The amplifier 150 amplifies the first sensing signal DI and the second sensing signal DIB to generate a first output signal Q and a second output signal QB.
As described above, a ground termination circuit may be coupled between a ground voltage VSSQ and a reception node NR receiving the input signal DIN. In this case, the input signal DIN swings between the low voltage level VOL and the high voltage level VOH, as described with reference to
In case that the two reference voltages VREF1 and VREF2 are used, the input circuit 130a may include a first input PMOS transistor PMI1, a first reference PMOS transistor PMR1, a second input PMOS transistor PMI2 and a second reference PMOS transistor PMR2.
The first input PMOS transistor PMI1 is coupled between the power node NP and a first node N1 generating the first sensing signal DI, and a gate of the first input PMOS transistor PMI1 receives the input signal DIN. The first reference PMOS transistor PMR1 is coupled between the power node NP and a second node N2 generating the second sensing signal DIB, and a gate of the first reference PMOS transistor PMR1 receives the first reference voltage VREF1. The second input PMOS transistor PMI2 is coupled between the power node NP and the first node N1, and a gate of the second input PMOS transistor PMI2 receives the input signal DIN. The second reference PMOS transistor PMR2 is coupled between the power node NP and the second node N2, and a gate of the second reference PMOS transistor PMR2 receives the second reference voltage VREF2.
For example, the first reference voltage VREF1 has a voltage level higher than an average voltage level VA of the low voltage level VOL and the high voltage level VOH of the input signal DIN, and the second reference voltage VREF2 has a voltage level lower than the average voltage level VA. In one example embodiment, the first reference voltage VREF1 may have the high voltage level VOH of the input signal DIN, and the second reference voltage VREF2 may have the low voltage level VOL of the input signal DIN.
Referring
For example, the first reference voltage VREF1 may have the high voltage level VOH of the input signal DIN and the second reference voltage VREF2 may have the low voltage level VOL of the input signal DIN, as illustrated in
In this case, when the input signal DIN has the low voltage level VOL, the current passing through the second input PMOS transistor PMI2 is equal to the current passing through the second reference PMOS transistor PMR2 because the voltage levels of the input signal DIN and the second reference voltage VREF2 are the same. As a result, the input circuit 130a may generate the first sensing signal DI and the second sensing signal DIB based on the input signal DIN applied to the first input PMOS transistor PMI1 and the first reference voltage VREF1 applied to the first reference PMOS transistor PMR1, when the input signal DIN has the low voltage level VOL.
When the input signal DIN has the high voltage level VOH, the current passing through the first input PMOS transistor PMI1 is equal to the current passing through the first reference PMOS transistor PMR1 because the voltage levels of the input signal DIN and the first reference voltage VREF1 are the same. As a result, the input circuit 130a may generate the first sensing signal DI and the second sensing signal DIB based on the input signal DIN applied to the second input PMOS transistor PMI2 and the second reference voltage VREF2 applied to the second reference PMOS transistor PMR2, when the input signal DIN has the low high level VOH.
The p-type sense amplifier 100a may be floated during the first half-cycle corresponding to logic high level of the clock signal CLK and may perform the sensing operation during the second half-cycle corresponding to logic low level of the clock signal CLK. The first and second sensing signals DI and DIB may be provided as the voltage signals to the voltage-current conversion circuit 152 and voltage levels of the first and second output signals Q and QB may be formed by the output currents from the voltage-current conversion circuit 152. As described above, the first and second output signals Q and QB may not swing fully between the power supply voltage VDDQ and the ground voltage VSSQ, and the post-amplifier 170 may further amplify the first and second output signals Q and QB, through the node voltages O1 and O2, to provide the third output signal OUT that swings fully between the power supply voltage VDDQ and the ground voltage VSSQ.
A sensing margin SM, when the one reference voltage VREF having the average voltage level VA of the high voltage level VOH and the low voltage level VOL of the input signal is used to sensing the input signal, is illustrated in the upper portion of
Sensing margins SM1 and SM2, when the first reference voltage VREF1 having the high voltage level VOH higher than the average voltage level VA and the second reference voltage VREF2 having the low voltage level VOL lower than the average voltage level VA are used to sensing the input signal, are illustrated in the bottom portion of
Referring to
The first pre-driver 311 in the first device DEV1 outputs a pull up signal PU1 and a pull down signal PD1 corresponding to a first transmission signal DT1, and the first transmission driver 351 in the first device DEV1 drives the first transmission line TL1 in response to the pull up signal PU1 and the pull down signal PD1. The second p-type sense amplifier 102 in the second device DEV2 senses a first input signal DIN1 transferred through the first transmission line TL1 to generate output signals Q1 and QB1.
The second pre-driver 312 in the second device DEV2 outputs a pull up signal PU2 and a pull down signal PD2 corresponding to a second transmission signal DT2, and the second transmission driver 352 in the second device DEV2 drives the second transmission line TL2 in response to the pull up signal PU2 and the pull down signal PD2. The first p-type sense amplifier 101 in the first device DEV2 senses a second input signal DIN2 transferred through the second transmission line TL2 to generate output signals Q2 and QB2.
As such, the system 11 may perform bi-lateral communication using the two uni-lateral transmission lines TL1 and TL2. For example, the NMOS transistors NMU1 and NMU2 may be used as pull up drivers to increase the integration rate and the operational speed of the circuits, and the p-type sense amplifiers 101 and 102 may be used to efficiently receive the input signals DIN1 and DIN2 that swing narrowly near the ground voltage VSSQ (e.g., under 1V).
Referring to
Compared with the ground termination circuits 201 and 202 in
The first pre-driver 311 in the first device DEV1 outputs a pull up signal PU1 and a pull down signal PD1 corresponding to a first transmission signal DT1, and the first transmission driver 351 in the first device DEV1 drives the first transmission line TL1 in response to the pull up signal PU1 and the pull down signal PD1. The second p-type sense amplifier 102 in the second device DEV2 senses a first input signal DIN1 transferred through the first transmission line TL1 to generate output signals Q1 and QB1.
The second pre-driver 312 in the second device DEV2 outputs a pull up signal PU2 and a pull down signal PD2 corresponding to a second transmission signal DT2, and the second transmission driver 352 in the second device DEV2 drives the second transmission line TL2 in response to the pull up signal PU2 and the pull down signal PD2. The first p-type sense amplifier 101 in the first device DEV2 senses a second input signal DIN2 transferred through the second transmission line TL2 to generate output signals Q2 and QB2.
When the signal is transferred from the first device DEV1 to the second device DEV2, the first transmitter circuit TX1 and the second receiver circuit RX2 are enabled and the second transmitter circuit TX2 and the first receiver circuit RX1 are disabled. In this case, the first ground termination circuit 203 is disabled in response to the deactivated first termination enable signal TEN1 and the second ground termination circuit 204 is enabled in response to the activated second termination enable signal TEN2.
When the signal is transferred from the second device DEV2 to the first device DEV1, the second transmitter circuit TX2 and the first receiver circuit RX1 are enabled and the first transmitter circuit TX1 and the second receiver circuit RX2 are disabled. In this case, the second ground termination circuit 204 is disabled in response to the deactivated second termination enable signal TEN2 and the first ground termination circuit 203 is enabled in response to the activated first termination enable signal TEN1.
As such, the system 12 may perform bi-lateral communication using the one bi-lateral transmission line TL. According to example embodiments, the NMOS transistors NMU1 and NMU2 may be used as pull up drivers to increase the integration rate and the operational speed of the circuits, and the p-type sense amplifiers 101 and 102 may be used to efficiently receive the input signals DIN1 and DIN2 that swing narrowly near the ground voltage VSSQ.
Referring to
The pre-driver 311 in the first transmitter circuit TX1 outputs a pull up signal PU1 and a pull down signal PD1 corresponding to a first transmission signal DT1, and the first transmission driver 351 in the first transmitter circuit TX1 drives the first transmission line TL1 in response to the pull up signal PU1 and the pull down signal PD1. The p-type sense amplifier 101 in the first receiver circuit RX1 senses a first input signal DIN1 transferred through the first transmission line TL1 to generate output signals Q1 and QB1. In the same way, the second transmitter circuit TX2 drives the second transmission line TL2 based on a second transmission signal DT2 and the second receiver circuit RX2 receives a second input signal DIN2 through the second transmission line TL2 to generate output signals Q2 and QB2. The third transmitter circuit TX3 drives the third transmission line TL3 based on a third transmission signal DT3 and the third receiver circuit RX3 receives a third input signal DIN3 through the third transmission line TL3 to generate output signals Q3 and QB3.
Referring to
As illustrated in
The p-type sense amplifier 100a may have the configuration as illustrated in
Referring to
As illustrated in
The first device DEV1 may be formed through the common manufacturing process and may be integrated in one chip. In this case, the elements 321, 322, 361 and 362 for providing the reference voltages VREF1 and VREF2 may have the same operational characteristics as the elements 310 and 350 for transferring the signal. Accordingly the reference voltages VREF1 and VREF2 may reflect exactly the high voltage level VOH and the low voltage level VOL of the input signal DIN because the variations due to the manufacturing process, the operational voltage and the operational temperature are applied commonly to the reference voltage transfer and the signal transfer.
The p-type sense amplifier 100a may have the configuration as illustrated in
Referring to
The first reference pre-driver 321 may be configured to output the pull up signal PU1 fixed at the first voltage V1 and the pull down signal PD1 fixed at the second voltage V2. In this case, the pull up NMOS transistor NMU of the first reference driver 361 may be always turned on and the pull down NMOS transistor NMD of the first reference driver 361 may be always turned off. As a result, the first reference voltage VREF1 received by the second device DEV2 through the first reference voltage transmission line RTL1 may have the high voltage level VOH of the input signal DIN.
The second reference pre-driver 322 may be configured to output the pull up signal PU2 fixed at the second voltage V2 and the pull down signal PD2 fixed at the first voltage V1. In this case, the pull up NMOS transistor NMU of the second reference driver 362 may be always turned off and the pull down NMOS transistor NMD of the second reference driver 362 may be always turned on. As a result, the second reference voltage VREF2 received by the second device DEV2 through the second reference voltage transmission line RTL2 may have the low voltage level VOL of the input signal DIN.
Referring to
The system 16 may perform the DDR transfer such that two bits may be transferred in a single cycle of the clock signal CLK. The first device DEV1 operating as the transmitter may have the configuration to perform the DDR transfer. For example, the pre-driver 310 may generate the pull up signal PD and the pull down signal PD such that one even-numbered bit and one odd-numbered bit in the transmission signal may be transferred in the single cycle of the clock signal CLK.
The clock signal CLK is applied to the gate of the switching PMOS transistor PMS1 in the first p-type sense amplifier 111, and the inverted clock signal CLKB is applied to the gate of the switching PMOS transistor PMS2 in the second p-type sense amplifier 112. The second p-type sense amplifier 112 may perform the sensing operation during the first half-cycle corresponding to the logic high level of the clock signal CLK and may be floated from the power supply voltage during the second half-cycle corresponding to the logic low level of the clock signal CLK. In contrast, the first p-type sense amplifier 111 may perform the sensing operation during the second half-cycle corresponding to the logic low level of the clock signal CLK and may be floated from the power supply voltage during the first half-cycle corresponding to the logic low high of the clock signal CLK. As a result, the first p-type sense amplifier 111 may sense the even-numbered bits in the input signal DIN to generate the even-numbered output signals QE and QEB and the second p-type sense amplifier 112 may sense the odd-numbered bits in the input signal DIN to generate the odd-numbered output signals QO and QOB.
As such, the frequency of the clock signal CLK may be increased by supporting the DDR transfer using the two p-type sense amplifiers 111 and 112 that operate complementarily, and the operational speed of the system 16 may be increased.
The devices of the embodiments described herein (e.g., DEV1 and DEV2) may each be formed as a single semiconductor chip, with the p-type sense amplifiers of the receivers RX of the devices connected to respective external transmission lines via terminals of the semiconductor chip (e.g., chip pads). Alternatively, devices described herein may be formed from multiple chips. For example, one or more of the devices DEV1 and DEV2 may be formed of multiple chips within a semiconductor package (e.g., stacked chips in a multi-chip package) with external terminals (e.g., solder bumps) of the semiconductor package connecting the p-type sense amplifiers to external transmission lines.
Referring to
For example, the semiconductor memory chip 840 and the controller chip 820 may be electrically connected to each other through the input-output bumps 830 the controller chip 820 and the base substrate 810 may be electrically connected to each other using wires 860. Bumps 811 for electrical connection to an external device may be formed under the bottom surface of the base substrate 810.
Referring to
In the embodiment of
Referring to
The SOC 1010 may be an application processor (AP) SOC including an interconnect device INT and a plurality of intellectual properties or functional blocks coupled to the interconnect device INT. For example, the intellectual properties may include a memory controller MC, a central processing unit CPU, a display controller DIS, a file system block FSYS, a graphic processing unit GPU, an image signal processor ISP, a multi-format codec block MFC, etc.
The memory controller MC and the memory device 1020 may perform the signal transfer according to example embodiments as described with reference to
The SOC 1010 may communicate with the memory device 1020, the storage device 1030, the input/output device 1040 and the image sensor 1060 via a bus such as an address bus, a control bus, and/or a data bus. In some embodiments, the SOC 1010 may be coupled to an extended bus, such as a peripheral component interconnection (PCI) bus. Devices described herein with respect to other embodiments (e.g., DEV1 and DEV2) may correspond to one or more of the memory device 1020, the storage device 1030, the input/output device 1040 and the image sensor 1060. One or more receivers RX of the embodiments described herein may be formed in one or more of the memory device 1020, the storage device 1030, the input/output device 1040 and the image sensor 1060. One or more transmitters TX of the embodiments described herein may be formed in one or more of the memory device 1020, the storage device 1030, the input/output device 1040 and the image sensor 1060. Transmission lines may connect such receivers RX and transmitters TX. Alternatively, the devices described herein (e.g., DEV1 and DEV2) may correspond to one or more of the functional blocks of the SOC 1010. Transmission lines connecting respective receivers RX and transmitters TX may be thus formed as part of chip SOC 1010, or on-chip to the SOC 1010. The details of such connections and respective operations have been previously described and need not be repeated here.
The memory device 1020 may store data for operating the computing system 2000. For example, as with memory devices of other embodiments described herein, the memory device 1020 may be implemented with a dynamic random access memory (DRAM) device, a mobile DRAM device, a static random access memory (SRAM) device, a phase random access memory (PRAM) device, a ferroelectric random access memory (FRAM) device, a resistive random access memory (RRAM) device, and/or a magnetic random access memory (MRAM) device. The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input/output device 1040 may include an input device (e.g., a keyboard, a keypad, a mouse, etc.) and an output device (e.g., a printer, a display device, etc.). The power supply 1050 supplies operation voltages for the computing system 2000.
The image sensor 1060 may communicate with the SOC 1010 via the buses or other communication links. As described above, the image sensor 1060 may be integrated with the SOC 1010 in one chip, or the image sensor 1060 and the SOC 1010 may be implemented as separate chips.
The components in the electronic device 1000 may be packaged in various forms, such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), or wafer-level processed stack package (WSP).
The electronic device 1000 may be any computing system including at least one SOC. For example, the electronic device 1000 may include a digital camera, a mobile phone, a smart phone, a portable multimedia player (PMP), a personal digital assistant (PDA), etc.
Referring to
A CSI host 1112 of the SOC 1110 may perform a serial communication with a CSI device 1141 of the image sensor 1140 via a camera serial interface (CSI). In some embodiments, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER). A DSI host 1111 of the SOC 1110 may perform a serial communication with a DSI device 1151 of the display device 1150 via a display serial interface (DSI).
In some example embodiments, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). The electronic device 1100 may further include a radio frequency (RF) chip 1160 performing a communication with the SOC 1110. A physical layer (PHY) 1113 of the electronic device 1100 and a physical layer (PHY) 1161 of the RF chip 1160 may perform data communications based on a MIPI DigRF. The SOC 1110 may further include a DigRF MASTER 1114 that controls the data communications of the PHY 1161.
The electronic device 1100 may further include a global positioning system (GPS) 1120, a storage 1170, a MIC 1180, a DRAM device 1185, and a speaker 1190. In addition, the electronic device 1100 may perform communications using an ultra wideband (UWB) 1120, a wireless local area network (WLAN) 1220, a worldwide interoperability for microwave access (WIMAX) 1130, etc. However, the structure and the interface of the electric device 1100 are not limited thereto.
The example embodiments described above may be applied to arbitrary devices and systems that require the signal transfer. Particularly the example embodiments may be efficiently applied to mobile devices and systems that require a smaller size, a higher operational speed and lower power consumption.
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2012-0105697 | Sep 2012 | KR | national |
This U.S. non-provisional application claims priority under 35 USC §119 to U.S. Provisional Application No. 61/551,072 filed on Oct. 25, 2011 in the USPTO, and Korean Patent Application No. 10-2012-0105697, filed on Sep. 24, 2012 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61551072 | Oct 2011 | US |
