BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a circuit diagram showing a receiver circuit according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram showing an internal circuit of the amplifier of the receiver circuit;
FIG. 3 is a graph showing the size dependency of the threshold voltage variation of MOSFETs;
FIGS. 4A to 4D are graphs showing the frequency characteristic and pulse reply characteristic of receiver circuits according to a related art and the present invention;
FIGS. 5A and 5B are graphs showing an output voltage waveform of the receiver circuit according to the first embodiment of the present invention from after power on to stable operation;
FIG. 6 a circuit diagram showing the receiver circuit according to a second embodiment of the present invention;
FIG. 7 is a circuit diagram showing a receiver circuit according to a related art;
FIG. 8 is a circuit diagram showing a receiver circuit disclosed in Japanese Unexamined Patent Application Publication No. 2002-176324;
FIG. 9 is a graph showing an output voltage waveform of the receiver circuit disclosed in Japanese Unexamined Patent Application Publication No. 2002-176324 from after power on to stable operation; and
FIG. 10 is a circuit diagram showing a receiver circuit disclosed in Japanese Unexamined Patent Application Publication No. 2004-153012.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
First Embodiment
Firstly, the structure of a receiver circuit according to a first embodiment of the present invention is explained with reference to FIG. 1. As shown in FIG. 1, this receiver circuit includes a photodiode PD, an amplifier A1 for converting a current from the photodiode PD into a voltage, an amplifier A2 for adjusting an offset voltage of the amplifier A1 and a control unit for controlling on/off of an offset voltage adjustment function of the amplifier. The control unit includes a first MOSFET M1 connected between a noninverting input terminal of the amplifier A2 which is supplied with a reference voltage and a noninverting input terminal of the amplifier A1, a second MOSFET M12 connected between an output of the amplifier A2 and the noninverting input terminal of the amplifier A1, and a control circuit C1 for controlling on/off of the MOSFETs M11 and M12. Furthermore, a feedback resister “r” is provided in the amplifier A1.
The anode of the photodiode PD is connected to ground. The cathode of the photodiode PD is connected to the inverting input terminal of the amplifier A1, the inverting input terminal of the amplifier A2 and one end of the feedback resister “r”. The other end of the feedback resister “r” is connected to the output terminal of the amplifier A1. The MOSFET M11 is connected to the noninverting input terminal of the amplifier A1, the noninverting input terminal of the amplifier A2, a reference voltage Vc and the control circuit C1. The noninverting input terminal of the amplifier A2 is connected to the reference voltage Vc. The MOSFET M12 is connected to the noninverting input terminal of the amplifier A1, the output terminal of the amplifier A2 and the control circuit C1. In the following explanation, it is assumed that a voltage of the output terminal of the amplifier A2 is x and a voltage of the noninverting input terminal of the amplifier A1 is y.
Next, the operation in the receiver circuit according to the first embodiment of the present invention is explained with reference to FIGS. 1 to 5. As shown in FIG. 1, the voltage Vc is supplied to the noninverting input terminal of the amplifier A2 as a reference voltage. Inside of the amplifier A2 is formed of a differential amplifier circuit “a” and a buffer b as shown in FIG. 2. The differential amplifier circuit “a” includes two N-channel MOSFETs (MN1 and MN2), forming a differential pair, two P-channel MOSFETs (MP1 and MP2), forming an active load provided between the differential pair and a power supply potential VCC and a current source CS1 provided between the differential pair and a ground potential GND. Since a gain to a differential input voltage of this differential amplifier circuit “a” is high, for example, 60 to 80 dB and an output of the amplifier A2 is stabilized at a limited voltage (near Vc), a voltage of the inverting input terminals of the amplifiers A1 and A2 will be Vc+ΔV2 when assuming that an input offset voltage variation of the amplifier A2 is ΔV2. Here, the input offset voltage variation ΔV2 is corresponding to the input offset voltage variation generated when the amplifier A2 is formed from a negative feedback circuit (voltage follower etc.) with one time gain.
Inside of the amplifier A1 is formed from the differential amplifier circuit “a” and the buffer “b” as shown in FIG. 2. The voltage variation ΔV1 corresponding to the input offset voltage generated when the amplifier A1 is formed from a negative feedback circuit (voltage follower etc.) with one time gain is generated between the input terminals of the amplifier A1. As mentioned above, since the voltage of the inverting input terminal of the amplifier A1 is Vc+ΔV2 by the operation of the amplifier A2, the noninverting input terminal of the amplifier A1 operates to be Vc+ΔV2−ΔV1 due to a voltage for the input offset voltage variation ΔV1 of the amplifier A1. Therefore, the offset voltage variation ΔV1 has no effect on the output voltage Vout. Thus, when a current of the photodiode PD is Ip, the output voltage Vout is the sum of the product of the photodiode current Ip and the feedback resister “r” and the voltage Vc+ΔV2 of the inverting input terminal of the amplifier A1, and is expressed as follows.
Vout=Ip×r+Vc+ΔV2
Inside of the amplifier A1, N-channel MOSFETs (MN1, MN2) and P-channel MOSFETs (MP1, MP2) with either or both of the gate length L and the gate width W being small is used for the differential amplifier circuit “a” as shown in FIG. 2. Accordingly, from the relation shown in the abovementioned FIG. 3, current-voltage conversion of the photodiode current Ip can be carried out in wideband from a direct current to several 100 MHz using the wideband characteristic of the differential amplifier circuit “a”.
Since the amplifier A2 does not need the wideband characteristic but requires the low offset voltage variation characteristic on the other hand, MOSFETs with either or both of the gate length L and the gate width W being larger than the MOSFETs used for the differential amplifier circuit of the amplifier A1 is used for the N-channel MOSFETs (MN1, MN2) and P-channel MOSFETs (MP1, MP2) of the differential amplifier circuit “a” as shown in FIG. 2. Accordingly, from the relation shown in the abovementioned FIG. 3, the differential amplifier circuit where the input offset voltage variation ΔV2 becomes the minimum can be used.
Moreover, in addition to the receiver circuit of the related art shown in FIG. 8, the receiver circuit shown in FIG. 1 has switching MOSFETs for controlling the voltage of the noninverting input terminal of the amplifier A1 so that the output voltage Vout is stabilized near Ip×r+Vc+ΔV2 in a short time after power on and the control circuit C1 for controlling the gate voltage of the switching MOSFETs so as to control the state. By the switching MOSFETs (M11 and M12) and the control circuit C1, on/off of the offset adjustment function of the amplifier A2 is controlled. To be more specific, as shown in FIGS. 5A and 5B, in the period t1 immediately after power on, by the control circuit C1, the MOSFET M11 is made to be on-state or low resistance state, the MOSFET M12 is made to be off-state or high resistance state and the noninverting terminal of the amplifier A1 is made to be Vc voltage. By this, the offset adjustment function of the amplifier A2 is turned off. At this time, the output voltage Vout of the amplifier A1 can be expressed as follows.
Vout=r×Ip+Vc+ΔV1
Here, ΔV1 is an input offset voltage variation of the amplifier A1. Next, by making the MOSFET M11 to be off or high resistance state by the C1 circuit, with the amplification operation of the amplifiers A1 and A2 and the negative feedback operation as the whole circuit, the noninverting terminal of the amplifier A1 changes from Vc to Vc+ΔV2−ΔV1 in a period t3 through the transition period of a period t2, as shown in FIGS. 5A and 5B. At this time, the output voltage Vout of the amplifier A1 can be expressed as follows.
Vout=r×Ip+Vc+ΔV2
In FIGS. 5A and 5B, it is simplified to voltage ΔV2≅0. As shown in FIGS. 5A and 5B, the feature of the receiver circuit of this example shown in FIG. 1 is that the noninverting terminal of the amplifier A1 changes from Vc to Vc+ΔV2−ΔV1 with a small voltage change ΔV2−ΔV1 after power on of the receiver circuit. Therefore, Vout becomes neither excessive (near power supply voltage VCC) nor too small (near GND). Therefore, malfunction of the next stage circuit which inputs the output voltage Vout of the receiver circuit can be prevented.
In addition, the period t2 in which the potential state of each terminal of the receiver circuit changes from the period t1 to the period t3 shown in FIGS. 5A and 5B is determined by a RC time constant. The CR time constant is determined by a resistance component of the switching MOSFET M12 in on-state or low resistance state and a gate capacitance of the noninverting terminal input unit MOSFET of the amplifier A1. Here, a resistance may be connected between MOSFET M12 and the noninverting terminal of the amplifier A1 in series. A capacitance may be connected between GND and the noninverting terminal of the amplifier A1 in series.
The frequency characteristic of the receiver circuit according to the related art illustrated in FIG. 7 is shown in FIG. 4A. Furthermore, FIG. 4B shows an output voltage waveform for a photodiode current input in pulse form in the receiver circuit according to the related art. Note that in FIGS. 4A and 4B, the input offset voltage variation ΔV1 of the amplifier A1 for current-voltage conversion shown in FIG. 7 is 40 mV.
The frequency characteristic of the receiver circuit according to the present invention is shown in FIG. 4C. Moreover, FIG. 4D shows an output voltage waveform for a photodiode current input in pulse form in the receiver circuit according to the present invention. Note that in FIGS. 4C and 4D, the input offset voltage variation ΔV1 of the current-voltage conversion amplifier A1 shown in FIG. 1 is 40 mV and the input offset voltage variation ΔV2 of the offset voltage adjustment amplifier A2 is 4 mV.
As shown in FIGS. 4A and 4C, in the receiver circuit according to the present invention, the frequency characteristic where the voltage value after current-voltage conversion is −3 dB is the same as that of the receiver circuit according to the related art. On the other hand, as shown in FIGS. 4B and 4D, the offset voltage variation of the output voltage is reduced to 4 mV, which is 1/10 of the related art. The offset voltage variation 4 mV is equivalent to the input offset voltage variation of the offset voltage adjustment amplifier A2 shown in FIGS. 1 and 6. As shown in FIGS. 4A to 4D, the receiver circuit according to the present invention has realized both characteristics of the wideband current-voltage conversion and the low offset voltage variation.
In this way, by using two amplifiers for the receiver circuit, where one amplifier is to be a circuit for current-voltage conversion in wideband and another amplifier is to be a circuit of low offset voltage variation for correcting an offset voltage variation in the current-voltage conversion circuit, it is possible to realize a receiver circuit with wideband and low offset voltage variation.
To be more specific, both characteristics of the “wideband characteristic” and the “low offset voltage variation” can be realized by applying the optimal size of MOSFETs for each of the wideband current-voltage conversion circuit and the offset voltage correction circuit.
Moreover, since the output voltage Vout only makes a small voltage change ΔV2−ΔV1 after power on of the receiver circuit, the output voltage Vout becomes neither excessive (near VCC) nor too little (near GND) even in the intermediate period until the correction operation for the voltage ΔV1 is stabilized. Thus, malfunction in the next stage circuit in a pickup device can be suppressed.
Second Embodiment
Next, the structure of the receiver circuit according to a second embodiment is explained with reference to FIG. 6. Note that the structure of the receiver circuit according to the second embodiment of the present invention is that the control circuit C1 shown in FIG. 1 is illustrated specifically. Other components except the control circuit C1 are identical to the structure of the receiver circuit according to the first embodiment of the present invention and thus the explanation is omitted.
As shown in FIG. 6, the control circuit C1 includes a comparator A3, a resistance RC1, a resistance RC2, a 2-phase inverter I1 and a 3-phase inverter I2.
An inverting input terminal of the comparator A3 is connected to one end of the resistances RC1 and RC2. The other end of the resistance RC1 is connected to the power supply voltage VCC and the other end of the resistance RC2 is connected to ground, respectively. A noninverting input terminal of the comparator A3 is connected to a reference voltage VC2 and an output terminal of the comparator A3 is connected to input terminals of the 2-phase inverter I1 and the 3-phase inverter I2. An output terminal of the 2-phase inverter I1 is connected to a MOSFET M11 and an output terminal of the 3-phase inverter I2 is connected to a MOSFET M12, respectively.
Next, the operation in the receiver circuit according to the second embodiment of the present invention is explained. As shown in FIG. 6, the resistances RC1 and RC2 in the control circuit C1 divide the power supply voltage VCC and generate a voltage VA. The voltage VA is input into the inverting terminal of the comparator A3. A reference voltage VC generated inside an IC of the receiver circuit is input into the noninverting terminal of the comparator A3. The 2-phase inverter I1 and the 3-phase inverter I2 are connected to the output of the comparator A3. Thus, each output of the 2-phase inverter I1 and the 3-phase inverter I2 is input to each gate of the MOSFETs M11 and M12, respectively.
When the voltage VA input into the inverting input terminal of the comparator A3 is smaller than the reference voltage VC2, an output voltage of the comparator A3 becomes high-level, the MOSFET M11 is turned on and the MOSFET M12 is turned off. On the other hand, when the voltage VA is larger than the reference voltage VC2, the output voltage of the comparator A3 becomes low-level, the MOSFET M11 is turned off and the MOSFET M12 is turned on.
From the above operation, assuming that the period when the voltage VA shown in FIG. 6 is VA<VC2 is from the period t1 to t2 shown in FIGS. 5A and 5B and the period when VA is VA≧VC2 is the period t3 shown in FIGS. 5A and 5B, in the period from t1 to t2, the MOSFET M11 is on and the MOSFET M12 is off and in the period t3, the MOSFET M11 is off and the MOSFET M12 is on. Therefore, in the receiver circuit of this example shown in FIG. 6, as with the first embodiment, the offset adjustment function of the amplifier A2 is turned off in a predetermined period and turned on after the predetermined period. Thus, the receiver circuit according to this embodiment is able to supply the stable output voltage Vout to the next stage circuit.
It is apparent that the present invention is not limited to the above embodiments but it may be modified and changed without departing from the scope and spirit of the invention.
Patent Application
20080075473
