Receiver device

Abstract

A receiver device 1 comprises a gain control portion 40 which regulates a received signal by controlling the opening and closing of a switch 52 which bypasses a first amplifier 12 and providing variable control over the gain of a second amplifier 16, and which also switches the gain of the second amplifier 16 to compensate for gain fluctuations due to the opening and closing of the switch 12. This gain control portion 40 also comprises a digital logic circuit which can program a time offset between the open/closing period of the switch 52 and the switching period of the gain of the second amplifier 16.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from the description as set below with reference to the accompanying drawings, wherein:

FIG. 1 schematically shows an example of the configuration of a prior-art OFDM receiver device which provides an automatic gain control function;

FIG. 2A is illustrative of gain control which the gain control portion 40 performs by using the low-noise amplifier 12;

FIG. 2B is illustrative of gain control of the variable-gain amplifier 16 by the gain control portion 40;

FIG. 2C shows variations in the total gain of FIGS. 2A and 2B;

FIG. 3A shows gain variations when the incoming signal strength increases to exceed the threshold value L1 and the timing of the switching of the gain of the variable-gain amplifier is delayed slightly with respect to the timing of the bypassing of the low-noise filter;

FIG. 3B shows the total of the gain due to the low-noise amplifier and the gain of the variable-gain amplifier;

FIG. 4A shows gain variations when the incoming signal strength increases to exceed the threshold value L1 and the timing of the switching of the gain of the variable-gain amplifier is slightly faster than the timing of the bypassing of the low-noise amplifier;

FIG. 4B shows the total of the gain due to the low-noise amplifier and the gain of the variable-gain amplifier;

FIG. 5 schematically shows an example of the configuration of an OFDM receiver device in accordance with a first embodiment of the present invention;

FIG. 6A is a graph of variations in the incoming signal strength of the received signal;

FIG. 6B is a timing chart of the open/close control signal which the RF-SW switching portion generates;

FIG. 6C is a timing chart of the gain command signal which the V-AMP gain determination portion generates;

FIG. 6D is a graph of actual gain variations in the variable-gain amplifier which is controlled in accordance with FIG. 6C;

FIG. 6E is a timing chart of the open/close control signal having timing which has been adjusted by the timing adjustment portion;

FIG. 6F is a graph of variations in the total of the gain due to the low-noise amplifier and the gain of the variable-gain amplifier;

FIG. 7 is a flowchart of an example of the method of determining the set time offset T;

FIG. 8A is a graph of a gain command signal having a hysteresis characteristic, which is generated by the V-AMP gain determination portion 41;

FIG. 8B is a graph of an open/close control signal having a hysteresis characteristic, which is generated by the RF-SW switching portion 42;

FIG. 9 is a flowchart of a method of controlling the opening/closing of the radio-frequency signal switch 52 and the gain of the variable-gain amplifier 16, with a hysteresis characteristic;

FIG. 10 shows the spectrum of an OFDM signal which comprises a null carrier; and

FIG. 11 schematically shows an example of the configuration of an OFDM receiver device in accordance with a second embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described in detail below while referring to the attached figures. An example of the configuration of an OFDM receiver device in accordance with a first embodiment of the present invention is shown schematically in FIG. 5. Since the OFDM receiver device 1 shown in FIG. 5 has a configuration similar to that of the OFDM receiver device described previously with reference to FIG. 1, components which are the same or similar thereto are denoted by the same reference numbers and further description of the same functions is omitted.

As described previously with reference to FIG. 2A, when the incoming signal strength which the power detection portion 33 has estimated changes from a strength which is below the predetermined signal strength threshold value L1 to a high strength, the RF-SW switching portion 42 closes the radio-frequency signal switch 52 to make the received signal bypass the low-noise amplifier 12. When the incoming signal strength which the power detection portion 33 has estimated changes from a strength which is higher than the predetermined signal strength threshold value L1 to a low strength, the RF-SW switching portion 42 opens the radio-frequency signal switch 52 to halt the bypassing of the low-noise amplifier 12.

In addition, the V-AMP gain determination portion 41 exerts variable control over the gain of the variable-gain amplifier 16 in response to reception strength, in accordance with the gain lines GLL and GLH which reduce the gain as the incoming signal strength increases, as described previously with reference to FIG. 2B. While the incoming signal strength is weaker than the threshold value L1 and the low-noise amplifier 12 is not bypassed, the gain is determined by the gain line GLL which gives a comparatively low gain. While the incoming signal strength is greater than or equal to the threshold value L1 and the low-noise amplifier 12 is bypassed, the gain is determined by the gain line GLH which is the gain G1 greater than the gain line GLL. The gain width G1 is set to the same value as the gain of the low-noise amplifier 12.

To enable the V-AMP gain determination portion 41 to determine the gain of the variable-gain amplifier 16 in accordance with the above-described gain lines GLL and GLH, each gain which the variable-gain amplifier 16 ought to have for each incoming signal strength is written into a gain settings table in which gains are linked to the corresponding incoming signal strengths, and a gain settings table is created for each gain line and is stored in a memory portion 44. The V-AMP gain determination portion 41 reads out the gain corresponding to the incoming signal strength which the power detection portion 33 has estimated from this gain settings table, for use as the gain command value for the variable-gain amplifier 16.

Therefore, when the incoming signal strength which the power detection portion 33 has estimated changes from a strength which is lower than the predetermined signal strength threshold value L1 to a higher strength and the low-noise amplifier 12 is bypassed, the V-AMP gain determination portion 41 switches the gain line to be used in the determination of the gain of the variable-gain amplifier 16 from the comparatively low gain line GLL to the gain line GLH of the low-noise amplifier 12 which is the gain G1 higher, to compensate for gain fluctuations generated by the bypassing of the low-noise amplifier 12.

When the incoming signal strength which the power detection portion 33 has estimated changes from a strength which is higher than the predetermined signal strength threshold value L1 to a lower strength, the V-AMP gain determination portion 41 switches the gain line to be used in the gain determination from the comparatively high gain line GLH to the low gain line GLL which is G1 lower.

Returning to FIG. 5, the gain control portion 40 of this example of the configuration comprises a timing adjustment portion 43 which is formed of a digital logic circuit. This timing adjustment portion 43 inputs a gain command signal for the variable-gain amplifier 16 in digital format which was generated by the V-AMP gain determination portion 41 (hereinafter called simply “gain command signal”) and an open/close control signal for the radio-frequency signal switch 52 which was generated by the RF-SW switching portion 42 (hereinafter called simply “open/close control signal”).

The timing adjustment portion 43 outputs the gain command signal and the open/close control signal unchanged if there is no open/close control of the radio-frequency signal switch 52. But adjusts the time offset between the open/closing period of the radio-frequency signal switch 52 and the switching period of the gain of the variable-gain amplifier 16 to the setting of the time offset which was set previously (hereinafter called “set time offset”), by adjusting the time offset of the output timing of the open/close signal and the output timing of the open/close control signal if open/close control of the radio-frequency signal switch 52 has occurred.

The timing adjustment portion 43 could be configured as an digital logic circuit implemented by an FPGA, comprising a storage circuit which stores a number of cycles generated by a predetermined clock signal during the set time offset, a detection circuit which detects changes in the gain command signal or open/close control signal which are caused by the incoming signal strength crossing the predetermined threshold value L1, a counter circuit which starts to count the predetermined clock signal for the number of cycles stored in the storage circuit when this change in the signal are caused, and a delay circuit which causes a change in the open/close control signal when the counter circuit completes the count.

The description now turns to an example of how the timing adjustment portion 43 adjusts the time offset between the open/closing period of the radio-frequency signal switch 52 and the switching period of the gain of the variable-gain amplifier 16, with reference to FIGS. 6A to 6F. FIG. 6A is a graph of variations in the incoming signal strength of the received signal, FIG. 6B is a timing chart of the open/close control signal which the RF-SW switching portion 42 generates, FIG. 6C is a timing chart of the gain command signal which the V-AMP gain determination portion 41 generates, FIG. 6D is a graph of actual gain variations of the variable-gain amplifier 16 which is controlled in accordance with the signal shown in FIG. 6C, FIG. 6E is a timing chart of the open/close control signal which has had timing adjusted by the timing adjustment portion 43, and FIG. 6F is a graph of variations in the gain which is the total of the gain due to the low-noise amplifier 12 and the gain due to the variable-gain amplifier 16.

Consider a case in which the in coming signal strength exceeds the predetermined signal strength threshold value L1 for switching the bypassing of the low-noise amplifier 12 at a time t1, while the incoming signal strength is increasing, as shown in FIG. 6A. When that happens, the gain command value of the gain command signal is switched by the RF-SW switching portion 42 changing the open/close control signal from the state in which the radio-frequency signal switch 52 is open to that in which it is closed at the time t1, as shown in FIG. 6B, and the V-AMP gain determination portion 41 switching the gain line used in the gain determination from the comparatively low GLL to GLH, as shown in FIG. 6C.

Since the response speed of the variable-gain amplifier 16 is limited in practice, as described above, the gain of the variable-gain amplifier 16 changes comparatively gently between the time t1 and a time t3 in comparison with the gain command signal, as shown in FIG. 6D.

The timing adjustment portion 43 minimizes fluctuations in the gain which is the total of the gain due to the low-noise amplifier 12 and the gain of the variable-gain amplifier 16, which are generated in the vicinity of the switching time t1 as shown in FIG. 6F, by adjusting the time offset between the timing of the output of the open/close control signal and the timing of the output of the gain command signal to an ideal set time offset T, as shown in FIG. 6E.

A flowchart of an example of the method of determining the set time offset T is shown in FIG. 7. With this determination method, the switching of the radio-frequency signal switch 52 and the low-noise amplifier 12 is repeated while a time offset TT between the timing at which the open/close control signal is output and the timing at which the gain command signal is output is varied by a predetermined incremental step ΔT, fluctuations in the signal which is input to the demodulation circuit portion 20 which occur during that time are measured, and the time offset TT at which the fluctuation is the smallest is determined to be the set time offset T.

First of all, a constant electrical field is applied to the antenna 11 of the receiver device 1 in which the set time offset is to be determined, in a step S1. Next, in a step S12, the value of the time offset TT between the timing at which the open/close control signal is output and the timing at which the gain command signal is output is set to an initial value of 0.

In a step S13, the time offset TT is 0, in other words, the gain command signal and the open/close control signal after switching are output simultaneously, to perform the bypass switching of the low-noise amplifier 12 and the gain switching of the variable-gain amplifier 16. In a step S14, the fluctuation in the signal strength of the signal which is input to the demodulation circuit portion 20, caused during the switching, is measured and stored in a variable PC1.

In a step S16, the bypass switching of the low-noise amplifier 12 and the gain switching of the variable-gain amplifier 16 are performed in a state in which the time offset TT has been increased (step S15), and fluctuation in the signal strength of the signal which is input to the demodulation circuit portion 20, caused during the switching, is measured and stored in a variable PC2 (step S17).

In a step S18, the variables PC1 and PC2 are compared and, if the value in PC1 is greater than that in PC2 (in other words, if the signal strength fluctuation has been reduced as a result of the increase in the time offset TT), the incremental step ΔT is set to a positive value to ensure that the adjustment is in the direction in which the time offset TT increases (step S19). Conversely, if PC1 is not greater than PC2, the incremental step ΔT is set to a negative value (step S20).

Subsequently, in a step S21, a power history variable PH for storing a minimum value of the signal strength fluctuations of the signal which is input to the demodulation circuit portion 20, and measured at each time offset TT which is varied sequentially in subsequent steps S23 to S27, is set in the value of PC2 measured at step S17.

In a step S22, the incremental step ΔT which was determined as described above is added to each time offset TT, then the bypass switching of the low-noise amplifier 12 and the gain switching of the variable-gain amplifier 16 are performed (step S23), and the fluctuation in the signal strength of the signal which is input to the demodulation circuit portion 20, caused during the switching, is measured and stored in the variable PC2 (step S24).

In a step S25, it is determined whether or not the signal strength fluctuation value PC2 measured in the previous cycle has increased to more than the minimum value PH for fluctuations measured so far, in other words, whether or not the time offset TT has passed through the optimal adjustment point.

If the signal strength fluctuation value PC2 is smaller than the minimum value PH of fluctuations measured so far, the incremental step ΔT is again added to the time offset TT in a step S26, the minimum value PH is updated to the fluctuation value PC measured in this cycle, in a step S27, the processing returns to step S23, and the steps S23 to S27 are repeated until the signal strength fluctuation value PC2 begins to increase by adding the incremental step ΔT.

If the signal strength fluctuation value PC2 is larger than the minimum value PH of fluctuations measured so far in step S25, the incremental step ΔT is removed from the current time offset TT (TT−ΔT) and the result is determined to be the set time offset in a step S28, and processing ends.

Note that if the response speed of the variable-gain amplifier 16 is different between when the switchover is such as to increase the gain of the variable-gain amplifier 16 (in other words, switching which bypasses the low-noise amplifier 12) and when the switchover is such as to reduce the gain of the variable-gain amplifier 16 (in other words switching to halt the bypassing of the low-noise amplifier 12), the timing adjustment portion 43 could employ different set time offsets as the time offset T between the output timing of the gain command signal and the output timing of the open/close control signal, between during the switchover in which the gain of the variable-gain amplifier 16 increases and that in which it decreases. For that reason, the determination method shown in FIG. 7 is performed in both of the above-described cases, to determine set time offsets which are suitable for each case.

When the receiver device 1 moves, it is considered that the incoming signal strength could fluctuate in a direction from strong to weak, or from weak to strong, but when the receiver device 1 does not move, for example, it is considered that a constant reception strength is maintained. If the incoming signal strength of the receiver device 1 is maintained in the vicinity of the predetermined threshold value L1 for switching of the bypass of the low-noise amplifier 12, it is thought that the reception characteristic could deteriorate due to frequent bypass control switching.

In such a case, the thus-configured receiver device 1 has two threshold values for the incoming signal strength for the switchover of the radio-frequency signal switch 52 and the gain switching of the variable-gain amplifier 16, and hysteresis characteristics are provided in the switchover control of the radio-frequency signal switch 52 by the RF-SW switching portion 42 and the gain switching control of the variable-gain amplifier 16 by the V-AMP gain determination portion 41.

A graph of a gain command signal having a hysteresis characteristic which is generated by the V-AMP gain determination portion 41 is shown in FIG. 8A and a graph of an open/close control having a hysteresis characteristic which is generated by the RF-SW switching portion 42 is shown in FIG. 8B.

First of all, the comparatively low threshold value L1 and a comparatively high L2 are specified in the V-AMP gain determination portion 41 and the RF-SW switching portion 42 as threshold values for the gain switching control of the variable-gain amplifier 16 and for the switchover control of the radio-frequency signal switch 52. These threshold values could also be previously programmed into the logic circuits which make up the V-AMP gain determination portion 41 and the RF-SW switching portion 42, or they could be stored in an external storage element and read out for use, as will be described later.

As shown by the solid line in FIG. 8A, the V-AMP gain determination portion 41 performs variable control over the gain of the variable-gain amplifier 16 in accordance with the gain line GLL, which has a comparatively low gain, once the incoming signal strength has fallen below the comparatively low threshold value L1 and until the incoming signal strength subsequently reaches the comparatively high threshold value L2. Once the incoming signal strength exceeds the comparatively high threshold value L2, the V-AMP gain determination portion 41 performs the variable control over the gain of the variable-gain amplifier 16 in accordance with the gain line GLH, which has a comparatively high gain, until the reception strength reaches the comparatively low threshold value L1, as shown by the broken line.

Similarly, the RF-SW switching portion 42 puts the radio-frequency signal switch 52 into the open state once the incoming signal strength has fallen below the comparatively low threshold value L1 and until the incoming signal strength subsequently reaches the comparatively high threshold value L2, as shown by the solid line in FIG. 8B. Once the incoming signal strength exceeds the comparatively high threshold value L2, the RF-SW switching portion 42 puts the radio-frequency signal switch 52 into the closed state until the incoming signal strength subsequently reaches the comparatively high threshold value L2, as shown by the broken line.

A flowchart of the method of controlling the opening/closing of the radio-frequency signal switch 52 and the gain of the variable-gain amplifier 16, using hysteresis characteristics, is shown in FIG. 9.

First of all, at a step S31 at the start of operation of the receiver device 1, the RF-SW switching portion 42 outputs the open/close control signal to put the radio-frequency signal switch 52 into the open state, so that the received signal is amplified by the low-noise amplifier 12, and the V-AMP gain determination portion 41 uses the gain line GLL, having a comparatively low gain, to perform variable control of the gain of the variable-gain amplifier 16.

If the OFDM receiver device 1 receives a signal in a step S32, the power detection portion 33 detects an incoming signal strength RI of the received signal at a step S33.

At a step S34, the RF-SW switching portion 42 and the V-AMP gain determination portion 41 determine whether or not the incoming signal strength RI has exceeded the comparatively high threshold value L2 and, if the incoming signal strength RI has not exceeded the threshold value L2, the processing returns to step S32 and steps S32 to S34 are repeated. During this time, the radio-frequency signal switch 52 remains open and the V-AMP gain determination portion 41 continues the gain control of the variable-gain amplifier 16, still using the gain line GLL.

If the incoming signal strength RI has exceeded the threshold value L2 in step S34, the RF-SW switching portion 42 switches the value of the open/close control signal to the value which puts the radio-frequency signal switch 52 in the closed state, so that the received signal bypasses the low-noise amplifier 12, and the V-AMP gain determination portion 41 switches the gain line used in the control of the variable-gain amplifier 16 to the comparatively high gain line GLH at step S35.

When the receiver device 1 receives the signal subsequently at step S36, the power detection portion 33 detects the incoming signal strength RI of the received signal at step S37.

At step S38, the RF-SW switching portion 42 and the V-AMP gain determination portion 41 determine whether or not the incoming signal strength RI has fallen below the comparatively low threshold value L1 and, if the incoming signal strength RI has not fallen below the threshold value L1 the processing returns to step S36 and steps S36 to S38 are repeated. During this time, the radio-frequency signal switch 52 remains in the closed state and the V-AMP gain determination portion 41 continues the gain control of the variable-gain amplifier 16, still using the gain line GLH.

If the incoming signal strength RI has fallen below the threshold value L1 at step S38, the RF-SW switching portion 42 switches the value of the open/close control signal to the value which sets the radio-frequency signal switch 52 to the open state, so that the received signal is amplified by the low-noise amplifier 12, and the V-AMP gain determination portion 41 switches the gain line used in the gain control of the variable-gain amplifier 16 to the comparatively low gain line GLL, and then the processing returns to S32.

The provision of these hysteresis characteristics to the switchover control of the radio-frequency signal switch 52 and the gain switching control of the variable-gain amplifier 16 ensures that no bypass control is applied so long as there are no fluctuations in the incoming signal strength which reach as far as one of the two threshold values L1 and L2, if bypass control has been activated by the other threshold value, thus making it possible to restrain the frequency at which bypass control is switched. Note that the threshold values L1 and L2 are preferably set by conversions which suit the elements and circuit configuration of the receiver device 1, as well as the characteristics of the circuitry as a whole (such as the NF characteristics thereof).

Even if the time offset between the open/close timing of the radio-frequency signal switch 52 and the timing of the gain switching of the variable-gain amplifier 16 is adjusted optimally, the gain line for the entire receiver device 1 will not be a complete straight line; a slight gain fluctuation will occur at the switching, as shown in FIG. 6F. In addition, there is a danger that the transient response components of the DC offset component of the low-noise amplifier 12 and the variable-gain amplifier 16 will be amplified by such gain fluctuations, reducing the reception capability.

For example, since the DC offset components of the low-noise amplifier 12 and the variable-gain amplifier 16 become input offsets at the analog-digital converters 25a and 25b which convert analog baseband signals into digital baseband signals, the dynamic ranges of the analog-digital converters 25a and 25b will be compressed by any increase in these DC offset components, which leads to a deterioration in the S/N ratio of the digital baseband signal.

In the present example of the configuration, deterioration of the reception capability due to transient response components of the DC offset components in this example of the configuration can be avoided by allocating a null carrier (a carrier component which does not include a significant signal) to a sub-carrier of the plurality of sub-carrier signals which make up the OFDM signal which is converted into the DC component in the demodulation circuit portion 20, and removing the DC offset components of the low-noise amplifier 12 and the variable-gain amplifier 16 at the previous stage of the analog-digital converters 25a and 25b.

The spectrum of an OFDM received signal which has passed through the frequency converter 13 and been converted into an intermediate-frequency signal is shown in FIG. 10. As shown in this figure, the OFDM received signal comprises a plurality of sub-carrier signals W0 to W6 which are allocated to different frequency bands.

Of this plurality of sub-carrier signals, the sub-carrier W0 which has the central frequency of its carrier frequency band, which is identical to the frequency of the local signal which the demodulation circuit portion 20 uses in the orthogonal demodulation (orthogonal detection), is converted into the DC signal component by the orthogonal demodulation of the demodulation circuit portion 20. By allocating the null carrier to this sub-carrier, it becomes possible to ignore the DC signal components comprised within the analog baseband signal.

Thus, of the plurality of sub-carrier signals which make up the OFDM signal, the sub-carrier signal which is converted into the DC component by the orthogonal demodulation is determined to correspond to the frequency LO2 of the local signal which is used in the orthogonal demodulation and is taken as the null carrier. The device comprises DC component cancelers 26a and 26b configured of high-pass filters or the like which remove the DC component from the analog baseband signal which has been converted by the orthogonal demodulation, to remove the DC offset components of the low-noise amplifier 12 and the variable-gain amplifier 16, together with the DC components generated by the conversion of the null carrier.

An example of the configuration of an OFDM receiver device in accordance with a embodiment example of the present invention is shown in FIG. 11. With this configuration, the set time offset T which is designated as a time offset between the open/closing period of the radio-frequency signal switch 52 and the switching period of the gain of the variable-gain amplifier 16 as described above is stored beforehand in the memory portion 44.

The timing adjustment portion 43 is implemented by a digital logic circuit, in a similar manner to that described above with reference to FIG. 5, but instead of having the set time offset T programmed beforehand into the timing adjustment portion 43 as in the configurational example of FIG. 5, the set time offset T which is stored in the memory portion 44 is read out therefrom, and the time between the open/closing period of the radio-frequency signal switch 52 and the switching period of the gain of the variable-gain amplifier 16 is adjusted to this set time offset T.

In this example of the configuration, the RF-SW switching portion 42 and the V-AMP gain determination portion 41 perform the switching control over whether or not the low-noise amplifier 12 is to be bypassed and the gain switching control of the variable-gain amplifier 16, and also the threshold value L1 for switching of the bypass of the low-noise amplifier 12 is stored in the memory portion 44. The RF-SW switching portion 42 and the V-AMP gain determination portion 41 use the threshold value L1 which is read out from the memory portion 44 at the start of operation of the receiver device 1, to determine whether or not switching of the bypass of the low-noise amplifier 12 is necessary and whether or not the gain switching of the variable-gain amplifier 16 is necessary.

Note that in this example of the configuration as well, two threshold values L1 and L2 can be provided for switching of the bypass of the low-noise amplifier 12, and hysteresis characteristics can be provided for the switchover control over the radio-frequency signal switch 52 by the RF-SW switching portion 42 and the gain switching control of the variable-gain amplifier 16 by the V-AMP gain determination portion 41. These two incoming signal strength threshold values L1 and L2 can also be stored in the memory portion 44, so that the RF-SW switching portion 42 and the V-AMP gain determination portion 41 can read them out.

The present invention makes it possible to set both the timing of the switching of bypassing of one of a plurality of serially-connected amplifiers and the timing of gain switching of another of those amplifiers, accurately and also flexibly.

It also enables easy removal of DC offset components in the amplifies caused by the switching timing state, even if those components have been amplified.

Since a digital logic circuit is used instead of the time constant circuit of the prior art, the timing adjustment portion can be incorporated into an integrated logic circuit in a conventional receiver device, thus improving the reception characteristics without increasing the number of components or the cost.

The present invention can be applied to a receiver device which performs automatic gain control to regulate a received signal to a predetermined signal strength.

While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art, without departing from the basic concept and scope of the invention.

Claims

1. A receiver device having serially-connected first and second amplifiers which amplify a received signal, a switch which causes said received signal to bypass said first amplifier, and a gain control portion which regulates said received signal to a predetermined signal level by controlling the opening and closing of said switch and exerting variable control over the gain of said second amplifier, depending on the incoming signal strength of said received signal; wherein said gain control portion compensates for gain fluctuations due to the opening and closing of said switch by switching over the gain of said second amplifier; wherein said gain control circuit comprises a digital logic circuit which adjusts a time offset between the open/closing period of said switch and the switching period of the gain of said second amplifier to a previously programmed setting.

2. The receiver device as set forth in claim 1, wherein: said digital logic circuit is a programmable digital logic board which has been previously programmed with a time offset between the open/closing period of said switch and the gain switching period of said second amplifier.

3. The receiver device as set forth in claim 1, wherein: said gain control circuit further comprises a memory portion in which is previously stored a setting of a time offset between the open/closing period of said switch and the gain switching period of said second amplifier; andsaid digital logic circuit adjusts the time offset between the open/closing period of said switch and the gain switching period of said second amplifier to said stored setting.

4. The receiver device as set forth in claim 1, wherein: the open/close control of said switch and the switching control of the gain of said second amplifier performed by said gain control portion have a hysteresis characteristic.

5. The receiver device as set forth in claim 1, wherein: said received signal is an orthogonal frequency-division multiplexed signal formed of a plurality of sub-carrier signals including a null carrier;said receiver device comprises a orthogonal demodulator, which performs orthogonal demodulation on an orthogonal frequency-division multiplexed signal with a predetermined local signal, and a DC component canceler, which removes a DC component of an orthogonally demodulated signal; andthe frequency of said predetermined local signal is determined to be the frequency at which said null carrier which has been demodulated by said local signal forms a DC component.