Receiver With Improved Noise Immunity

Abstract

A binary receiver combines a fast amplifier with a relatively slow amplifier for noise rejection. Both the fast and slow amplifiers employ hysteresis. The fast amplifier has relatively lower hysteresis, meaning that its sensitivity is a less effected by prior data values but more susceptible to glitch-induced errors. Conversely, the slow amplifier has relatively higher hysteresis and rejects glitches but introduces undesirable signal-propagation delays. A state machine taking input from both amplifiers allows the receiver to filter glitches without incurring a significant data-propagation delay.

Description

BACKGROUND

Digital signals represent data as a sequence of symbols that each represent a discrete value. This contrasts with analog signals, which represent data across a continuum. The following discussion relates to binary signals, digital signals that represent data with only two values, commonly represented as zero and one.

Binary signals represent zeros and ones as bands of analog levels. For example, voltage levels below some reference level may represent a logic zero and above the reference level a logic one. Inadvertent changes to the signal can be disregarded so long as the voltage level remains within the respective low and high ranges. Information can thus be transmitted without error.

Binary signals cannot transition between high and low ranges instantaneously, and not all such transitions are a function of the communicated data. Various types of noise and circuit imperfections can induce erroneous transitions and thus introduce errors in the digital data. For example, wires that extend between integrated circuits to communicate binary signals can introduce reflections of signal transitions that appear as “glitches” at the receiver. A glitch that appears at an inopportune instant can be misperceived as a data transition, and thus introduce an error.

A form of binary communication is defined by a specification called MIPI I3C, which details an electrical connection between integrated-circuit devices. The MIPI I3C connection includes two wires, one that conveys a binary data signal and another that conveys a clock signal for timing receipt of the data signal at the recipient device. In general, the data symbol can transition between one and zero after a falling edge of the clock signal so that the new value can be sampled on the next rising edge. Signal reflections induce glitches that can cause errors, particularly at higher data rates. As in myriad other digital circuits, receivers that comply with the MIPI I3C standard should be simple, inexpensive, efficient, fast, and error free.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 depicts a receiver 100, a state diagram 105 for receiver 100, and a timing diagram 110 illustrating the operation of receiver 100.

FIG. 2 depicts a receiver 200 in accordance with another embodiment.

FIG. 3 depicts a receiver 300 in accordance with yet another embodiment.

DETAILED DESCRIPTION

An architecture for a binary receiver combines a fast amplifier for speed performance with a slow amplifier for noise rejection, “fast” and “slow” being relative to one another. Both the fast and slow amplifiers employ hysteresis, which means that their sensitivity to changes in the received signal depends upon the history of that signal. Between the two, the fast amplifier has lower hysteresis, meaning that its sensitivity is less effected by prior data values but more susceptible to glitch-induced errors. Conversely, the slow amplifier has relatively higher hysteresis and thus rejects glitches but introduces undesirable signal-propagation delays. A state machine taking input from both amplifiers allows the receiver to offer the advantages of each, filtering glitches without incurring a significant data-propagation delay.

FIG. 1 depicts a receiver 100 for recovering a binary, digital output signal OUT from a voltage-modulated input signal VIN expressing a series of input symbols, each symbol expressed as a voltage within a range representative of either a first digital value (logic zero) or a second digital value (logic one). FIG. 1 additionally includes a state diagram 105 and a timing diagram 110 illustrating the operation of receiver 100 in accordance with one embodiment.

Receiver 100 includes a first amplifier 115 that amplifies input signal VIN while applying a first, relatively high hysteresis feedback transfer function (HFTF) 120 of its output to input signal VIN. A second amplifier 125 likewise amplifies signal VIN while applying a second, relatively low HFTF 130 of its output to input signal VIN. HFTFs 120 and 130 reduce the output switching speeds of respective amplifiers 115 and 125. The higher hysteresis provided by HFTF 120 is a stronger function of the output of amplifier 115 than lower hysteresis provided by HFTF 130 is of the output of amplifier 125. The output of amplifier 115 is thus slower to react to fluctuations of signal VIN than is the output of amplifier 125. Each of amplifiers 115 and 125 applies its respective hysteresis feedback to an input of a comparator 135, e.g. by adding the feedback to signal VIN or subtracting the feedback from a reference against which signal VIN is compared.

The outputs from amplifiers 115 and 120 stimulate a finite-state machine (FSM) 140 to transition between the four states illustrated in state diagram 105 to produce binary output signal OUT. State machine 140 sets output signal OUT to zero in two states 0A and 0B and to one in two states 1A and 1B.

Turning to timing diagram 110, input signal VIN is depicted as a trace 150 that transitions between extreme input levels VIL (voltage in, low) and VIH (voltage in, high) and around a middle level VIM (voltage in, mid). Output signal OUT is depicted as a binary trace 155 that transitions between a low value representative of a binary value of zero and a high level representative of a binary value of one. Input trace 150 includes glitches 160 that are not meant to communicate data. By selectively employing alternative levels of hysteresis, receiver 100 is able to quickly transition output signal OUT responsive to changes in signal VIN while disregarding glitches 160.

The relatively high hysteresis of high HFTF 120 is represented in timing diagram 110 as voltage levels VHH2 and VHL2. For the output of the slow, high-hysteresis amplifier 115 to switch from low to high, voltage VIN must rise above level VHH2; for the output of amplifier 115 to switch from high to low, voltage VIN must drop below level VHL2. For the output of the relatively fast, low-hysteresis amplifier 125 to similarly transition, voltage VIN must rise above level VHH1 or fall below level VHL1. Higher hysteresis means that levels VHH2 and VHL2 are more different than levels VHH1 and VHL1, and thus that the output of amplifier 115 is slower to change responsive to input signal VIN than is the output of amplifier 125.

The following discussion moves between state diagram 105 and timing diagram 110 to illustrate the operation of receiver 100. Beginning at the left of the timing diagram, signal VIN is at the bottom of its range and state machine 140 is in state 0B outputting a logic zero as output signal OUT. State 0B is a “fast” state, meaning the receiver 100 makes relatively fast decisions in this state. The way to transition out of state 0B is to detect a fast, low-hysteresis transition via amplifier 125. When signal VIN rises above level VHH1, state machine 140 transitions from state 0B to state 1A (0B→1A), raising output signal OUT to a level indicative of a logic one. State 1A is a “slow” state, meaning the receiver 100 makes relatively slow decisions in this state. The way to transition out of state 1A is to detect a slow, high-hysteresis transition via amplifier 115. Two high-hysteresis transitions are possible from state 1A, as input signal VIN can either rise above level VHH2 or fall below level VHL2. In the example of diagram 110, signal VIN rises above level VHH2 so state machine 140 transitions to fast state 1B (1A→1B) and maintains output signal OUT at logic one. Had signal VIN instead fallen below level VHL2, state machine 140 would have transitioned back to fast state 0B and output signal OUT would have returned to zero.

State machine 140 only transitions from fast state 1B if signal VIN falls below level VHL1, at which point state machine 140 transitions to slow state 0A (1B—>0A) and switches output signal OUT to logic zero. As in slow state 1A, two high-hysteresis transitions are possible from slow state 0A. In the example of diagram 110, signal VIN rises above level VHH2 so state machine 140 transitions to fast state 1B (0A→1B) and raises output signal OUT to logic one. Had signal VIN instead fallen below level VHL2, state machine 140 would have instead transitioned to fast state 0B and output signal would have remained at zero.

The remaining transitions of timing diagram 110 proceed according to state diagram 105, with each state transition moving between fast and slow states. The fast states (0B and 1B) allow output signal OUT to respond quickly to changes in input signal VIN, but each fast state is only arrived at via a slow state that applies a relatively high level of hysteresis to filter out glitches. Receiver 100 thus benefits from the speed of amplifier 125 and the glitch tolerance of amplifier 125.

The values of levels VHH2, VHL2, VHH1, and VHL1 are adjustable in some embodiments, allowing receiver 100 to be calibrated during e.g. a boot cycle that optimizes for some tradeoff between efficiency and performance. In a low-noise environment, some of receiver 100 can be disabled to save power. For example, state machine 140 might be limited to fast states 0B and 1B and rely on only amplifier 125 for state transitions. The remaining amplifier 115 can be disabled. Registers, not shown, can be loaded during calibration to configuration receiver 100.

FIG. 2 depicts a receiver 200 in accordance with another embodiment. Receiver 200 includes three comparators 205, 210, and 215, amplifiers that amplify input signal VIN with respect to a respective reference level and feed a resultant binary decision to a finite state machine (FSM) 220. Comparator 205 is equipped with positive feedback that applies the relatively low level of hysteresis of the fast states of FIG. 1. This configuration, commonly known as a Schmitt trigger, offers relatively fast and power-efficient switching but with somewhat poor control that can exacerbate glitch sensitivity. Comparators 210 and 215 may be of a less efficient and more precise configuration, but the circuitry can run at a lower slew rate for reduced power consumption. Comparators 210 and 215 do not themselves apply hysteresis feedback in this example but FSM 220 saves the states of their outputs or signal OUT so that transitions from slow states are dependent upon transitions from comparator 210 and 215 rather than the only the current values of their outputs. Comparators 210 and 215, with state information in FSM 220, can be thought of as a single amplifier 225 that applies the relatively high level of hysteresis of the slow states of FIG. 1. The HFTFs are simple, linear functions in this embodiment but other linear and nonlinear functions can be used.

FIG. 3 depicts a receiver 300 in accordance with another embodiment. Relatively slow, high-hysteresis amplification is provided by amplifier 225 of FIG. 2 using reference levels VHH2 and VHL2; relatively fast, low-hysteresis amplification is provided by a similar amplifier 305 that uses reference levels VHH1 and VHL1 that are more closely spaced. An FSM 310 produces output signal OUT as a function of the output levels from amplifiers 225 and 305, including their prior states, to transition as illustrated in state diagram 105 of FIG. 1.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding. In some instances, the terminology and symbols may imply specific details that are not required. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Moreover, while the receivers detailed above communicate binary signals using four states, other embodiments support additional states to communicate digital signals using more than two levels.

While the subject matter has been described in connection with specific embodiments, other embodiments are also envisioned. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.

Claims

1. (canceled)

2. A receiver comprising: an input node to receive an input signal;a first amplifier coupled to the input node to produce first decisions responsive to the input signal, the first amplifier to apply a first hysteresis feedback transfer function of the first decisions to the input signal;a second amplifier coupled to the input node to produce second decisions responsive to the input signal, the second amplifier to apply a second hysteresis feedback transfer function of the second decisions to the input signal; anda state machine having a first state-machine input coupled to the first amplifier and the second amplifier, the state machine to transition between first, second, third, and fourth states responsive to the first decisions and the second decisions.

3. The receiver of claim 2, wherein the state machine only transitions between the first, second, third, and fourth states.

4. The receiver of claim 2, wherein the state machine issues a first binary value in the first and second states and a second binary value in the third and fourth states.

5. The receiver of claim 4, wherein the state machine transitions from the first state to the second state and from the third state to the fourth state responsive to the first decisions.

6. The receiver of claim 5, wherein the state machine transitions from the second state to the third state and from the fourth state to the first state responsive to the second decisions.

7. The receiver of claim 6, wherein the state machine transitions from the first state to the fourth state and from the third state to the second state responsive to the first decisions.

8. The receiver of claim 2, wherein the first amplifier is slow relative to the second amplifier.

9. The receiver of claim 8, wherein the first hysteresis feedback transfer function exhibits higher hysteresis than the second hysteresis feedback transfer function.

10. A method of recovering a digital output signal from a series of input symbols, the method comprising: making a first decision for each of the input symbols while applying a low hysteresis feedback transfer function of the first decisions to the input symbols;making a second decision for each of the input symbols, the second decisions slow relative to the first decisions, while applying a high hysteresis feedback transfer function of the second decisions to the input symbols, the high hysteresis feedback transfer function greater than the low hysteresis feedback transfer function;in a slow state, ignoring the first decisions while outputting the digital output signal responsive to each of the second decisions; andin a fast state, ignoring the second decisions while outputting the digital output signal responsive to each of the first decisions.

11. The method of claim 10, wherein the slow state is one of first and second slow states, the method further comprising ignoring the first decisions while outputting a first binary value of the digital output signal in the first slow state and ignoring the first decisions while outputting a second binary value of the digital output signal in the second slow state.

12. The method of claim 11, wherein the fast state is one of first and second fast states, the method further comprising ignoring the second decisions while outputting the first binary value of the digital output signal in the first fast state and ignoring the second decisions while outputting the second binary value of the digital output signal in the second fast state.

13. The method of claim 10, wherein the low hysteresis feedback transfer function is linear.

14. The method of claim 13, wherein the high hysteresis feedback transfer function is linear.

15. The method of claim 10, wherein applying at least one of the low hysteresis feedback transfer function and the high hysteresis feedback transfer function comprises adding to the input symbols.

16. The method of claim 10, further comprising comparing the input symbols to a reference, wherein applying at least one of the low hysteresis feedback transfer function and the high hysteresis feedback transfer function comprises subtracting from the reference.

17. The method of claim 10, wherein the digital output signal is a binary signal.

18. A receiver for recovering a digital output signal from a series of input symbols, the digital output signal exhibiting a first digital value and a second digital value, the receiver comprising: a first amplifier to make a first decision for each of the input symbols while applying a low hysteresis feedback transfer function of the first decisions to the input symbols;a second amplifier to make a second decision for each of the input symbols while applying a high hysteresis feedback transfer function of the second decisions, the high hysteresis feedback transfer function a stronger function of the second decisions than the low hysteresis feedback transfer function is of the first decisions;a state machine to transition between states responsive to the first decisions and the second decisions, the state machine having: a first slow state to output the first digital value;a second slow state to output the second digital value;a first fast state to output the first digital value; anda second fast state to output the second digital value;the state machine to transition: from the first slow state to one of the first and second fast states responsive to the second decisions, ignoring the first decisions; andfrom the second slow state to one of the first and second fast state responsive to the second decisions, ignoring the first decisions.

19. The receiver of claim 18, the state machine to transition: from the first fast state to one of the first and second slow states responsive to the first decisions, ignoring the second decisions; andfrom the second fast state to one of the first and second slow states responsive to the first decisions, ignoring the second decisions.

20. The receiver of claim 19, wherein the state machine transitions from the first and second slow states to either of the first and second fast states.

21. The receiver of claim 20, wherein the state machine transitions from the first fast state to only one of the first and second slow states and from the second fast state to only the other of the first and second slow states.