Patent Application
20250055500
The invention relates to a receiver front-end, in particular it relates to a radio frequency (RF) front-end for a pulsed or impulse radar such as an ultra-wideband (UWB) radar.
UWB pulsed radars are often used for short range sensing such as proximity, presence and gesture detection, and heart rate and respiration monitoring. In such scenarios, the target to be detected can be very close to the radar, e.g., within a few centimeters, or even a few millimeters. A (strong) reflection from the target (or reflector) will then be received by the radar in a very short space of time after transmission, or even while transmission is still ongoing.
While a reflected signal from such a close target will still be very strong, the receiver architecture is designed for and must be capable of amplifying a reflection from significantly greater distance and therefore of much lower amplitude. The weak reflected signal is boosted by a high gain amplifier, typically a low-noise amplifier (LNA) and may also be accumulated over multiple individual pulses so as to reinforce the reflected signal while averaging out noise. A filter may be placed before the LNA to reject (unwanted) out-of-band signals.
The requirement for a high gain amplifier in the receiver hinders the design of the radar architecture in certain ways. In particular, the transmitter must be high powered to generate pulses with sufficiently large voltage swing so that reflections can be received from a required range. If those high power transmit pulses are fed to the amplifier of the receiver, they can damage the circuitry. Therefore, design is typically limited to either a two-port (2-port) full-duplex design (a transmitter driving a first antenna and a receiver amplifying signal from a second antenna) or a single-port (1-port) half-duplex design in which the receiver and transmitter share an antenna, but the receiver's amplifier is switched OFF or blocked during transmission to protect it from the high power transmit pulse. A 1-port transceiver design is beneficial in terms of form factor as each antenna can take up a lot of physical area. For example, where all the processing can be done on-chip, the antennae make up the majority of the overall device area. Therefore, removing one antenna can almost halve the device area (particularly important for incorporation into small and/or portable devices such as laptops, tablets, mobile telephones or wearable devices or other devices where space is constrained, e.g., the bezel around a display screen). However half-duplex operation restricts near-zero range detection as no reflections can be received (in the receiver's high gain mode) until after the transmitter has finished transmitting and the receive path has been switched back ON.
According to the invention there is provided a differential transceiver circuit for transmitting and receiving via a single antenna interface, the transceiver circuit comprising:
In this document, “downstream” is used to refer to the receive signal direction, i.e., with the antenna being at the most upstream location and with receive signal proceeding downstream from the antenna through the amplifier to the load. It will be appreciated that the transmit signal goes in the opposite direction from the transmitter to the antenna, but any transmit signal that passes through the amplifier is also in a downstream direction.
From the transmitter, the first and second transmit signals are transmitted both to the antenna (for pulse transmission) and through the differential amplifier towards the processing circuitry. However, this transmission of large signals through the amplifier is undesirable and is what gives rise to the half-duplex operation in single antenna designs as the transmit signal swing is too large for downstream components to handle. Hence, in previous designs, the amplifier has simply been switched OFF during transmit mode so as to protect downstream components. With the above architecture, however, during transmit mode (i.e., while the transmitter is transmitting), the differential circuit is essentially switched into a single-ended receive mode. The receive signal (and unwanted transmit signal) on one signal path of the differential circuit is diverted to ground and therefore not available for further processing. In its place, the transmit signal corresponding to the other differential signal path is inserted so that the same transmit signal (with the same polarity) is present on both differential signal paths. Thus, when the differential signal is processed by differential downstream components with high common-mode rejection, the transmit signals on the two differential signal paths (i.e., of the same polarity) cancel out, leaving just the receive signal on one signal path to be processed. This allows the receive signal to be received and processed throughout transmission and therefore allows pseudo-full-duplex operation. We refer to this as pseudo-full-duplex rather than full-duplex as the architecture requires a switch from differential to single-ended receive operation and therefore only receives a fraction (e.g., half) of the signal strength that it can receive during full differential receive mode (i.e., any time when the transmitter is inactive).
It will be appreciated that the arrangement described here is a direct-RF front end, i.e., the RF signal is received and processed directly without any frequency conversion. In such arrangements the filtering is particularly important to restrict the receive signal to just the signal of interest while excluding out-of-band interferers. In some cases, filtering can be achieved with just the antenna, but for direct-RF arrangements this is usually not sufficient and so a dedicated filter is required. By way of example only, in some direct-RF front ends the filter and amplifier try to realize around 60 dB attenuation out-of-band with a noise figure<5 dB.
There are different ways in which the receive signal path can be diverted to signal ground and different ways in which the first transmit signal is connected onto the signal path. For example, a selector switch could be used to determine whether to connect the receive signal to the output or to signal ground. However, in some preferred embodiments the switching network comprises a first switch arranged to selectively connect the second signal path to a transceiver circuit output, and a second switch arranged to selectively connect the second signal path to the signal ground node. The use of two switches, one for each connection makes for fast and convenient operation with transistor switches. For example, in some examples these switches are FETs (e.g., MOSFETs) for fast switching operation. Normally these two switches are in opposite states (i.e., when one is ON the other is OFF and vice versa) so that the signal is only sent along one onward path. Both switches can of course be switched OFF to block onward signal transmission completely, e.g., if half-duplex operation is desired.
In preferred embodiments the injection circuit comprises an injection switch arranged to selectively connect the injection circuit to the second signal path. The injection of the first transmit signal onto the second differential signal path can thus be controlled selectively so that it is only injected during pseudo-full-duplex operation, e.g., during transmit mode. During normal receive mode (i.e., when the transmitter is OFF), there is no need for the injection circuit and it is therefore separated (the injection switch is OFF) so that a full differential receive signal can pass along the second path for improved signal reception.
The copy of the first transmit signal can be obtained in different ways. In some embodiments the injection circuit obtains the copy of the first transmit signal directly from the differential transmitter. Obtaining the signal directly from the differential transmitter is advantageous as the identity of the first transmit signal on both differential signal paths can be ensured more accurately. In such embodiments the transmit signals provided onto both the first differential signal path and the second differential signal path are both generated by the same transmitter circuit and therefore the waveform (e.g., amplitudes, phases, etc.) are identical at source. This may be achieved using a splitter or a transformer in the transmitter to duplicate the signal. The copy of the signal is unconnected with the main differential signal paths and so does not (and cannot) have any receive signal present through the injection circuit. Also, in this way the injection circuit path does not affect the main differential signal path.
In other embodiments the injection circuit may comprise a dummy transmitter circuit substantially identical to one differential half of the differential transmitter, and which is arranged to generate the copy of the first transmit signal. Although this requires an additional transmitter circuit (and is therefore inefficient in area terms), it keeps the injection path completely isolated from the main transmit architecture and therefore has no effect on the main transmitter itself.
Whichever way the copy of the transmit signal (required for cancellation) is generated (directly or indirectly via a dummy transmitter), it is important to ensure that the generated transmit signal is processed identically in the injection path as it is in the main first differential signal path. This is to ensure that any alterations in amplitude and/or phase on one version are mimicked in the other version. Keeping the two versions as identical as possible is important for ensuring that they can be canceled accurately and completely in later processing. Any differences will result in incomplete cancellation and therefore degradation of the actual receive signal (e.g., indicative of a reflection from a target object in a radar implementation). Accordingly, in some embodiment the injection path comprises a dummy amplifier. The dummy amplifier is preferably substantially identical to one differential half of the differential amplifier. This ensures that the signals on the injection path and the first differential signal path are amplified in exactly the same way and thus influenced (e.g., amplified) to the same degree so that they should cancel completely (or as near completely as possible) in later processing, e.g., in a circuit with high common-mode rejection.
As the injection path is separate from the first transmit path, the impedance that it sees is different to that of the first differential signal path. In particular, the first differential signal path is connected to the antenna so that the first transmit signal can be sent out as an RF waveform. The injection path on the other hand is not connected to the antenna. This difference results in different impedances on each transmit signal path which can create differences between the two signals. Therefore, in some preferred embodiments the injection path comprises an impedance matching network arranged to match the impedance seen by the copy of the first transmit signal on the injection path to the impedance seen by the first transmit signal on the first signal path. The impedance matching network can be used to mimic the impedance at the point where the transmit signal is inserted (as well as any other impedance differences between the two paths) and can therefore be used to adjust the impedances of the two paths to be identical (or near identical). Once again this ensures that the transmit signal on each of the first and second differential signal paths ends up being as identical as possible for later cancellation. Preferably the impedance matching network is trimmable. A trimmable (i.e., adjustable) network means that the transceiver circuit can be tuned during calibration so as to ensure correspondence of the transmit signals passing along the first differential signal path and the injection path. Calibration may involve sending a known waveform along each path, comparing them, and adjusting the trimmable impedance matching network until the difference is zero or as near-zero as can reasonably be achieved. The impedance matching network is preferably a resistive-capacitive network. While inductors could also be used in the impedance matching network, it is preferred to use just a resistive-capacitive network as inductors are large and costly to add to on-chip circuits. On the other hand, resistors and capacitors are relatively inexpensive on-chip and are sufficient to allow adjustment of both the real and imaginary components of impedance so as to ensure correspondence of the transmit signals as discussed above. In some embodiments, where adding inductors is not an issue or where they provide the best matching, the impedance matching network may be a resistive-capacitive-inductive network.
The differential transceiver circuit may further comprise a controller, the controller arranged such that, during a transmit pulse, it: controls the switching network to divert the amplifier output on the second signal path to the signal ground node; and controls the injection circuit to inject the copy of the first transmit signal onto the second signal path. The controller can be used to switch the differential transceiver circuit between different modes, e.g., between a receive mode (fully-differential receive mode) and a transmit mode (single-ended receive mode). The controller may additionally be able to switch the differential transceiver circuit into a half-duplex mode in which the receiver is switched OFF during transmission.
The switching network may comprise a first circuit branch which comprises a first buffer element in series with the first switch. The first buffer element serves to buffer the signal through the first circuit branch. In normal operation, this provides high output impedance (as seen from the load) and reverse isolation, i.e., to isolate the load connected to the output from the input and guarantee unconditional stability. The first buffer element may be a non-switchable element configured to be in an always-ON configuration. The isolation provided by the first buffer element prevents any changes in load from impacting any impedance matching upstream (i.e., closer to the antenna). In addition, the load conditions (e.g., frequency selectivity) remain unaffected. This has the benefit that the frequency response of the receiver remains the same regardless of operating mode. Even when the only signal through the buffer element is via the injection circuit, the frequency response retains the same shape. This facilitates subsequent processing of the signal. It will be appreciated that when the first switch is a transistor it can also provide amplification to the signal in addition to providing its function of switching off the circuit branch to the transceiver circuit output. Thus, the first switch may be an integral part of the amplifier. Equally, the first buffer element could be made to be switchable as well, but this is not necessary given the presence of the first switch. The first buffer element may also be a switchable element (such as a transistor) configured so as to be in an always-ON configuration. The first buffer element may be a unity gain buffer, or it may be an amplifier to provide additional gain if desired.
The first buffer element may be connected between the first switch and the transceiver circuit output. The first buffer element may be a single stage or a cascade of stages. For a single stage, it may comprise a field effect transistor (FET).
In some examples, the first switch and the first buffer element each comprise transistors in a common-gate (CG) arrangement (i.e., current buffers). Thus, the second signal path comprises a common-gate configured transistor as the first switch, with its drain connected to the source of a common-gate configured transistor as the first buffer element. The drain of the first buffer element can also be directly connected to the transceiver circuit output. The first buffer element provides the reverse isolation while the first switch provides the ON/OFF control of the second path from the amplifier as well as acting as a current buffer (with low input impedance and high out impedance). The first buffer element (e.g., a non-switching CG-stage) buffers signal from the first switch to the load.
The switching network may comprise a second circuit branch which comprises a second buffer element in series with the second switch. The second buffer element may be connected between the second switch and the signal ground node. The second buffer element may be a unity gain buffer, or it may be an amplifier to provide additional gain if desired.
The second switch and the second buffer element may each comprise transistors in a common-gate arrangement. The second buffer element may be a unity gain buffer, or it may be an amplifier to provide additional gain if desired.
The second switch may be identical to the first switch. Identical here means to have the same characteristics so that the first and second switches have the same effect on the circuit when they are used as alternatives. In practice, this means that the first and second switches may have the same physical dimensions. They may be made from the same material with the same doping. They may be transistors with the same threshold voltage.
The second buffer element may be identical to the first buffer element so as to provide the same characteristics when the second signal path is diverted to ground and when it is not diverted to ground.
The transceiver circuit can be operated in different modes by either sending the second signal path to the transceiver circuit output or replacing it with the signal from the injection circuit. In some embodiments the transceiver circuit further comprises a controller; wherein the controller is arranged to operate in at least a transmit mode and a receive mode; wherein in the transmit mode, the controller controls the switching network to divert the amplifier output on the second signal path to the signal ground node and controls the injection circuit to inject the copy of the first transmit signal onto the second signal path; and wherein in the receive mode, the controller controls the switching network not to divert the amplifier output on the second signal path to the signal ground node and controls the injection circuit not to inject the copy of the first transmit signal onto the second signal path.
In the transmit mode, the transmitter is active and provides a strong signal on both the first signal path and the second signal path. In order to prevent damage to downstream components, the second signal path is controlled to divert the signal (or at least the majority of it) to the signal ground node while replacing it with a copy of the transmit signal on the first signal path (the first transmit signal) such that the first transmit signal is common to both the first and second signal paths while the receive signal is present (in single-ended form) only on the first transmit path. In the receive mode, the second signal path is controlled to pass the signal (or at least the majority of it) from the differential amplifier to the transceiver circuit output for onwards processing. In this mode, the transmitter is not active and so the only signal present at the transceiver circuit output is the (wanted) received small signal from the antenna in differential form on both the first signal path and the second signal path. In this mode, maximum differential signal strength is achieved.
In some embodiments the differential amplifier is an impedance matching amplifier arranged to receive the receive signal from the antenna interface and arranged to output an amplified differential signal on the first and second signal paths. The impedance matching amplifier provides transconductance gain (i.e., voltage to current conversion). The impedance matching amplifier can be designed so that the correct impedance match is one of its characteristics, while still providing gain to the input signal (on each differential path). In preferred embodiments there is no switch upstream of the impedance matching amplifier. No such switch is required as the selectivity that allows for half-duplex or pseudo-full duplex operation is downstream of the impedance matching amplifier.
The impedance matching amplifier may have two differential halves and each differential half may comprise a transistor or multiple transistors arranged in a common-gate and/or a common-source arrangement. One way to achieve this is with a field effect transistor arranged in either common-gate or common-source configuration, with the windings of a trifilar transformer coupling the signal between at least the gate and the source, while ensuring that there is only coupling between two of its windings (which ensures stability and/or maximum gain). This arrangement allows additional characteristics, such as the turns ratio of the windings and the coupling coefficient to impact on the impedance matching. Therefore, the amplifier can be designed for both gain and impedance matching. While a trifilar arrangement is particularly convenient and area-efficient, a similar effect can also be achieved with two transformers (bifilars).
It will be appreciated that this amplifier is necessarily provided upstream of (i.e., closer to the antenna than) the switching network, and therefore, it will see the full power of the transmit signal when the transceiver is in transmit mode. Thus, this transistor (on each differential signal path) can be designed to be sufficiently robust to handle the large-signal swing from the transmitter. It will be appreciated that as this is the first amplifier in the receive path, it has not yet amplified the transmitter signal and so is the least problematic part of the receive path. The signal downstream of this amplifier has been amplified, and thus, becomes a reliability issue (i.e., risks damaging downstream components). This arrangement is of particular benefit in pulsed transceivers, e.g., pulsed, or impulse radars. In such systems (as opposed to continuous wave transceivers) the transmitter is only active for short periods of time (to transmit a pulse) before going inactive for long periods of time (the rest of the pulse repetition period). Thus, the power that must be withstood by the amplifier is short and transient and thus a sufficiently robust transistor can be incorporated without great expense. The arrangement is especially beneficial in low-power transceivers, e.g., UWB transceivers as the transmit power restrictions in the UWB band also facilitate the use of an amplifier element that is fully exposed to the full transmit power of the transmitter.
Note that the single common-gate or common-source transistor mentioned above can be replaced by multiple transistors acting as a transconductance stage. For example, the gain stage could be a circuit (commonly referred to as a Darlington pair) comprising two transistors with the source of the first transistor connected to the gate of the second transistor, and the drains of the two transistors connected. Another example being a common-source transistor and a common-gate transistor in parallel arrangement with the source of the common-gate transistor connected to the gate of the common-source transistor and with the drains of the two transistors connected via an ‘inversion’. Other multiple transistor arrangements are also possible.
The transistor of each differential half may comprise a field effect transistor and each differential half of the impedance matching amplifier may further comprise a transformer coupling the signal between the gate and the source of the field effect transistor. This coupling provides an additional gain mechanism by applying the signal at the gate to the source or vice-versa. By arranging the transformer in an inverting relationship, the gate-source voltage is increased, thereby increasing the gain of the transistor.
In some examples, the field effect transistor is in common-source arrangement and each differential half of the impedance matching amplifier comprises a transformer arranged to increase the amplitude of the signal at the gate of the field effect transistor.
In such examples, the transformer on each differential signal path may be a trifilar transformer with a primary winding connected to the source, a secondary winding connected between the gate and signal ground and a tertiary winding connected between the secondary winding and the gate, wherein the primary winding and the secondary winding are coupled in inverting relationship, wherein the secondary winding and the tertiary winding are coupled to increase voltage at the gate, and wherein there is substantially no coupling between the primary winding and the tertiary winding. With this arrangement, the coupling between the primary and secondary windings increases the gate-source voltage as discussed above, thereby providing one gain mechanism. At the same time, the coupling between the secondary and tertiary windings further increases the gate voltage (and therefore also the gate-source voltage), thereby providing an additional gain mechanism. At the same time, as the input impedance of the arrangement depends upon both the transconductance of the transistor and the turns ratios of the transformer, it is possible to achieve good impedance matching via a well-defined input impedance as well as high gain. More details of this type of arrangement can be found in WO2018/033743, the entire contents of which are incorporated herein by reference. A similar effect may be achieved by using two bifilar transformers instead of a trifilar. This may be achieved with one bifilar providing coupling between the source and the gate (equivalent to the primary and secondary of the trifilar), and one bifilar providing coupling to increase the gate voltage (equivalent to the secondary and tertiary of the trifilar).
In other examples, the field effect transistor may be in common-gate arrangement and each differential half of the impedance matching amplifier may comprise a transformer coupling the signal between the source and the drain of the field effect transistor. This source-drain coupling provides an additional gain mechanism by applying the signal (current) sensed at the drain back to the source. By arranging the transformer in a non-inverting relationship, the drain-source current is increased, thereby increasing the gain of the transistor.
In such examples, the transformer on each differential signal path may be a trifilar transformer with a primary winding connected to the source, a secondary winding connected to the gate and a tertiary winding connected to the drain, wherein the primary winding and the secondary winding are coupled in an inverting relationship and wherein the primary winding and the tertiary winding are coupled in non-inverting relationship, and wherein there is substantially no coupling between the secondary winding and the tertiary winding. With this arrangement, the coupling between the primary and secondary windings increases the gate-source voltage as discussed above, thereby providing one gain mechanism. At the same time, the coupling between the primary and tertiary windings increases the drain-source current, thereby providing an additional gain mechanism. At the same time, as the input impedance of the arrangement depends upon both the transconductance of the transistor and the turns ratios of the transformer, it is possible to achieve good impedance matching via a well-defined input impedance as well as high gain. More details of this type of arrangement can be found in WO2019/086853, the entire contents of which are incorporated herein by reference. A similar effect may be achieved by using two bifilar transformers instead of a trifilar. This may be achieved with one bifilar providing coupling between the source and the gate (equivalent to the primary and secondary of the trifilar), and one bifilar providing coupling between the source and the drain (equivalent to the primary and tertiary of the trifilar).
According to another aspect of the invention, there is provided a transceiver comprising: a transmitter circuit, an antenna, a transceiver circuit as discussed above (optionally including any of the preferred or optional features also discussed above). The transmitter circuit may comprise an impulse or pulse generator.
According to another aspect of the invention, there is provided a pulsed radar comprising a transceiver as discussed above.
According to another aspect of the invention, there is provided a method of duplex operation of a differential transceiver circuit via a single antenna interface, wherein the transceiver circuit comprises:
All of the preferred and optional features described above in relation to the apparatus may equally be applied in relation to the method and therefore further description thereof is omitted here.
Certain preferred embodiments of the invention will now be described, by way of example only, and with reference to the accompanying drawings in which:
A differential filter 320 is connected to the differential antenna 310. The differential filter 320 is bidirectional such that it filters the incoming receive signal from the antenna 310 and also filters the transmit signal from transmitter 330 before passing it to the antenna 310. The type of filter and frequency response will depend on the field of operation of the circuit, but in most cases the filter 320 will be a high pass filter or a band pass filter, optionally with one or more notches to exclude undesired interferers. In the case of UWB applications such as UWB pulsed radars, the filter 320 may be designed to ensure that the transmitted signal conforms to the regulatory frequency mask (e.g., 3.1-10.6 GHz in the USA).
Receive signal that passes through the filter 320 then passes to a differential low-noise amplifier (LNA) 340 which amplifies the signal for improved processing by downstream components. In this document the term “downstream” is used with respect to the receive signal such that the LNA 340 is downstream from the filter 320 which is in turn downstream from the antenna 310.
A differential transmitter 330 is connected between the differential filter 320 and the differential LNA 340 such that it can provide signals 331, 332 onto the first differential signal path 351 and the second differential signal path 352 which then pass through the differential filter 320 and are transmitted from the antenna 310. It will be appreciated that this filter connection arrangement corresponds to that shown in
Downstream of the differential LNA 340,
Alongside the main differential signal paths 351, 352,
The switching network 380 is provided on the second differential signal path 352 downstream of the LNA 340 and is capable of diverting the signal on the second differential signal path 352 to ground (note that this only needs to be a signal ground rather than a DC ground, so it can be a connection to a power rail such as Vdd). More generally, signal ground can be any ground to which the signal can be dissipated. This may be a positive or negative voltage rail, an AC ground, or any other ground connection of the circuit. This leaves the second differential signal path 352 downstream of the switching network 380 disconnected from the rest of the receive architecture (i.e., disconnected from the antenna 310, filter 320 and LNA 340. Diverting the second differential signal path 352 to ground therefore also changes the receiver from differential to single-ended (as receive signal is now only present on the first differential signal path 351). In place of the diverted signal on the second differential signal path 352, the injection circuit provides the amplified copy signal 333 which should match exactly the first transmit signal 331 from the differential transmitter 330 that has passed through the LNA 340. Therefore, at this point in the transceiver circuit 300 (i.e., at the input to the differential output block (e.g., ADC 350), both the first differential signal path 351 and the second differential signal path 352 have identical (or very nearly identical) copies of the amplified first transmit signal 331. Any downstream processing that has high common-mode rejection will eliminate these identical signals and all that is left will be any receive signal present on the first differential signal path 351.
Although this process results in the loss of half the differential receive signal that is received by the differential antenna 310 (i.e., the loss of the half that is diverted to ground by the switching network 380), the big advantage of this transceiver circuit is that it can continue to receive even while transmitting. Thus, the transceiver circuit 300 can operate in a pseudo-full-duplex mode. We refer to this as pseudo-full-duplex rather than full-duplex as the circuit 300 needs to throw away half the received signal during the transmit pulse. Notably, this pseudo-full-duplex operation is all possible with a single differential antenna 310 rather than the two separate antennae that are normally used for full duplex operation.
When the transceiver 300 is not transmitting (which may be most of the time in a pulsed system such as a pulsed radar), the switching network 380 can be switched to not divert the signal to ground, e.g., to connect the second differential signal path 352 to the output (e.g., output block 350). In this mode of operation, the receive signal is received and processed fully-differentially throughout the path from antenna 310 to output 350 and therefore preserves the full signal swing of the received signal for optimal processing. In this mode the injection circuit has no effect as no copy signal 333 is produced by the transmitter 330.
The inputs at Port 0 and Port 1 are the differential input to the differential LNA 340. In
At the output of the amplifier 340 (i.e., at the drain of M1), a switching network 380 is provided which has a first circuit branch 381 connecting the output of the amplifier to the load (represented here by inductors L, i.e., the transceiver circuit output) and a second circuit branch 382 which diverts the output of the amplifier to a signal ground (in this case the supply rail Vdd). The first circuit branch 381 comprises a first switch 383 in series with a first buffer element 384. The second circuit branch 382 comprises a second switch 385 in series with a second buffer element 396. Each of the buffer elements 384, 386 is arranged in common-gate arrangement such that they are always-ON. The first buffer element 384 provide a high output impedance and good reverse isolation such that the load does not affect the biasing (and thus impedance matching) of the amplifier 340. The first switch 383 and the second switch 385 provide the means by which to select whether to divert or not divert the amplifier output to the signal ground node. When the first switch 383 is ON and the second switch 385 is OFF, the amplifier output (and thus the second differential signal path 352) is connected to the load (transceiver circuit output). When the first switch 383 is OFF and the second switch 385 is ON, the amplifier output (and thus the second differential signal path 352) is connected to the signal ground node (e.g., Vdd). The first switch 383 is identical to the second switch 385 and the second buffer element 386 is identical to the first buffer element 384. Identical here means the same characteristics such as size and strength. The two circuit branches 381, 382 are identical so that the amplifier 340 always sees an identical load regardless of which path is connected. This ensures that the biasing of the amplifier 340 (and thus its impedance matching) is not affected by switches between the transmit mode and the receive mode, i.e., when the switching network 380 changes state.
While the main function of the switching network is to select one path to connect the amplifier output to (i.e., so that one switch is ON and the other is OFF), it will be appreciated that it is also possible to switch both the first switch 383 and the second switch 385 ON so as to divide the signal with half going to ground and half going to the transceiver circuit output. Such operation may be useful in receive mode if a particularly strong signal is amplified too much by the amplifier 340. Connecting both circuit branches 381, 382 in parallel provides a degree of gain control to reduce the signal amplitude at the transceiver circuit output.
It will be appreciated that the structure at the output of transistor M2 on the first differential signal path is identical to that described above and is therefore not described further here, except to note that the switching network on this path is generally not used for diverting the signal unless it is desired to switch the whole receiver side off (e.g., for half-duplex operation). The switching network here still has functionality though as it provides symmetry with the switching network on the second differential signal path.
The injection circuit 390 is shown from the input at Port 3 (which takes the copy 333 of the first transmit signal 331 from the transmitter) to the connection at the node on first circuit branch 381 between the first switch 383 and the first buffer element 384 where the injection signal is injected onto the second differential signal path 352 downstream of the first switch 383. The injection circuit 390 has components identical to those on the second differential signal path 352 as described above. Thus, the injection circuit 390 includes an amplifier which comprises a field effect transistor M3 in common-source arrangement with a trifilar transformer X1 connected to its terminals. The transistor M3 is identical to transistor M1 and the windings of the trifilar transformer X1 are identical to those of transformer T1, i.e., T1,p=X1,p, T1,s=X1,s, T1,t=X1,t. As the amplifier components are identical on the injection circuit 390 to those on the second differential signal path 352, the outputs should be identical. Notably, the amplifier M2 and the trifilar windings connected to it are also identical to those of M1 and M3 so that a transmit signal sent along any of these three routes should be processed (e.g., amplified) identically.
As indicated in
The switches 383 and 385 on the second signal path 352 are controlled by control signals ϕ2 and ϕ1 respectively. The corresponding switches on the first signal path are controlled by control signals ϕ4 and ϕ5 respectively. The switch 388 on the injection circuit 390 is controlled by control signal ϕ3. All of these control signals may be generated by controller 395.
For normal receive mode operation, the injection circuit is not required, so ϕ3 is ‘low’ (OFF). The signals on both differential signal arms 351, 352 are connected to the output to pass receive signal, so ϕ2 and ϕ4 are ‘high’ (ON). No signal is to be diverted to ground, so ϕ1 and ϕ5 are ‘low’ (OFF).
For full-duplex or pseudo-full-duplex mode operation, the first differential signal path passes the signal as normal, with no diversion to ground, so control signal ϕ5 is ‘low’ (OFF) and control signal ϕ4 is ‘high’ (ON). The second differential signal path 352 diverts the received signal to signal ground, so control signal ϕ2 is ‘low’ (OFF), while control signal ϕ1 is ‘high’ (ON). The injection circuit 390 is active to inject the copy signal 333 onto the second signal path 352 so control signal ϕ3 is ‘high’ (ON). The circuit can also be operated in half-duplex mode if desired. For half-duplex mode operation, the injection circuit 390 is not used and so control signal ϕ3 is ‘low’ (OFF). During receive mode, the control signals ϕ2 and ϕ4 are ‘high’ (ON) so as to pass the receive signal, while control signals ϕ1 and ϕ5 can be either ‘low’ (OFF) for full receive mode or ‘high’ (ON) for gain control mode. During transmit mode, the receiver is simply blocked and so signals ϕ2 and ϕ4 are ‘low’ (OFF), and signals ϕ1 and ϕ5 can be either ‘low’ (OFF) or ‘high’ (ON). Only for the latter is the amplifier impedance matched (i.e., it sees proper biasing conditions) and therefore this option is preferred in some embodiments.
In
It will be appreciated that variations and modifications of the above circuits may be made without departing from the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2118014.6 | Dec 2021 | GB | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2022/085695 | 12/13/2022 | WO |
