Claims
- 1. A receiver comprising:an FM tuner having an FM mixer for converting the frequency of an FM signal; a double conversion type AM tuner having a first AM mixer for up-converting the frequency of an AM signal and down-converting the frequency of the AM signal; and a PLL circuit having a crystal oscillator, a first VCO for generating an output signal to be applied to said FM mixer on the basis of the outcome of comparing the output signal of said crystal oscillator and that of said FM mixer and a second VCO for generating an output signal to be applied to said first AM mixer on the basis of the outcome of comparing the output signal of said crystal oscillator and that of said first AM mixer; wherein said crystal oscillator includes a first oscillation circuit, a second oscillation circuit having a loop gain higher than the first oscillation circuit and a control circuit for activating at least said second oscillation circuit for a predetermined period of time after the start and inactivating said second oscillation circuit after the predetermined period of time, while keeping said first oscillation circuit activated; the output terminals of said first and second oscillation circuits being connected commonly and positively fed back.
- 2. A receiver according to claim 1, whereinsaid control circuit is constituted by a one-shot multi-vibrator for controlling the operation of the bias circuits adapted to bias said first and second oscillation circuits respectively.
- 3. A receiver according to claim 1, whereinsaid control circuit is constituted by a timer for controlling the operation of the bias circuits adapted to bias said first and second oscillation circuits respectively.
- 4. A receiver according to claim 1, whereinsaid first oscillation circuit is controlled by an ALC (automatic level controller).
- 5. A receiver according to claim 1, whereinsaid first and second oscillation circuits are constituted by differential amplifiers.
- 6. A receiver according to claim 1, whereinsaid FM tuner, said AM tuner and said PLL circuit are contained in a single chip.
Priority Claims (2)
Number |
Date |
Country |
Kind |
9-152418 |
Jun 1997 |
JP |
|
9-251152 |
Sep 1997 |
JP |
|
Parent Case Info
This application is a division of application Ser. No. 09/089,504 filed on Jun. 3, 1998, now U.S. Pat. No. 6,373,398.
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