Claims
- 1. A method comprising:
receiving a current transfer request to store data in a first in first out (FIFO) memory, the data to be retrieved using a bus, the current transfer request specifying a transfer amount for the data to be stored in the FIFO memory; and initiating retrieval and storage of the data into the FIFO memory, only if the transfer data amount combined with a previously reserved data amount has a predetermined relationship with an available FIFO space.
- 2. The method of claim 1, wherein the previously reserved amount comprises a reserved FIFO space corresponding to a previous transfer request, the method further comprising:
decrementing the reserved FIFO space as data corresponding to the previous transfer request is received and stored in the FIFO memory; decrementing the available FIFO space as data is written into the FIFO memory; and incrementing the available FIFO space as data is read out of the FIFO memory.
- 3. The method of claim 2, wherein the FIFO memory stores tags to distinguish stored data corresponding to the previous transfer request from stored data corresponding to the current transfer request.
- 4. The method of claim 3, wherein the previously reserved amount further comprises a programmable FIFO buffer zone.
- 5. The method of claim 4, wherein the programmable FIFO buffer zone is programmed to a negative value for FIFO memory sharing, and the predetermined relationship is that the transfer data amount plus the previously reserved data amount is less than or equal to the available FIFO space.
- 6. The method of claim 4, wherein the bus comprises a system-interconnect bus.
- 7. The method of claim 6, wherein the system-interconnect bus comprises a Peripheral Component Interconnect Extended bus.
- 8. A method comprising:
identifying one or more data writing rates for data to be received from interleaved multiple concurrent transactions and written into a FIFO memory having a programmable buffer zone; identifying one or more data reading rates for data to be read from the FIFO memory; and setting a buffer zone size for the programmable buffer zone of the FIFO memory based upon the identified one or more data writing rates and the one or more data reading rates.
- 9. The method of claim 8, wherein identifying one or more data writing rates comprises identifying one or more data writing rates for data to be received over a system-interconnect bus.
- 10. The method of claim 9, wherein setting the buffer zone size comprises setting the buffer zone size to a negative number.
- 11. The method of claim 10, wherein identifying one or more data reading rates comprises identifying two or more data reading rates.
- 12. The method of claim 11, wherein the system-interconnect bus comprises a Peripheral Component Interconnect Extended bus.
- 13. The method of claim 12, wherein said identifying one or more data writing rates and said identifying one or more data reading rates comprises identifying default rates.
- 14. A first in first out memory comprising:
memory circuitry; and control circuitry coupled with the memory circuitry, the control circuitry including difference circuitry to track available space in the memory circuitry, transfer length input lines to receive memory space requests for multiple data transfers, and a ready output line to indicate whether a sum of the memory space requests exceeds the available space.
- 15. The memory of claim 14, wherein the memory circuitry includes control bits and data bits.
- 16. The memory of claim 15, wherein the control circuitry further includes one or more buffer input lines to receive a buffer zone size, and wherein the ready output line indicates whether a sum of the memory space requests and the buffer zone size exceeds the available space.
- 17. The memory of claim 16, further comprising data compression circuitry and data decompression circuitry.
- 18. The memory of claim 16, wherein the control circuitry further includes a register set to hold the received buffer zone size, wherein the register set includes programmable bit patterns to designate large variations in buffer zone size.
- 19. The memory of claim 16, wherein the memory circuitry comprises a dual port random access memory.
- 20. Circuitry comprising:
means for receiving a current transfer request to store data in a FIFO memory, the data to be retrieved using a bus, the current transfer request specifying a transfer amount for the data to be stored in the FIFO memory; and means for initiating retrieval and storage of the data into the FIFO memory, only if the transfer data amount plus a previously reserved data amount is less than or equal to an available FIFO space.
- 21. The circuitry of claim 20, further comprising means for storing tags to distinguish stored data corresponding to a previous transfer request from stored data corresponding to a current transfer request.
- 22. The circuitry of claim 21, further comprising means for programming a FIFO buffer zone.
- 23. The circuitry of claim 22, further comprising means for compressing and decompressing data.
- 24. A bus adapter comprising:
a processor; an adapter memory coupled with the processor; a bus interface coupled with the adapter memory through a first in first out memory, the bus interface supporting multiple concurrent data transfers; a storage connection coupled with the adapter memory; the first in first out memory coupled with the bus interface and with the adapter memory, the first in first out memory comprising memory circuitry, and control circuitry including difference circuitry to track available space in the memory circuitry, transfer length input lines to receive memory space requests for multiple data transfers, one or more buffer input lines to receive a buffer zone size, and a ready output line to indicate whether a sum of the memory space requests and the buffer zone size exceeds the available space; and management circuitry coupled with the first in first out memory, the management circuitry to provide the memory space requests to the transfer length input lines and coordinate initiation of the multiple data transfers.
- 25. The bus adapter of claim 24, wherein the memory circuitry includes control bits and data bits to store tags identifying data transactions stored in the memory circuitry.
- 26. The bus adapter of claim 25, wherein the bus interface conforms to a Peripheral Component Interconnect Extended bus standard.
- 27. The bus adapter of claim 26, wherein the storage connection comprises a network interface conforming to a Fibre Channel standard.
- 28. The bus adapter of claim 27, wherein the management circuitry comprises a register block to store memory space requests that are skipped by the first in first out memory.
- 29. The bus adapter of claim 28, wherein the first in first out memory further comprises data compression circuitry and data decompression circuitry.
- 30. A system comprising:
a programmable machine including a system-interconnect bus that supports interleaved multiple concurrent transactions; a storage area network; and a bus adapter coupled with the system-interconnect bus and the storage area network, the bus adapter comprising a processor, an adapter memory coupled with the processor, a bus interface coupled with the system-interconnect bus and coupled with the adapter memory through a first in first out memory comprising memory circuitry, and control circuitry including difference circuitry to track available space in the memory circuitry, transfer length input lines to receive memory space requests for multiple data transfers, and a ready output line to indicate whether a sum of the memory space requests exceeds the available space.
- 31. The system of claim 30, wherein the memory circuitry includes control bits and data bits to store tags identifying data transactions stored in the memory circuitry.
- 32. The system of claim 31, wherein the control circuitry further includes one or more buffer input lines to receive a buffer zone size, and wherein the ready output line indicates whether a sum of the memory space requests and the buffer zone size exceeds the available space.
- 33. The system of claim 32, wherein the control circuitry further includes a register set to hold the received buffer zone size, wherein the register set includes programmable bit patterns to designate large variations in buffer zone size.
- 34. The system of claim 32, wherein the system-interconnect bus comprises a Peripheral Component Interconnect Extended bus.
- 35. The system of claim 32, wherein the storage area network comprises a Fibre Channel network and a plurality of mass storage devices.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of the priority of U.S. Provisional Application Serial No. 60/339,643, filed Dec. 11, 2001 and entitled “PCI/X TRANSMIT FIFO”.
Provisional Applications (1)
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Number |
Date |
Country |
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60339643 |
Dec 2001 |
US |