Various embodiments generally relate to a semiconductor technology, and, more particularly, to a receiving device, a transmitting device, and a semiconductor device and system using the same.
An electronic apparatus may consist of a large number of electronic components. Among other things, a computer system may include therein many semiconductor devices, which are semiconductor based electronic components. When semiconductor devices receive and transmit electrical signals with low signal voltages and high frequencies, it is important for receiving/transmitting devices to mitigate signal distortion. For example, the receiving/transmitting devices may include a decision feedback equalizer (DFE) to compensate for signal distortion.
In an embodiment, a receiving device may include a buffer, a summer circuit, a first delay cell, and a second delay cell. The buffer may receive an external signal. The summer circuit may sum an output of the buffer, a first feedback signal, and a second feedback signal. The first delay cell may set its delay amount based on a delay control voltage, and may generate the first feedback signal by delaying an output of the summer circuit. The second delay cell may set its delay amount based on the delay control voltage, and may generate the second feedback signal by delaying the first feedback signal.
In an embodiment, a transmitting device may include a first delay cell and a driver. The first delay cell may set its delay amount based on a delay control voltage, and may delay an internal signal. The driver may drive an output node based on an output of the first delay cell.
Hereinafter, a receiving device, a transmitting device, and a semiconductor device and system using the same will be described below with reference to the accompanying drawings through various examples of embodiments.
The first and second semiconductor devices 110 and 120 may be coupled to each other through a signal transmission line 130. The first semiconductor device 110 may include a pad 111, and the pad 111 may be coupled to the signal transmission line 130. The second semiconductor device 120 may include a pad 121, and the pad 121 may be coupled with the signal transmission line 130. Here, the pads 111 and 121 are conductor portions of the semiconductor devices provided to make an electrical connection to an external element. The signal transmission line 130 may be a channel, a link or a bus. The first semiconductor device 110 may include a transmitting device 112 and a receiving device 113. The transmitting device 112 may generate an output signal according to an internal signal of the first semiconductor device 110, and may transmit the output signal to the second semiconductor device 120 through the signal transmission line 130. The receiving device 113 may receive a signal transmitted from the second semiconductor device 120 through the signal transmission line 130, and may generate an internal signal. Similarly, the second semiconductor device 120 may include a transmitting device 122 and a receiving device 123. The transmitting device 122 may generate an output signal according to an internal signal of the second semiconductor device 120, and may transmit the output signal to the first semiconductor device 110 through the signal transmission line 130. The receiving device 123 may receive a signal transmitted from the first semiconductor device 110 through the signal transmission line 130, and generate an internal signal.
The signal transmission line 130 may be a bus, a link or a channel capable of transmitting various signals. The signal transmission line 130 may transmit various signals such as, for example, a request, a command signal, an address signal, data and a strobe signal. The transmitting devices 112 and 122 and the receiving devices 113 and 123 may perform a certain operation to transmit/receive electrical signals without error. For example, the transmitting devices 112 and 122 and the receiving devices 113 and 123 may correct potential errors in the signal transmitted through the signal transmission line 130 or potential errors in the signal received through the signal transmission line 130. The transmitting devices 112 and 122 and the receiving devices 113 and 123 may include a decision feedback equalizer (DFE) to correct a signal transmitted or received through the signal transmission line 130.
The decision feedback equalizer 220 may correct the output of the buffer 210 and generate an internal signal INTS. The internal signal INTS may be applied to an internal circuit of a semiconductor device that includes the receiving device 200. The decision feedback equalizer 220 may remove a post-cursor component of the signal buffered by the buffer 210, and may generate the internal signal INTS which has a precise waveform.
The decision feedback equalizer 220 may include a summer circuit 221, a first delay cell 222, and a second delay cell 223. The summer circuit 221 may sum the signal buffered by the buffer 210, a first feedback signal FDS1, and a second feedback signal FDS2.
The first delay cell 222 may delay the output of the summer circuit 221 and generate the first feedback signal FDS1. The first delay cell 222 may delay the output of the summer circuit 221 based on a delay control voltage DCV. The delay control voltage DCV may be a bias voltage generated to control a delay amount of the first delay cell 222. The delay control voltage DCV may have a voltage level that allows the first delay cell 222 to have a delay amount corresponding to a unit of delay time. The unit of delay time may be a time corresponding to, for example, one half cycle or one cycle of a clock signal. The first delay cell 222 may not receive a clock signal. The first delay cell 222 may generate the first feedback signal FDS1, instead of receiving a clock signal, by delaying the output of the summer circuit 221 by a time corresponding to a predetermined cycle of the clock signal based on the delay control voltage DCV.
The second delay cell 223 may delay the first feedback signal FDS1 and generate the second feedback signal FDS2. Similarly to the first delay cell 222, the second delay cell 223 may delay the first feedback signal FDS1 based on the delay control voltage DCV. The second delay cell 223 may have substantially the same circuit structure as the first delay cell 222. Accordingly, the second delay cell 223 may generate the second feedback signal FDS2 by delaying the first feedback signal FDS1 by a time corresponding to a predetermined cycle of the clock signal based on the delay control voltage DCV. The second feedback signal FDS2 may be provided as the internal signal INTS.
In
As described above, the receiving device 200 may include the first and second delay cells 222 and 223, and the amount of delay of the first and second delay cells 222 and 223 may be set based on the delay control voltage DCV. The delay cell of a general decision feedback equalizer may delay a signal input thereto by using a clock signal. Here, the clock signal may be generated by a phase-locked loop circuit or by a delay-locked loop circuit. Therefore, the clock signal should be transmitted to a receiving device through a signal transmission line. This requires more circuit area in a semiconductor device, and power consumption increases due to current consumption of the signal transmission line. Instead of using a clock signal, the receiving device 200 in accordance with an embodiment may set the amount of delay of the first and second delay cells 222 and 223 by using the delay control voltage DCV such as a bias voltage.
The driver 520 may drive an output node ON based on the output of the first delay cell 511. An output signal EXS of the transmitting device 500 may be generated from the output node ON. The output signal EXS may be output to an external device through the pad 111 or 121 and through the signal transmission line 130 as illustrated in
The transmitting 500 may further include a second delay cell 512. The second delay cell 512 may receive the output of the first delay cell 511, and may delay the output of the first delay cell 511. The second delay cell 512 may receive the delay control voltage DCV. The second delay cell 512 may delay the output of the first delay cell 511 by the unit of delay time based on the delay control voltage DCV, and may output an output signal. The second delay cell 512 may have substantially the same structure as the first delay cell 511.
The transmitting device 500 may further include a first equalizing circuit 531 and a second equalizing circuit 532. The first equalizing circuit 531 may equalize a signal being output through the output node ON based on the internal signal INTS. The second equalizing circuit 532 may equalize a signal being output through the output node ON based on the output of the second delay cell 512. For example, when the internal signal INTS is at a high level, the driver 520 may drive the output node ON after a delay time corresponding to the unit of delay time. Here, this delay is produced by the first delay cell 511. The first equalizing circuit 531 may drive the output node ON to a low level before the driver 520 drives the output node ON. The second equalizing circuit 532 receives the internal signal INTS after a delay corresponding to two units of delay time, and the second equalizing circuit 532 may drive the output node ON to the low level after the driver 520 drives the output node ON. Here, the delay corresponding to two units of delay time may be produced by the first and second delay cells 511 and 512. As the first and second equalizing circuits 531 and 532 drive the output node ON to a voltage level opposite to the internal signal INTS before and after the driver 520 drives the output node ON based on the internal signal INTS, it is possible to generate the output signal EXS precisely and stably. When the internal signal INTS is at a low level, the first and second equalizing circuits 531 and 532 may drive the output node ON to a high level before and after the driver 520 drives the output node ON. Unlike the delay cell of a general transmitting device, which sets its delay based on a clock signal, the first and second delay cells 511 and 512 of the transmitting device 500 in accordance with an embodiment may set their delay based on the delay control voltage DCV such as a bias voltage, instead of a clock signal.
While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the receiving device, the transmitting device, and the semiconductor device and system using the same described herein should not be limited based on the described embodiments.
Number | Date | Country | Kind |
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1020160140315 | Oct 2016 | KR | national |
The present application is a divisional application for U.S. patent application Ser. No. 15/443,665 and claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2016-0140315 filed on Oct. 26, 2016, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.
Number | Date | Country | |
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Parent | 15443665 | Feb 2017 | US |
Child | 16116724 | US |