BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing an example of a hardware configuration of a personal computer to which the present invention is applied;
FIG. 2 is a flow diagram illustrating processing of packet communication by the personal computer of FIG. 1;
FIG. 3 is a diagrammatic view illustrating a relationship between a jumbo packet and packets;
FIG. 4 is a table illustrating a process of producing an IP header;
FIG. 5 is a table illustrating a process of producing a TCP header;
FIG. 6 is a flow diagram illustrating processing of packet reception by the personal computer of FIG. 1;
FIG. 7 is a block diagram showing an example of a functional configuration of the personal computer of FIG. 1;
FIG. 8 is a flow chart illustrating a data reception process by the personal computer of FIG. 1;
FIG. 9 is a flow chart illustrating details of a jumbo packet function initialization process illustrated in FIG. 8;
FIG. 10 is a view illustrating a jumbo packet register shown in FIG. 7;
FIG. 11 is a flow chart illustrating a jumbo packet register setting process illustrated in FIG. 9;
FIG. 12 is a flow chart illustrating a jumbo packet reception process illustrated in FIG. 8; and
FIG. 13 is a block diagram showing a configuration of a general personal computer.
Patent Application
20070171829
