BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing an example of a structure of a receiver according to the present invention.
FIG. 2 is a diagram showing another example of a structure of the receiver according to the present invention.
FIG. 3 is a diagram showing an example of a general structure of a conventional receiver that receives ground wave digital broadcasting for a mobile unit.
FIG. 4 is a diagram showing an example of a structure of a tuner circuit portion that is provided to the reception apparatus shown in FIG. 3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, an embodiment of the present invention will be described with reference to the attached drawings. A receiver that receives ground wave digital broadcasting for a mobile unit is exemplified as the receiver according to the present invention in the following description. An example of a structure of a receiver according to the present invention that receives ground wave digital broadcasting for a mobile unit is shown in FIG. 1. Note that the same part as that in FIGS. 3 and 4 is denoted by the same numeral in FIG. 1, so that detailed description thereof will be omitted.
The receiver shown in FIG. 1 according to the present invention adopts the diversity method and the single conversion method in the same manner as the conventional receiver shown in FIG. 3.
The receiver shown in FIG. 1 according to the present invention has a structure in which the PLL circuits 17 and 37 and the voltage controlled oscillators 18 and 38 are eliminated from the conventional receiver shown in FIG. 3 including the tuner circuit portion having the structure shown in FIG. 4, and a PLL circuit 51 and a voltage controlled oscillator 52 are added to the same, so that two reception systems share the PLL circuit 51 and the voltage controlled oscillator 52.
An operation of the receiver shown in FIG. 1 according to the present invention having the structure described above will be described only about differences with the conventional receiver shown in FIG. 3 that includes the tuner circuit portion having the structure shown in FIG. 4.
The PLL circuit 51 generates a control voltage corresponding to a received channel based on the reference signal delivered from the reference signal oscillator 7 and a local oscillation signal delivered from the voltage controlled oscillator 52. The voltage controlled oscillator 52 generates the local oscillation signal of a local oscillation frequency (that is a sum of the reception frequency and a frequency of the intermediate frequency signal) based on the control voltage from the PLL circuit 51, and the generated local oscillation signal is supplied to the mixers 19 and 39.
The mixer 19 mixes the output signal of the interstage circuit 16 and the local oscillation signal from the voltage controlled oscillator 52 so as to generate the intermediate frequency signal. The intermediate frequency signal delivered from the mixer 19 is amplified by the amplifier 20 and then is supplied to a SAW (Surface Acoustic Wave) filter 21 disposed after. In addition, the mixer 39 mixes the output signal of the interstage circuit 36 and the local oscillation signal from the voltage controlled oscillator 52 to as to generate the intermediate frequency signal. The intermediate frequency signal delivered from the mixer 39 is amplified by the amplifier 40 and is supplied to a subsequent SAW (Surface Acoustic Wave) filter 41.
Since the receiver shown in FIG. 1 according to the present invention has a structure in which the PLL circuit 51 and the voltage controlled oscillator 52 are shared by two reception systems, one PLL circuit and one voltage controlled oscillator can be eliminated from the conventional receiver shown in FIG. 3 including the tuner circuit portion having the structure shown in FIG. 4. Therefore, cost reduction and space saving can be achieved.
Next, another example of a structure of a receiver according to the present invention that receives ground wave digital broadcasting for a mobile unit is shown in FIG. 2. Note that the same part as that in FIG. 1 is denoted by the same numeral in FIG. 2, so that detailed description thereof will be omitted.
The receiver shown in FIG. 2 according to the present invention distributes the reference signal delivered from the reference signal oscillator 7 into three. One of them is supplied to the PLL circuit 51, another is supplied to the demodulation circuit 5 after its signal level is secured by an amplifier 53, and the other is supplied to the demodulation circuit 6 after its signal level is secured by an amplifier 54. If a frequency of the reference signal delivered from the reference signal oscillator 7 does not match the clock frequency necessary for the demodulation circuits 5 and 6, a multiplier or a divider should be disposed before or after each of the amplifiers 53 and 54 so that a clock signal of a clock frequency necessary for the demodulation circuits 5 and 6 can be obtained.
The receiver shown in FIG. 2 according to the present invention does not need a special clock signal source for generating a clock signal to be the reference signal of the demodulation circuit. On the contrary, the receiver shown in FIG. 1 according to the present invention or the conventional receiver shown in FIG. 3 including the tuner circuit portion having the structure shown in FIG. 4 is provided with a special clock signal source for generating a clock signal to be the reference signal of the demodulation circuit thought it is not shown in the drawings. Therefore, the receiver shown in FIG. 2 according to the present invention can achieve further cost reduction and space saving compared with the receiver shown in FIG. 1 according to the present invention.
In addition, in order to achieve further cost reduction and space saving in the receiver shown in FIG. 1 or 2 according to the present invention, the mixers 19 and 39, the amplifiers 20 and 40, the PLL circuit 51, the voltage controlled oscillator 52, and the IFAGC amplifiers 22 and 42 are integrated into a single IC package.
As to the receiver shown in FIG. 1 or 2 according to the present invention, the reception circuit is made up of the tuner input terminals 11 and 31, the band pass filters 12 and 32, the broadband amplifiers 13 and 33, the input circuits 14 and 34, the RFAGC amplifiers 15 and 35, the interstage circuits 16 and 36, the mixers 19 and 39, the reference signal oscillator 7, the PLL circuit 51, the voltage controlled oscillator 52, the amplifiers 20 and 40, the SAW filters 21 and 41, the IFAGC amplifiers 22 and 42, the tuner output terminals 23, 24, 43 and 44.
The receiver shown in FIG. 1 or 2 according to the present invention has the structure in which the PLL circuit 51 and the voltage controlled oscillator 52 are shared by two reception systems, so it is easy to house the two reception systems in a single case. Therefore, it is preferable to house the reception circuit in a single case.
In addition, since the reception circuit described above is a circuit that delivers the intermediate frequency, a user who handles the reception circuit as a component can freely select the demodulation circuits 5 and 6 that are disposed after the reception circuit.
In addition, from a viewpoint of cost reduction and space saving, it is possible to integrate the reception circuit and the demodulation circuits 5 and 6 into a single IC package. In this case, it is preferable to mount the reception circuit and the demodulation circuits 5 and 6 on individual chips that constitute an IC package of MCP (Multi Chip Package), so that it is relatively easy to select the demodulation circuits 5 and 6 that are disposed after the reception circuit.
In addition, it is preferable to mount the reception circuit and the demodulation circuits 5 and 6 on both sides or on a single side of a mother board of a final product (the receiver).
In addition, as to the receiver shown in FIG. 1 or 2 according to the present invention, it is preferable that the reception circuit, the demodulation circuit 5 and the MPEG decoder 8 have a module structure. Thus, it becomes easier to manage total cost of the reception circuit, the demodulation circuit 5 and the MPEG decoder 8. In addition, the module structure enables generalization so that cost reduction can be achieved, and it becomes easier for designers of set manufacturers or TV manufacturers to use.
Note that although the receiver that utilizes the single conversion method is exemplified in the embodiment described above, it is clear that the present invention can also be applied to a receiver that uses a double conversion method or a receiver that uses a direct conversion method.
Patent Application
20080051049
