The present invention relates to optoelectronic semiconductor fabrication and, more particularly, to fabrication of a recessed germanium (Ge) diode in a silicon substrate.
Demand for low cost and high density near infrared (NIR) solid-state detectors has motivated development and use of germanium on silicon (Ge/Si) heterostructures to extend the optoelectronic application of Si technology. Ge/Si structures are currently being considered for NIR P/N detectors that can be integrated with Si complementary metal-oxide-semiconductor (CMOS) devices. Various research demonstrations of integrated Ge/Si diodes with CMOS have been made, including using sputtered polycrystalline germanium (poly-Ge) to form Ge/Si photodiodes after CMOS transistors were complete. Poly-Ge may be formed by various methods, including the use of plasma enhanced chemical vapor deposition (PECVD).
When integrating Ge on a Si substrate, such as for use as a free-space coupled, infrared (IR) photodiode detector, a substantial thickness (typically greater than 0.5 μm, and often 2 μm or more) of Ge is required. However, growing Ge on a Si surface creates large steps, which pose problems for subsequent fine geometric or lithographic planar semiconductor processing, such as placing leads on devices. Such processing typically requires step heights of less than about 1 μm.
An embodiment of the present invention provides a method for fabricating a recessed semiconductor device in a substrate. The substrate may include a first material, such as silicon or silicon-on-insulator (SOI), and an optional passivation layer on the surface of the first material. A hole is etched through the passivation layer, if present, and at least about 0.5 μm into the first material. A second material, different than the first material, is epitaxially grown in the hole. The second material may include, for example, germanium or a germanium alloy. At least a portion of the grown second material may be doped.
The second material may be grown in stages. The second material may be epitaxially grown to partially fill the hole, then the grown second material may be heated to between about 750° C. and about 900° C. or to about 850° C. The heating may take place in situ in an epitaxial reactor used to epitaxially grow the second material. After heating the second material, additional second material may be epitaxially grown in the hole. The grown second material may be heated after the additional second material is grown. The growing and heating stages may be repeated.
Doping the at least a portion of the grown second material may form a photodiode. An optical path, perpendicular to the surface of the substrate, may be provided to the photodiode.
Optionally, a third material, that is different than the first material and different than the second material, may be epitaxially grown on a surface of the second material, and at least a portion of the grown third material may be doped. The third material may include a Group 3-5 compound, such as gallium arsenide.
Before etching the hole, a passivation layer may be formed on the surface of the substrate. The total thickness of passivation material on the surface of the substrate, through which the hole is etched, and the thickness of first material, through which the hole is etched, may be related by a ratio in the range of about 1:6 to about 1:1 or in a the range of about 1:4 to about 2:3. The total thickness of passivation material on the surface of the substrate, through which the hole is etched, may be at least about 0.3 μm, and the thickness of first material, through which the hole is etched, may be at least about 0.5 μm or about 1.2 μm.
The height of a ridge on the grown second material may be reduced, such as by heating the substrate, such as to a temperature between about 750° C. and about 900° C. Optionally or alternatively, the height of the ridge on the grown second material may be reduced by chemically-mechanically planarizing (CMP) at least a portion of the grown second material.
A polysilicon-based electrode may be deposited on at least a portion of the grown second material.
Another embodiment of the present invention provides a light conversion apparatus. A substrate includes a first material and a passivation layer on the surface of the first material. A second material is recessed into the passivation layer and into the first material. The second material extends to at least about 0.5 μm into the first material, as measured from the boundary between the passivation layer and the first material. At least a portion of the second material is doped to create a semiconductor device. The light conversion apparatus also includes at least one electrical connection to the semiconductor device.
The semiconductor device may include a photodiode. A structure may define an optical path, perpendicular to the surface of the substrate, to the photodiode.
A second passivation layer may overlay at least a portion of the passivation layer and define an opening through which an optical signal may pass to the semiconductor device. As noted, the semiconductor device may include a photodiode. The at least one electrical connection may include a polysilicon-based electrode overlaying the opening defined by the second passivation layer. The at least one electrical connection may be electrically coupled to the photodiode to extract photogenerated carriers from the photodiode.
Yet another embodiment of the present invention provides a method for for fabricating a semiconductor device on a substrate that includes a first material and a passivation layer on the surface of the first material. A hole is etched through the passivation layer to the first material. A second material, different than the first material, is epitaxially grown to partially fill the hole, and then the grown second material is heated, such as to a temperature between about 750° C. and about 900° C. The heading may occur in situ in an epitaxial reactor used to epitaxially grow the second material. After heating the grown second material, the second material is further epitaxially grown in the hole. At least a portion of the grown second material may be doped.
Optionally, after further epitaxially growing the second material in the hole, the grown second material is heated. Heating and growing the second material may be repeated in stages.
The invention will be more fully understood by referring to the following Detailed Description of Specific Embodiments in conjunction with the Drawings, of which:
In accordance with the present invention, methods and apparatus are disclosed for providing a recessed germanium (Ge) region in a silicon (Si) substrate. The top of such a Ge region may be flush, or nearly flush, with the surrounding Si substrate or a passivation layer on the substrate, to facilitate subsequent semiconductor processing. However, the Ge region may be thick enough to obtain good coupling efficiencies to vertical, free-space light entering the Ge region. The Ge region may be fabricated by etching a hole through the passivation layer and into the Si substrate and then growing Ge in the hole by a selective epitaxial process.
High-speed optical communication systems typically include optical fibers to carry optical signals and photodetectors coupled to the ends of the optical fibers to detect the optical signals and to convert the optical signals into electrical signals. Group 3-5 compound semiconductor photodiodes are commonly used as the photodetectors in such contexts. Group 3-5 compound semiconductors are fabricated on non-Si substrates, because group 3-5 compound semiconductors have material, thermal, doping, fabrication and other incompatibilities with Si. However, other devices, such as bipolar transistors that are commonly used with photodetectors, are well suited for fabrication on Si or silicon-on-insulator (SOI) substrates. Thus, the group 3-5 compound photodetectors cannot be fabricated on the same substrates as the devices to which they are commonly connected.
On the other hand, Ge is compatible with Si and SOI substrates and, as noted, germanium-on-silicon (Ge/Si) heterostructures, such as Ge photodiodes, have been found to be useful in optoelectronic application. For example, Ge has an appropriate band gap and absorption length for a wide range of wavelengths used in optical communication systems. Furthermore, it would be desirable to integrate Ge photodiodes with bipolar transistors and other related devices and circuits on a common substrate.
For good coupling efficiency between an incoming optical signal and a Ge region of a photodiode, the optical signal should be able to pass through a sufficient amount of Ge. “Responsivity” is a measure of electrical current output per unit of optical input power. In general, responsivity varies with wavelength of the incident radiation. At wavelengths commonly used in communication systems, longer wavelengths typically require more Ge (“absorption length”) to generate acceptable electrical signals. For example, an optical signal having a wavelength of about 850 nm typical requires an absorption length of only about 0.2 μm. However, a 1,300 nm optical signal requires an absorption length of about 1 μm, and a 1,600 nm optical signal requires an even greater absorption length.
Many current integrated circuit (IC) processes involves fabricating advanced complementary metal-oxide-semiconductor devices on SOI substrates (CMOS on SOI). Such processes utilize very thin (often only about 0.25 μm or less thick) layers of Si. Ge structures having sufficient vertical (i.e., perpendicular to the surface of the substrate) absorption lengths cannot be fabricated in such thin layers of Si. Instead, to achieve sufficient absorption lengths, Ge is deposited in long, thin horizontal layers, and optical signals are coupled horizontally (i.e., parallel to the surface of the substrate) into the Ge. However, such coupling is difficult to achieve with high efficiency.
Optical fibers may be coupled to photodetectors using one of two methods: waveguide coupling and free-space coupling.
A Si layer 114, on which the Ge region 110 is disposed, is typically only about 0.25 μm or less in thickness. To prevent coupling of the optical signal 108 to the Si layer 114, an insulating layer 118, typically more than about 1 μm in thickness, separates the mode coupler 104 from the Si layer 114. The optical signal 108 generates electron-hole pairs in the Ge region 110, and electrodes (one of which is shown at 120) connected to N+ and P+ junctions on opposite sides (top and bottom or left and right) of the Ge region 114 collect the generated carriers.
Mode couplers/waveguides are difficult and expensive to fabricate, at least in part due to their geometries and the need to fabricate very thick optical fiber-to-waveguide couplers, as shown in
On the other hand, a vertical freespace-coupled device does not require a mode coupler/waveguide. However, the Ge region should be about 1.5 μm thick, depending on the wavelengths of interest, to provide a sufficient absorption length. Prior art methods of fabricating freespace-coupled devices involve growing Ge on a Si surface, which creates large steps that pose problems for subsequent semiconductor processing. Even waveguide-coupled devices include tall structures, such as the tall coupler portion 102 of the mode coupler/waveguide 104. Thus, both coupling methods involve tall structures, which pose problems for subsequent processing.
An optical signal 330 from an optical fiber 335 or another source (such as a laser diode, etc.; not shown) may enter the Ge region 300 and generate electron-hole pairs. An electrode 340 that is sufficiently transparent at wavelengths of interest to transmit a sufficient portion of the optical signal 330 into the Ge region 300 may cover the opening 320 in the passivation layer 325 and provide one electrical connection to the photodiode 200 to collect the photogenerated carriers. A suitable polysilicon-based, transparent electrode is described in U.S. Pat. No. 7,205,525, titled “Light Conversion Apparatus with Topside Electrode,” by John Yasaitis, issued Apr. 17, 2007, the entire contents of which are incorporated herein by reference, for all purposes. Another electrical connection (not shown) to the photodiode 200 may be made conventionally. Optionally or alternatively, one or both electrical connections may be made by an optically-opaque metallic electrode, although such an electrode should be located so as not to completely occlude the optical signal 330, such as on one side (as viewed in
In
To form the Ge region 300 (
As used herein, “recessed” means disposed in a hole. The recessed material need not, however, fill the entire hole. For example, as shown in
It is well known that selective epitaxial growth of Ge on a Si surface, such as within a ring of oxide, produces a flat-topped mesa structure with slanted sides, because some crystallographic planes grow faster than others.
However, we have discovered that growing Ge selectively in a hole etched in Si and surrounded by oxide produces better results than selectively growing Ge on a Si surface surrounded by oxide. Surprisingly, the Ge may grow to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides 700 of a mesa (
Ge selectively epitaxially grows on Si, but tends not to grow on oxide. Despite this tendency, if the surface of the Si substrate is covered with one or more layers of oxide 808 and 809, we have discovered that, surprisingly, there may be some Ge growth up or adjacent the oxide sidewall 810 in the hole. Ge that grows on the Si sidewall 804 (
The Si sidewalls 1104 and bottom 1108 of the etched hole should be prepared to provide native oxide-free silicon surfaces, on which to grow Ge. The surfaces may be conventionally prepared by a pre-bake at about 1,050° C. However, if bipolar transistors have already been formed on the substrate, the thermal budget for processing the substrate is limited. That is, there is a limit to which the temperature of the wafer should be raised. A conventional pre-bake could alter doping profiles of the bipolar transistors. The substrate temperature should, therefore, be kept below about 900° C.
To prepare the Si sidewalls 1104 and bottom 1108 without high temperature pre-baking, the Si sidewalls 1104 and bottom 1108 of the etched hole may be cleaned with hydrofluoric acid (HF), i.e., by applying a well-known HF last cleaning. HF last cleaning results in a Si surface that is free of silicon oxide and passivated with hydrogen.
Ge is then selectively grown on the sidewalls 1104 and bottom 1108 of the etched and cleaned hole, such as in a single-wafer epitaxial reactor. Stages of this growth are shown schematically in
Returning to
Returning to
When Ge is grown on Si, a heteroepitaxial junction interface is created between the Si and the grown Ge. There is an about 4% difference between the crystal lattices of Si and Ge. Consequently, defects may form at the interface. The number of these defects may be reduced by annealing. Optionally, the annealing process may involve cycling between a high and a low (such as about 650° C.) temperature at about 30-second intervals, where the high temperature is sufficiently high to cause the Ge to flow.
We have found that annealing at about 850° C. causes the Ge to flow, which may largely level out the ridge 814 and fill in the trough 816. Cyclic annealing, using a high temperature of about 850° C. and a low temperature of about 650° C., also levels the Ge.
Although much or most of the surface of the substrate may be covered with a passivation layer 808, some Ge may nucleate and form Ge “islands” on the passivation layer 808 while the Ge is grown in the hole. An example of such an island is shown at 820 (
As shown in
A fabrication process, according to one embodiment, is described in a flowchart in
At 1214, Ge is selectively epitaxially grown in the hole until the top of the grown Ge is approximately level with the top surface of the passivation layer or an expected top surface after the passivation layer is subsequently cleaned. The grown Ge may be annealed in situ within the epitaxial reactor as part of the operation 1214, or the Ge may be annealed in a separate operation 1216.
At 1220, the grown Ge region(s) may be masked to protect the regions during the subsequent cleaning operation, and then the field oxide may be cleaned with peroxide and water or another suitable cleaner to remove Ge islands that may have formed on the field oxide.
Optionally, the top surface of the grown Ge may be planarized by CMP at 1224. However, the surface of the grown Ge may be sufficiently level as a result of annealing at 1214 and/or 1216 to make planarization unnecessary.
Another passivation layer is deposited at 1228, and at 1230, an opening is etched in the passivation layer. At 1234, polysilicon is deposited to form a topside electrode. The photodiode is doped at 1238, and the polysilicon topside electrode is patterned at 1240.
As noted with respect to
After dry etching a hole and preparing the surface of the Si, Ge is selectively grown on the sidewalls and bottom of the etched and cleaned hole, as described above and as shown in
The Ge may be grown at an intermediate temperature, such as about 600° C., and the annealing may be performed at a higher temperature, such as about 800° C. or 850° C. The annealing stages may be relatively short, such as about 30 seconds, so as to avoid dopant migration. The annealing may be performed in situ in the epitaxial reactor.
Although a two-stage Ge growth process is described, any number of growth stages, interspersed with annealing stages, may be used. Furthermore, a multi-stage growth process, as described, may be used to selectively grow Ge on the surface of a Si or SOI substrate, without etching a hole.
Although growing Ge in a recess in a substrate has been described, it is also possible to grow a layer of Ge in a recess, and then to grow a third material, different than Ge, on the Ge layer, thus producing a semiconductor device with a first and a second material in the recess, as schematically illustrated in
a) shows a seed Ge layer 1500 epitaxially grown on a single-crystal Si base layer of the sidewalls 804 and bottom 800 of a recess, as described above with respect to
All or part of the remainder of the recess may be filled by growing the third material 1515 on top of the Ge 1510. The third material 1515 may be doped. Other processing operations, such as planarization, annealing, flowing, etc., may be performed as described herein to level the surface of the second material 1515. Similarly, more than two materials may be successively grown in layers (not shown) in a single recess.
Using the disclosed method, a GaAs device, such as a light-emitting diode (LED), laser diode, transistor, etc., or other semiconductor device may be fabricated on a Si, SOI or other otherwise-incompatible substrate.
SiGe processes can yield very high speed (on the order of 40-50 GHz) bipolar devices and electrical circuits, such as transimpedance amplifiers (TIAs), which are often connected to photodiodes to amplify the optically generated charges into electrical signals for further processing, and circuits for driving high-speed optical sources, such as laser diodes. Such processes typically involve structures on relatively thick (such as about 2.5 μm) Si substrates. Thus, these processes are well suited for fabricating recessed Ge photodiodes, as described herein, yielding ICs that include both photodiodes and related devices and circuits.
In accordance with an exemplary embodiment, a recessed Ge photodiode and a method for fabricating such a photodiode is provided. While specific values chosen for these embodiments are recited, it is to be understood that, within the scope of the invention, the values of all of parameters may vary over wide ranges to suit different applications. For example, other thicknesses of passivation layers and depths of holes in Si substrates may be used. Furthermore, the disclosed method of fabricating a recessed Ge structure is applicable to other structures, such as waveguide-coupled photodetectors and Ge alloy structures grown in etched recesses.
While the invention is described through the above-described exemplary embodiments, it will be understood by those of ordinary skill in the art that modifications to, and variations of, the illustrated embodiments may be made without departing from the inventive concepts disclosed herein. For example, although some aspects of fabricating a recessed device have been described with reference to a flowchart, those skilled in the art should readily appreciate that functions, operations, decisions, etc. of all or a portion of each block, or a combination of blocks, of the flowchart may be combined, separated into separate operations or performed in other orders. In addition, although a Ge photodiode that is recessed in a Si substrate has been described, the disclosed methods and structures may be used with other materials and to fabricate other types of devices. Furthermore, disclosed aspects, or portions of these aspects, may be combined in ways not listed above. Accordingly, the invention should not be viewed as being limited to the disclosed embodiment(s).
This application is a divisional of U.S. patent application Ser. No. 12/169,825, filed Jul. 9, 2008, titled “Recessed Germanium (Ge) Diode,” the entire contents of which are hereby incorporated by reference herein for all purposes.
Number | Date | Country | |
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Parent | 12169825 | Jul 2008 | US |
Child | 12712858 | US |