Patent Application
20150303548
The invention relates to semiconductor structures and, more particularly, to a reconfigurable branch line coupler and methods of designing and reconfiguring the branch line coupler.
A branch line coupler is the simplest type of quadrature coupler, since the circuitry is entirely planar. In a typical branch line coupler, two parallel transmission lines are connected together with two other parallel transmission lines. The transmission lines are λ/4 long and have two distinct characteristic impedances. A signal entering the port 1 is split into two quadrature signals on the ports 2 and 3, with the remaining port 4 fully isolated from the input port at the center frequency.
Branch line couplers usually do not have such a wide bandwidth and are constrained by their designed frequencies. As to the latter point, a branch line coupler has a single frequency, which can be used with a single device. To accommodate different frequency devices, it is necessary to use a differently designed branch line coupler. Accordingly, large chip area needs to be used to accommodate different operating frequencies.
In an aspect of the invention, a reconfigurable branch line coupler comprises a plurality of transmission lines, each of which comprises a phase shifter. The reconfigurable branch line coupler further comprises an input port, which is split into two quadrature signals providing a second and third port between adjacent of the plurality of transmission lines, with a fourth port isolated from the input port at a center frequency.
In an aspect of the invention, a reconfigurable branch line coupler comprises: a plurality of transmission lines coupled to one another, the plurality of transmission lines comprising: a first transmission line having a characteristic impedance of Zo_B; a second transmission line having a characteristic impedance of Zo_A; a third transmission line having a characteristic impedance of Zo_B; and a fourth transmission line having characteristic impedance of Zo_A; and a phase shifter provided in each of the plurality of transmission lines, the phase shifter in each of the plurality of transmission lines being structured to maintain a constant characteristic impedance of Zo_B and Zo_A while changing a frequency in each of the plurality of transmission lines.
In an aspect of the invention, a method of reconfiguring a branch line coupler comprises determining initial characteristic impedance Zo_A and Zo_B for a specific frequency for each transmission line of the branch line coupler. The method further comprises adjusting capacitance and inductance, at the same time and same rate, taking into consideration w_scan, ws_scan, s_scan, w_ret, capacitance (high/low) and inductance (high/low), with the following approximations: %_change_l (Zo_A)=%_change_l (Zo_B); (ii) %_change_c (Zo_A)=%_change_c (Zo_B); (iii) 0.707*Zo_high (Zo_A)=Zo_high (Zo_B); and (iv) 0.707*Zo_low (Zo_A)=Zo_low (Zo_B).
In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of the reconfigurable branch line coupler, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the reconfigurable branch line coupler. The method comprises generating a functional representation of the structural elements of the reconfigurable branch line coupler.
The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.
The invention relates to semiconductor structures and, more particularly, to a reconfigurable branch line coupler and methods of designing and reconfiguring the branch line coupler. More specifically, the present invention is directed to a device and method that allows simple, robust reconfigurability of an on-chip Millimeter Wave (MMW) branch line coupler. In embodiments, the MMW branch line coupler includes arms (transmission lines) which each include a phase shifter (with discrete sections) making it possible to change the operating frequencies of the branch line coupler by a large factor, e.g., of about 3×, in controlled linear steps. For example, the branch line coupler can be reconfigured by (i) adjusting the characteristic impedance of the phase shifter on a first transmission line to equal the sqrt(2) times the characteristic impedance of the phase shifter on a second transmission line such that (ii) the transmission lines of the branch line coupler change frequencies by exactly the same factor. Accordingly, it is now possible to switch Zo-0.707*Zo and 0.707*Zo->Zo.
Advantageously, the branch line coupler of the present invention can change frequency significantly such that only a single device is used on a chip for different operating frequencies. This not only provides a considerable savings in chip area, but also allows large area circuit components to be re-used at different operating conditions and frequencies. Moreover, the branch line coupler of the present invention can combat processing variation by, for example, adjusting the delays, Zo (impedance), etc. In embodiments, for example, the branch line coupler can also maintain a constant delay and vary Zo or vice versa. Further, with the branch line coupler of the present invention, it is possible to implement a direct conversion Rx (receiving) and Tx (transmitting) with wide band.
The branch line coupler of the present invention can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer or nanometer scale. The methodologies, i.e., technologies, employed to manufacture the reconfigurable branch line coupler of the present invention have been adopted from integrated circuit (IC) technology. For example, the structures of the present invention are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the branch line coupler of the present invention uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
In embodiments, the phase shifters 14 have controllable inductance and controllable capacitance, where the characteristic impedance of a section can vary the phase shift without significantly affecting the constant characteristic impedance, Zo, of the branch line coupler 10. Accordingly, the phase shifters 14 are structured such that the branch line coupler 10 can maintain a constant Zo while changing the operating frequency up to, e.g., about 3×. On the other hand, by using the phase shifters 14, the branch line coupler 10 can maintain a constant operating frequency while varying Zo.
In operation, any combination of the discrete sections 14′ in each transmission line 12a, 12b, 12c and 12d is structured to be switched to incrementally adjust the delay or characteristic impedance, Zo. In this way, by switching discrete sections 14′ of the phase shifter, the inductance (L) and capacitance (C) can be adjusted high or low, while maintaining the same characteristic impedance, Zo, for a transmission line. That is, the reconfigurable branch line coupler can maintain constant characteristic impedance while changing delay in unison by a same ratio/percentage with the correct Zo_A and Zo_B ratio to ensure acceptable branch line performance. By way of example, the branch line coupler 10 can be reconfigured by adjusting characteristic impedance of the phase shifter on transmission lines by a factor of sqrt(2) times an original characteristic impedance of the transmission lines. In a more specific example, the branch line coupler 10 can be reconfigured by adjusting the characteristic impedance of the phase shifter on a first transmission line to equal the sqrt(2) times the characteristic impedance of the phase shifter on a second transmission line; whereas, the characteristic impedance of the phase shifter of the second transmission line is adjusted to 1/sqrt(2) times the characteristic impedance of the phase shifter on the first transmission line.
Advantageously, by using the discrete sections 14′ of the phase shifter, it is now possible to use the branch line coupler 10 for different frequency ranges, and hence allows large area circuit components to be reused at different operating frequencies without the need for different devices. So, for example, the branch line coupler 10 of the present invention can provide both 30 GHz and 60 GHz desired input and output characteristics of a circuit component.
In the circuit model of
characteristic impedance Zo_A new=Zo_B old (FIG. 2); and (i)
characteristic impedance Zo_B new=Zo_A old (FIG. 2). (ii)
Also, in implementation, the delay in the swapped transmission lines 12a, 12b, 12c and 12d can remain the same.
In embodiments, the swapping can be accomplished by independently changing the inductance high and capacitance low, or vice versa, in order to match a desired frequency. Also, in embodiments, the branch line coupler 10′ can be reconfigured on the fly to output to a different port, thereby being capable of being used as a switch. This implementation can be useful for power monitoring or for designs where small size is critical.
By way of more specific illustrative example, for a port swap mode, the following can be assumed:
sqrt(L_high—B/C_low—B)˜sqrt(2)*sqrt(L_low—B/C_low—B)=sqrt(2)*Zo—B˜Zo—A;
sqrt(C_low—B*L_high—B)˜sqrt(2)*sqrt(C_low—B*L_low—B)˜sqrt(2)*delay—B_fast;
sqrt(L_low—A/C_high—A)˜(1/sqrt(2))*sqrat(L_low—A/C_low—A)=(1/sqrt(2))*Zo—A˜Zo—B; and
sqrt(C_high—A*L_low—A)˜sqrt(2)*sqrt(C_low—A*L_low—A)˜sqrt(2)*delay—A_fast.
It should be understood that reference letters “A” and “B” represent transmission lines of length “A” and length “B”, respectively, reference letter “C” represents capacitance and reference letter “L” represents inductance.
In a normal frequency changing operation:
Let X=delay_B_fast, then, for 3-bit, 8 states of delay for “transmission line” B as follows:
[X, 1.143X, 1.286X, 1.429X, 1.571X, 1.714X, 1.857X, 2X]
By providing a swap mode, the branch line coupler 10′ can now be used as a switch due to the significant change in frequency, e.g., 1.429X which is ˜1.414X˜sqrt(2) X=sqrt(2)*delay_B_fast. Also, by implementing the processes and structures of the present invention, it is also noted that each transmission line can have both fine and course tuning segments, e.g., 10%-20% of the arm delay, Zo, etc., by incrementally switching the discrete sections of the phase shifter in some combination. This can thus be used for combating process variations and fine tuning for improved accuracy.
The flow can be implemented in any known computing infrastructure, using, for example, computer readable storage medium. For example, the computing infrastructure can be a computing device resident on a network infrastructure or computing device of a third party service provider. The computing device includes a processor (e.g., CPU), memory, an I/O interface, and a bus. The memory can include local memory employed during actual execution of program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. In addition, the computing device includes random access memory (RAM), a read-only memory (ROM), and an operating system (O/S). The computing device is in communication with external I/O device/resource and storage system. In general, processor executes computer program code (e.g., program control), which can be stored in memory and/or storage system. Moreover, in accordance with aspects of the invention, program control controls the processes described herein.
Computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device, e.g., computing infrastructure. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Referring to
%_change—l(Zo—A)=%_change—l(Zo_B): In this example: 96.6%˜99.9%; (i)
%_change—c(Zo—A)=%_change—c(Zo_B): In this example: 98.8%˜101.1%; (ii)
0.707*Zo_high (Zo—A)=Zo_high (Zo—B): In this example: 0.707*(53.5 Ohms)=37.8 Ohms˜37.1 Ohms; and (ii)
0.707*Zo_low (Zo—A)=Zo_low (Zo—B): In this example: 0.707*(53.8 Ohms)=38 Ohms˜37.2 Ohms. (iv)
Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in
Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990.
Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
