Patent Application
20200106394
In a radio frequency (RF) transceiver, a communication signal is typically received and down converted by receive circuitry, sometimes referred to as a receive chain. A receive chain typically includes a receive filter, a low noise amplifier (LNA), a mixer, a local oscillator (LO), a voltage controlled oscillator (VCO), a baseband filter, and other components, to recover the information contained in the communication signal. The transceiver may also include circuitry that enables the transmission of a communication signal to a receiver in another transceiver. The transceiver may be able to operate over multiple frequency ranges, typically referred to a frequency bands. Moreover, a single transceiver may be configured to operate using multiple carrier signals that may occur in the same frequency band, but that may not overlap in actual frequency, an arrangement referred to as non-contiguous carriers.
In an example, a single transmitter or receiver may be configured to operate using multiple transmit frequencies and/or multiple receive frequencies. For a receiver to be able to simultaneously receive two or more receive signals, the concurrent operation of two or more receive paths is required. Such systems are sometimes referred to as Carrier Aggregation (CA) systems. The term carrier aggregation may refer to systems that include inter-band carrier aggregation and intra-band carrier aggregation. Intra-band carrier aggregation refers to the processing of two separate and non-contiguous carrier signals that occur in the same communication band. To accommodate the broad operating ranges and bandwidths associated with carrier aggregation systems, an RF transceiver may require several switchable active and passive devices. A broadband LNA, for example, may require one or more variable capacitors to support impedance matching across the required frequencies. Such matching circuits may generate signal noise within the LNA and may degrade the performance of the LNA.
An example of a noise cancellation circuit according to the disclosure includes a first transconductance stage operably coupled to a radio-frequency input, a resistive matching circuit including a second transconductance stage operably coupled to the radio-frequency input, a first resistance element having a first terminal operably coupled to the radio-frequency input and a second terminal operably coupled to an output of the second transconductance stage, and a voltage-to-current converter circuit having an input terminal operably coupled to the output of the second transconductance stage, a second resistance element having a first terminal operably coupled to an output of the voltage-to-current converter circuit and a second terminal operably coupled to an output of the first transconductance stage, and a capacitance element having a first terminal operably coupled to the output of the voltage-to-current converter circuit and a second terminal operably coupled to the output of the first transconductance stage.
Implementations of such a noise cancellation circuit may include one or more of the following features. The first transconductance stage may include a capacitor coupled between the second terminals of the second resistance element and capacitance elements and one or more transconductance elements of the first transconductance stage. The second transconductance stage may include a first transistor having a gate operably coupled to the radio-frequency input, and a second transistor having a gate operably coupled to the radio-frequency input, wherein the second terminal of the first resistance element is operably coupled to a drain of the first transistor and the second transistor, such that the first transconductance stage includes a third transistor having a gate operably coupled to the radio-frequency input, and a fourth transistor having a gate operably coupled to the radio-frequency input, voltage-to-current converter circuit includes a fifth transistor, wherein the gate of the fifth transistor is operably coupled to the drain of the first transistor and a drain of second transistor. The first resistance element may be a first variable resistance element. The second resistance element may be a second variable resistance element or the capacitance element is a variable capacitance element. The first transistor may be a p-type metal oxide semiconductor (PMOS) transistor and the second transistor may be an n-type metal oxide semiconductor (NMOS) transistor, or the first transistor may be an NMOS transistor and the second transistor may b a PMOS transistor. The third transistor may be a p-type metal oxide semiconductor (PMOS) transistor and the fourth transistor may be an n-type metal oxide semiconductor (NMOS) transistor, or the third transistor may be an NMOS transistor and the fourth transistor may be a PMOS transistor. The capacitance element may be a first capacitance element, the first transconductance stage may further include a sixth transistor having a gate operably coupled to the radio-frequency input, a seventh transistor having a gate operably coupled to the radio-frequency input, such that the voltage-to-current converter circuit includes an eighth transistor having a gate operably coupled to the drain of the first transistor and the drain of the second transistor, a third resistance element having a first terminal operably coupled to a source of the eighth transistor and a second terminal operably coupled to a drain of the sixth transistor and to a drain of the seventh transistor via a capacitor, and a second capacitance element having a first terminal operably coupled to the source of the eighth transistor and a second terminal operably coupled to the drain of the sixth transistor and the drain of the seventh transistor via the capacitor. A primary component carrier processing circuit may be coupled to a first node coupled to the drain of the third transistor, the drain of the fourth transistor, and the second terminals of each of the second resistance element and the first capacitance element, and a secondary component carrier processing circuit may be coupled to a second node coupled to the drain of the sixth transistor, the drain of the seventh transistor, and the second terminals of each of the third resistance element and the second capacitance element. A first switch having a first terminal may be operably connected to the drain of the third transistor and the drain of the fourth transistor, the first switch may have a second terminal operably coupled to the drain of the sixth transistor and the drain of the seventh transistor, and a second switch in parallel with the first switch may have a first terminal operably connected to the drain of the third transistor and the drain of the fourth transistor, the first switch may have a second terminal operably coupled to the drain of the sixth transistor and the drain of the seventh transistor. Each of the first transconductance stage and the second transconductance stage may include at least one of an inverter, a transistor, or a cascode. A value of the second resistance element and a value of the capacitance element may be based on a frequency of a signal at the radio-frequency input. A frequency of a signal at the radio-frequency input may be in a range of 600 MHz to 3.8 GHz. The noise cancellation circuit may form at least a portion of a low noise amplifier (LNA) circuit in a receive path of a transceiver. An output of the noise cancellation circuit may be operably connected to a node operably coupled to the output of the second transconductance stage and the second terminals of each of the second resistance element and the capacitance element. The radio-frequency input may include a primary component carrier and a secondary component carrier in a carrier aggregation application. The primary component carrier and the secondary component carrier may be based on a non-contiguous carrier aggregation application.
An example of a device according the disclosure includes a resistive matching stage configured to receive a communication signal, a first cancellation path configured to receive the communication signal, the first cancellation path operably coupled to the resistive matching stage and a first load, and a first current combiner circuit operably coupled to the resistive matching stage and the first load, the first current combiner circuit being configured to control a phase of a current of the communication signal received from the resistive matching stage.
Implementations of such a device may include one or more of the following features. The first current combiner circuit may be controlled to cancel noise through the first cancellation path from the resistive matching stage. Noise from the resistive matching stage through the first cancellation path may be combined out-of-phase with noise through the resistive matching stage. The resistive matching stage may include a first variable resistance element operably coupled to a drain of a first transistor and a drain of a second transistor, and the first cancellation path may include a third transistor and a fourth transistor, a gate of the third transistor may be operably coupled to a gate of the first transistor in the resistive matching stage, and a gate of the fourth transistor may be operably coupled to a gate of the second transistor in the resistive matching stage. The first current combiner circuit may include a fifth transistor and a filter network, a gate of the fifth transistor may be operably coupled to the first variable resistance element in the resistive matching stage, and a source of the fifth transistor may be operably coupled to a second variable resistance element and a variable capacitance element in the filter network. A value of the second variable resistance element and a value of the variable capacitance element may be based on a frequency of the communication signal. The communication signal may include a primary component carrier and a secondary component carrier in a carrier aggregation application. A second cancellation path may be operably coupled to the resistive matching stage and a second load, and a second current combiner circuit operably coupled to the resistive matching stage and the second load. A second cancellation path, such that the second cancellation path may include a first secondary component carrier transistor and a second secondary component carrier transistor, a gate of the first secondary component carrier transistor may be operably coupled to a gate of the first transistor in the resistive matching stage, and a gate of the second secondary component carrier transistor may be operably coupled to a gate of the second transistor in the resistive matching stage, a second current combiner circuit, such that the second current combiner circuit may include a second current combiner transistor and a second current combiner filter network, a gate of the second current combiner transistor may be operably coupled to the first variable resistance element in the resistive matching stage, and a source of the second transistor may be operably coupled to the second current combiner filter network, and the second current combiner filter network may be operably coupled to a second load. A plurality of switches may be configured to enable a first current flow from the first cancellation path and the first current combiner circuit to the first load, or to enable a second current flow from the second cancellation path and the second current combiner circuit to the second load. The communication signal may include a primary component carrier and a secondary component carrier in an intra-band carrier aggregation application. The device may be at least a portion of a low noise amplifier (LNA) circuit in a receive path of a transceiver. The resistive elements and capacitive elements may be respective variable resistive elements and variable capacitive elements.
An example of a method for providing noise cancellation according to the disclosure includes performing impedance matching of a radio signal input with a resistive matching component, providing the radio signal input to one or more current combiner circuits, cancelling noise generated in the resistive matching component with a cancellation path, and providing an output of the one or more current combiner circuits and an output of the cancellation path to a load.
Implementations of such a method may include one or more of the following features. A resistance value for at least one resistor and a capacitance value for at least one capacitor may be set in the one or more current combiner circuits, such that the resistance value and the capacitance value are based on a frequency of the radio signal input. The radio signal input may include a primary component carrier and a secondary component carrier.
An example device according to the disclosure includes a resistive matching means configured to receive communication signal, means for canceling noise generated in the resistive matching means, and means for controlling a phase of a current of the communication signal received from the resistive matching means.
Techniques are discussed herein for a reconfigurable broadband and noise cancellation LNA architecture with intra-CA capabilities. For example, the LNA architecture may include a resistive matching network, a current combiner circuit and a cancellation circuit. The cancellation circuit may be configured to cancel noise generated by the resistive matching network. The current combiner circuit may be used to extend the noise cancellation by controlling the phase of a sampled output from the restive network and then injecting the phase-controlled signal into a load. The current combiner circuit may be used to control the phase of a wide range of frequencies. These techniques are examples only, and not exhaustive.
Items and/or techniques described herein may provide one or more of the following capabilities, as well as other capabilities not mentioned. A communication signal such as a radio signal may be provided to an amplifier circuit. The amplifier may include a resistive matching network, a noise cancellation circuit, and a current combiner circuit. The current combiner circuit may include one or more RC filters configured to control the phase of an output signal based on the phase of an input communication signal. Noise generated in the resistive matching network may be canceled through the noise cancellation circuit. The current combiner enables the noise cancellation circuit to operate over a wider range of frequencies. The noise cancellation circuit and current combiner module may include multiple paths to support carrier aggregation schemes. The amplifier may provide broadband noise cancellation support for frequencies in the range of 600 MHz to 3.8 GHz with intra-carrier aggregation capability. Other capabilities may be provided and not every implementation according to the disclosure must provide any, let alone all, of the capabilities discussed. Further, it may be possible for an effect noted above to be achieved by means other than that noted, and a noted item/technique may not necessarily yield the noted effect.
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The wireless device 110 may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. The wireless device 110 may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, etc. The wireless device 110 may communicate with wireless communication system 120. The wireless device 110 may also receive signals from broadcast stations (e.g., a broadcast station 134), signals from satellites (e.g., a satellite 150) in one or more global navigation satellite systems (GNSS), etc. The wireless device 110 may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA 1x, EVDO, TD-SCDMA, GSM, 802.11, etc.
The wireless device 110 may support carrier aggregation, which is operation on multiple carriers. Carrier aggregation may also be referred to as multi-carrier operation. The wireless device 110 may be able to operate in low-band (LB) band group covering frequencies lower than 1000 megahertz (MHz), mid-band (MB) band group covering frequencies from 1000 MHz to 2300 MHz, a high-band (HB) band group covering frequencies from 2300 MHz to 2600 MHz, and/or an ultra-high-band (UHB) covering frequencies from 2600 MHz to 3800 MHz. For example, low-band may cover 698 to 960 MHz, mid-band may cover 1475 to 2170 MHz, and high-band may cover 2300 to 2690 MHz and 3400 to 3800 MHz. Low-band, mid-band, high-band, and ultra-high-band refer to four groups of bands (or band groups), with each band group including a number of frequency bands (or simply, “bands”). Each band may cover up to 200 MHz and may include one or more carriers. Each carrier may cover up to 20 MHz in LTE. LTE Release 11 supports 35 bands, which are referred to as LTE/UMTS bands and are listed in 3GPP TS 36.101. In an embodiment, the wireless device 110 may be configured with up to five carriers in one or two bands in LTE Release 11.
In general, carrier aggregation (CA) may be categorized into two types - intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same band. Inter-band CA refers to operation on multiple carriers in different bands.
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A transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between radio frequency (RF) and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the example shown in
In the transmit path, the data processor 310 processes data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to the transmitter 330. The data processor 310 may include one or more digital-to-analog-converters (DAC's) 314a and 314b for converting digital signals generated by the data processor 310 into the I and Q analog output signals, e.g., I and Q output currents, for further processing.
Within the transmitter 330, one or more lowpass filters 332a and 332b filter the I and Q analog transmit signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion. Amplifiers (Amp) 334a and 334b amplify the signals from lowpass filters 332a and 332b, respectively, and provide I and Q baseband signals. An upconverter 340 includes the mixers 341a and 341b and is configured to upconvert the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 390 and provides an upconverted signal. A filter 342 filters the upconverted signal to remove undesired images caused by the frequency up-conversion as well as noise in a receive frequency band. A power amplifier (PA) 344 amplifies the signal from filter 342 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 346 and transmitted via an antenna 348.
In the receive path, one or more antennas 348 receives communication signals and provides a received RF signal, which is routed through a duplexer or a switch 346 and provided to a low noise amplifier (LNA) 352. The LNA 352 may be a reconfigurable broadband and noise cancellation LNA with intra-carrier aggregation capability as described herein. The switch 346 is designed to operate with a specific RX-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by LNA 352 and filtered by a filter 354 to obtain a desired RF input signal. One or more down conversion mixers 361a and 361b are configured to mix the output of filter 354 with I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator 380 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 362a and 362b and further filtered by lowpass filters 364a and 364b to obtain I and Q analog input signals, which are provided to data processor 310. In an example, the data processor 310 includes analog-to-digital-converters (ADC's) 316a and 316b for converting the analog input signals into digital signals to be further processed by the data processor 310.
A TX LO signal generator 390 generates the I and Q TX LO signals used for frequency up-conversion, while a RX LO signal generator 380 generates the I and Q RX LO signals used for frequency down conversion. Each LO signal is a periodic signal with a particular fundamental frequency. A phase locked loop (PLL) 392 receives timing information from data processor 310 and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from LO signal generator 390. Similarly, a PLL 382 receives timing information from data processor 310 and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from LO signal generator 380.
In an example, the wireless device 300 may also comprise a WIFI transceiver 376. The WIFI transceiver 376 may be coupled to an antenna 378 and to the data processor 310. The WIFI transceiver 376 may include transmit and receive circuitry configured to communicate over one or more WIFI communication bands pursuant to one or more of the IEEE 801.11 protocols. Although shown as having a separate antenna 378, the WIFI transceiver 376 may also be configured to use the antenna 348, in which case, the WIFI transceiver 376 would be coupled to the duplexer or switch 346.
The wireless device 300 may support CA and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies and/or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers.
In a CA communication environment where multiple receive signals are processed simultaneously, it is possible that a receive signal on a particular receive path can couple to and impair the sensitivity of a receiver operating on a receive signal on a different receive path. Moreover, it is also possible that that a WIFI transmit or receive signal can generate signal noise and impair the sensitivity of a receiver operating on a receive signal on a different receive path.
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The transconductance stage 554 includes a third transistor 570a and a fourth transistor 570b. The third and fourth transistors 570a and 570b are connected to form an inverter type architecture but other transconductance configurations can be likewise used. The third and fourth transistors 570a-b may be p-type and n-type MOSFETs respectively. The gates of the first transistor 564a and the third transistor 570a are coupled to the PMOS DC bias voltage, and the gates of the second transistor 564b and the fourth transistor 570b are coupled to the NMOS DC bias voltage. The drains of the third transistor 570a and the fourth transistor 570b are coupled to the load 558 via a capacitance element 572. Other AC coupling components are possible in other configurations. The transconductance stage 554 may include noise from the resistive matching stage that may be canceled when combined with the output from the current combiner 556 in an out of phase manner.
The current combiner 556 is operably coupled to the resistive matching stage 552 and the load 558. In an example, the current combiner 556 includes a n-type transistor 582, and an RC filter network including a second variable resistance element 584 and a variable capacitance element 586. The n-type transistor 582 may be referred to as the fifth transistor 582 in view of the first transistor 564a and the second transistor 564b. The RC filter is coupled to the source side of the fifth transistor 582 and can extend the noise cancellation features of the LNA 550 through a broad range of frequencies by changing the phase of the noise signal. Specifically, the fifth transistor 582 is configured to sample the output of the resistive matching stage 552 and inject the sampled signal into the load 558 with that of the transconductance stage 554. The second variable resistance element 584 and the variable capacitance element 586 may be respectively banks of resistors and capacitors that may be set based on the frequency band and used to control the phase of the injected signal. The current combiner 556 extends the noise cancellation capability over much wider range of frequencies by controlling the phase of the injected signal with the RC filter.
In an embodiment the noise cancelling LNA 550 includes a radio-frequency input (RF Vin)) and the first transistor 564a. A gate of the first transistor 564a is operably coupled to the radio-frequency input. The LNA 550 includes the second transistor 564b. A gate of the second transistor 564b is operably coupled to the radio-frequency input. The LNA 550 includes a first variable resistance element 562 including an input and an output, the input being operably coupled to the radio-frequency input, and the output being operably coupled to a drain of the first transistor 564a and a drain of the second transistor 564b. The LNA 550 includes a third transistor 570a. A gate of the third transistor 570a is operably coupled to the gate of the first transistor 564a. The LNA 550 includes a fourth transistor 570b. A gate of the fourth transistor 570b is operably coupled to the gate of the second transistor 564b. The LNA 550 includes a fifth transistor 582. A gate of the fifth transistor 582 is operably coupled to the output of the first variable resistance element 562, the drain of the first transistor 564a, and the drain of the second transistor 564b. The LNA 550 includes a second variable resistance element 584 including an input and an output, the input being operably coupled to a source of the fifth transistor 582, and the output being operably coupled to a drain of the third transistor 570a and a drain of the fourth transistor 570b. The LNA 550 includes a variable capacitance element 586 including an input and an output, the input being operably coupled to the input of the second variable resistance element 584, and the output being operably coupled to the output of the second variable resistance element 584. An output of the noise cancelling LNA 550 is operably coupled to the output of the variable capacitance element 586 and the drain of the third transistor 570a and the drain of the fourth transistor 570b.
In an aspect, as illustrated each of the transconductance stage 554 and the resistive matching stage include transistors based on an inverter architecture. However, other transconductance circuits may also be used such as single transistors, cascodes, or other non-CMOS transconductance architectures. Furthermore, the transconductance stage 554, while shown with just one inverter stage may include multiple stages (e.g., multiple inverters or other cascaded transconductance elements). The transconductance stage 554 may have a programmable/adjustable gain. Furthermore, any of the transconductance elements or transistors in the resistive matching stage 552 or the current combiner 556 may also be configured to have a programmable gain or include multiple cascaded elements. Moreover, as will be appreciated by those of skill, the components shown in
Based on the circuits shown in
The transconductance stage 554 may form a noise cancellation path. The path through the resistive matching stage 552 may provide an impedance via the first variable resistance element 562 (e.g., tuned to create overall 50-ohm input impedance). The current combiner 556 is used to combine the gm of the path through resistive matching stage 552 and the gm of the path through the transconductance stage 554. Noise through the path of the resistive matching stage 552 is sampled at the input impedance and converted into current through the transconductance stage 554. Signals going through the parallel paths are then combined where the RF signal from each path is combined in-phase while the sampled noise is combined out-of-phase.
The current combiner 556 may sum the gm from the resistive matching stage 552 with the gm through the transconductance stage 554 using a source follower as illustrated by the arrangement of the fifth transistor 582 (other voltage-to-current converter architectures may also be used). As noted above, the RC elements 584 and 586 act as a phase shifter to tune the phases between the output of the transconductance stage 554 and the output of the resistive matching stage 552.
While certain transistors are noted as n-type or p-type it should be appreciated that these types may be reversed or configured in a way consistent with the disclosure but using different types or different transistor technologies.
Furthermore, while the first variable resistance element 562, the second variable resistance element 584 and the variable capacitance element 586 are shown variable/tunable elements, in some embodiments each of these elements may be fixed values. As such, the disclosure contemplates at least one embodiment where these elements have fixed values.
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The current combiner 606 may include a plurality of current combiner circuits that are operably coupled to the resistive matching stage 602. For example, a first current combiner circuit may include a first transistor 632a and first filter network 634a, 636a, and a second current combiner circuit may include a second transistor 632b and a second filter network 634b, 636b. The values of the RC components may be based on the frequencies of the PCC and SCC. The output of the current combiner circuits are operably coupled to a respective one of the primary and secondary carrier paths as depicted in
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At stage 702, the method includes performing impedance matching on a radio signal input with a resistive matching stage. The resistive matching stage 602 receives an RF input and may include a first variable resistance element 612 and a plurality of transistors 614a-b. The value of the resistance may vary based on the frequency of the RF input. In a broadband application the value of the RF input may vary between 600 MHz to 3.8 GHz.
At stage 704, the method includes providing the radio signal input to one or more current combiner circuits. The resistive matching stage 602 is operably coupled to the current combiner 606. The current combiner 606 includes one or more transistors 632a-b and RC filter networks 634a-b, 636a-b. The values of the resistors and capacitors in the RC networks may vary based on the frequency of the RF input. The current combiner is configured to control the phase of the injected signal using the RC filter networks. The current combiner 606 may be configured to control the phase of both the PCC and SCC paths.
At stage 706, the method includes cancelling noise generated in the resistive matching stage. The transconductance stage 604 is operably coupled to the resistive matching stage 602 and includes a plurality of transistors 620a-b, 622a-b where noise generated on the PCC and SCC paths is canceled using out of phase combining. The resistive matching stage 602, including the transistors 614a-b, generates noise which may impact the performance of the LNA architecture.
At stage 708, the method includes providing an output of the current combiner 606 and an output of the transconductance stage 604 to a load. The load may be along the PCC or SCC path such as, for example, the first transformer 640 and the second transformer 642. The use of the current combiner 606 enables the control of the phase of the output signal for different frequencies. This phase control extends the operating frequency range of the cancellation circuit. The switching circuitry extends the frequency range performance to non-contiguous CA applications.
The LNA circuit described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The LNA circuit may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.
An apparatus implementing the LNA circuit described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.
Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of hardware, software and computers, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.
Also, as used herein, “or” as used in a list of items prefaced by “at least one of” or prefaced by “one or more of” indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C,” or a list of “one or more of A, B, or C,” or “A, B, or C, or a combination thereof” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C), or combinations with more than one feature (e.g., AA, AAB, ABBC, etc.).
As used herein, unless otherwise stated, a statement that a function or operation is “based on” an item or condition means that the function or operation is based on the stated item or condition and may be based on one or more items and/or conditions in addition to the stated item or condition.
Substantial variations may be made in accordance with specific requirements. For example, customized hardware might also be used, and/or particular elements might be implemented in hardware, software (including portable software, such as applets, etc.), or both.
The methods, systems, and devices discussed above are examples. Various configurations may omit, substitute, or add various procedures or components as appropriate. For instance, in alternative configurations, the methods may be performed in an order different from that described, and that various steps may be added, omitted, or combined. Also, features described with respect to certain configurations may be combined in various other configurations. Different aspects and elements of the configurations may be combined in a similar manner. Also, technology evolves and, thus, many of the elements are examples and do not limit the scope of the disclosure or claims.
Specific details are given in the description to provide a thorough understanding of example configurations (including implementations). However, configurations may be practiced without these specific details. For example, well-known circuits, processes, algorithms, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the configurations. This description provides example configurations only, and does not limit the scope, applicability, or configurations of the claims. Rather, the preceding description of the configurations provides a description for implementing described techniques. Various changes may be made in the function and arrangement of elements without departing from the spirit or scope of the disclosure.
Also, configurations may be described as a process which is depicted as a flow diagram or block diagram. Although each may describe the operations as a sequential process, some operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process may have additional stages or functions not included in the figure. Furthermore, examples of the methods may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof When implemented in software, firmware, middleware, or microcode, the program code or code segments to perform the tasks may be stored in a non-transitory computer-readable medium such as a storage medium. Processors may perform one or more of the described tasks.
Components, functional or otherwise, shown in the figures and/or discussed herein as being connected, coupled (e.g., communicatively coupled), or communicating with each other are operably coupled. That is, they may be directly or indirectly, wired and/or wirelessly, connected to enable signal transmission between them.
Having described several example configurations, various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the disclosure. For example, the above elements may be components of a larger system, wherein other rules may take precedence over or otherwise modify the application of the invention. Also, a number of operations may be undertaken before, during, or after the above elements are considered. Accordingly, the above description does not bound the scope of the claims.
“About” and/or “approximately” as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, encompasses variations of ±20% or ±10%, ±5%, or +0.1% from the specified value, as appropriate in the context of the systems, devices, circuits, methods, and other implementations described herein. “Substantially” as used herein when referring to a measurable value such as an amount, a temporal duration, a physical attribute (such as frequency), and the like, also encompasses variations of ±20% or ±10%, ±5%, or +0.1% from the specified value, as appropriate in the context of the systems, devices, circuits, methods, and other implementations described herein.
Further, more than one invention may be disclosed.
