Reconfigurable circuit

Abstract

A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a diagram illustrating a configuration example of a reconfigurable circuit according to an embodiment of the present invention.

FIG. 2 shows a diagram illustrating a configuration example of a network circuit.

FIG. 3 shows a diagram illustrating a configuration example of a switch.

FIG. 4 shows a diagram illustrating a more concrete configuration example of the reconfigurable circuit shown in FIG. 1.

FIG. 5 shows a flowchart illustrating an operation example of the reconfigurable circuit shown in FIG. 4.

FIG. 6 shows a diagram illustrating a more concrete configuration example of the reconfigurable circuit shown in FIG. 4.

FIG. 7 shows a diagram illustrating a configuration example of a swap selector.

FIG. 8 shows a diagram illustrating a configuration example of a reconfigurable circuit in which a configuration 0 is set.

FIG. 9 shows a diagram illustrating a configuration example of a reconfigurable circuit in which a configuration 1 is set.

FIG. 10 shows a diagram illustrating a configuration example of a network module.

FIG. 11 shows a diagram illustrating a configuration example simplified from the network module shown in FIG. 10.

FIG. 12 shows a diagram illustrating a circuit in which output terminals RAMo and ALU1o in the circuit shown in FIG. 11 are exchanged.

Claims

1. A reconfigurable circuit comprising: an arithmetic unit group performing arithmetic operations;a network circuit controlling connections between an output terminal and an input terminal of said arithmetic unit group; anda first selector connected between said arithmetic unit group and the network circuit,wherein said arithmetic unit group comprises a first terminal and a second terminal, andsaid network circuit comprises a first terminal and a second terminal, andwhen a first control signal is in a first state, said first selector connects said first terminal of the arithmetic unit group to said first terminal of the network circuit, and also connects said second terminal of the arithmetic unit group to said second terminal of the network circuit, while when a first control signal is in a second state, said first selector connects said first terminal of the arithmetic unit group to said second terminal of the network circuit, and also connects said second terminal of the arithmetic unit group to said first terminal of the network circuit.

2. The reconfigurable circuit according to claim 1, wherein said arithmetic unit group comprises a first output terminal and a second output terminal, andsaid network circuit comprises a first input terminal and a second input terminal, andwhen a first control signal is in a first state, said first selector connects said first output terminal of the arithmetic unit group to said first input terminal of the network circuit, and also connects said second output terminal of the arithmetic unit group to said second input terminal of the network circuit, while when a first control signal is in a second state, said first selector connects said first output terminal of the arithmetic unit group to said second input terminal of the network circuit, and also connects said second output terminal of the arithmetic unit group to said first input terminal of the network circuit, andwherein an input terminal of said arithmetic unit group is connected to an output terminal of said network circuit.

3. The reconfigurable circuit according to claim 2, wherein said arithmetic unit group comprises a third output terminal and a fourth output terminal, andsaid network circuit comprises a third input terminal and a fourth input terminal, andwhen a second control signal is in a first state, said first selector connects said third output terminal of the arithmetic unit group to said third input terminal of the network circuit, and also connects said fourth output terminal of the arithmetic unit group to said fourth input terminal of the network circuit, while when a second control signal is in a second state, said first selector connects said third output terminal of the arithmetic unit group to said fourth input terminal of the network circuit, and also connects said fourth output terminal of the arithmetic unit group to said third input terminal of the network circuit.

4. The reconfigurable circuit according to claim 1, further comprising: a network memory storing network control signal information; anda register storing said first control signal information,wherein said network circuit controls said connection according to the network control signal information stored in said network memory, andsaid first selector performs said connection according to the first control signal information stored in said register.

5. The reconfigurable circuit according to claim 2, further comprising: a network memory storing network control signal information; anda register storing said first control signal information,wherein said network circuit controls said connection according to the network control signal information stored in said network memory, andsaid first selector performs said connection according to the first control signal information stored in said register.

6. The reconfigurable circuit according to claim 1, wherein said arithmetic unit group comprises a first input terminal and a second input terminal, andsaid network circuit comprises a first output terminal and a second output terminal, andwhen a first control signal is in a first state, said first selector connects said first input terminal of the arithmetic unit group to said first output terminal of the network circuit, and also connects said second input terminal of the arithmetic unit group to said second output terminal of the network circuit, while when a first control signal is in a second state, said first selector connects said first input terminal of the arithmetic unit group to said second output terminal of the network circuit, and also connects said second input terminal of the arithmetic unit group to said first output terminal of the network circuit, andan output terminal of said arithmetic unit group is connected to an input terminal of said network circuit.

7. The reconfigurable circuit according to claim 6, wherein said arithmetic unit group comprises a third input terminal and a fourth input terminal, andsaid network circuit comprises a third output terminal and a fourth output terminal, andwhen a second control signal is in a first state, said first selector connects said third input terminal of the arithmetic unit group to said third output terminal of the network circuit, and also connects said fourth input terminal of the arithmetic unit group to said fourth output terminal of the network circuit, while when a second control signal is in a second state, said first selector connects said third input terminal of the arithmetic unit group to said fourth output terminal of the network circuit, and also connects said fourth input terminal of the arithmetic unit group to said third output terminal of the network circuit.

8. The reconfigurable circuit according to claim 6, further comprising: a network memory storing network control signal information; anda register storing said first control signal information,wherein said network circuit controls said connection according to the network control signal information stored in said network memory, andsaid first selector performs said connection according to the first control signal information stored in said register.

9. The reconfigurable circuit according to claim 1, wherein said arithmetic unit group comprises a first input terminal, a second input terminal, a first output terminal and a second output terminal, andsaid network circuit comprises a first input terminal, a second input terminal, a first output terminal and a second output terminal, andwhen a first control signal is in a first state, said first selector connects said first output terminal of the arithmetic unit group to said first input terminal of the network circuit, and also connects said second output terminal of the arithmetic unit group to said second input terminal of the network circuit, while when a first control signal is in a second state, said first selector connects said first output terminal of the arithmetic unit group to said second input terminal of the network circuit, and also connects said second output terminal of the arithmetic unit group to said first input terminal of the network circuit, and whereinwhen a second control signal is in a first state, a second selector connects said first input terminal of the arithmetic unit group to said first output terminal of the network circuit, and also connects said second input terminal of the arithmetic unit group to said second output terminal of the network circuit, while when a second control signal is in a second state, said second selector connects said first input terminal of the arithmetic unit group to said second output terminal of the network circuit, and also connects said second input terminal of the arithmetic unit group to said first output terminal of the network circuit.

10. The reconfigurable circuit according to claim 9, wherein said arithmetic unit group comprises a third input terminal, a fourth input terminal, a third output terminal and a fourth output terminal, andsaid network circuit comprises a third input terminal, a fourth input terminal, a third output terminal and a fourth output terminal, andwhen a third control signal is in a first state, said first selector connects said third output terminal of the arithmetic unit group to said third input terminal of the network circuit, and also connects said fourth output terminal of the arithmetic unit group to said fourth input terminal of the network circuit, while when a third control signal is in a second state, said first selector connects said third output terminal of the arithmetic unit group to said fourth input terminal of the network circuit, and also connects said fourth output terminal of the arithmetic unit group to said third input terminal of the network circuit, and whereinwhen a fourth control signal is in a first state, said second selector connects said third input terminal of the arithmetic unit group to said third output terminal of the network circuit, and also connects said fourth input terminal of the arithmetic unit group to said fourth output terminal of the. network circuit, while when a fourth control signal is in a second state, said second selector connects said third input terminal of the arithmetic unit group to said fourth output terminal of the network circuit, and also connects said fourth input terminal of the arithmetic unit group to said third output terminal of the network circuit.

11. The reconfigurable circuit according to claim 9, further comprising: a network memory storing network control signal information;a first register storing said first control signal information; anda second register storing said second control signal information,wherein said network circuit controls said connection according to said network control signal information stored in said network memory, andsaid first selector performs said connection according to said first control signal information stored in said first register, andsaid second selector performs said connection according to said second control signal information stored in said second register.