Patent Application
20250219289
Reconfigurable intelligent surfaces (alternatively referred to as intelligent reflective surfaces, or metasurfaces) are man-made thin reflective surfaces whose electromagnetic response can be electronically controlled. Intelligent reflective surfaces thus have the ability to boost the spectral energy and spectral efficiency of redirected electromagnetic waves. Because an intelligent reflective surface can change the phase shifts of signals reflected at the surface, intelligent reflective surfaces are being evaluated for use in beyond fifth generation (B5G) and sixth generation (6G) wireless communication and wireless sensing networks.
Traditionally, the elements, or unit cells, of a reconfigurable intelligent surface have a variable conductive patch size, wherein the size of the conductive patch determines the phase shift of the unit cell. By controlling the phase shifts among the unit cells of a reconfigurable intelligent surfaces, the reflections of the unit cells with respect to an impinging electromagnetic wave can be combined into a beam steered in a specified direction, or into multiple beams split into multiple directions.
The technology described herein is illustrated by way of example and not limited in the accompanying figures in which like reference numerals indicate similar elements and in which:
The technology described herein is generally directed towards a design and implementation of a reconfigurable intelligent surfaces (RIS) realized by incorporating reconfigurability within a phase-delay element of the unit cells that form the reconfigurable intelligent surfaces, as an alternative to the commonly used variable size element patch. The technology described herein overcomes many known problems with reconfigurable intelligent surfaces that have unit cells with variable patch sizes, including non-linearity of an element's phase profile caused by using a variable of resonating frequency for phase profile. Such non-linearity resulting from the variable patch sizes limits the achievable bandwidth of the reflectarray surface, because non-linearity leads to distorted radiation patterns, and further, the restricted operational bandwidth due to the non-linearity cannot effectively support wideband applications such as satellite and automotive radar systems. Another problem is fabricating reflectarrays with variable-sized elements, which requires high manufacturing precision due to its aggressive variation near its resonating frequency; imprecise element sizes result in performance degradation and reduced overall efficiency, which limits their use in high-frequency applications. Variable-sized elements also can introduce high insertion/reflection loss due to increased material usage, impedance mismatches and their usage in resonating frequency, which reduces the overall efficiency of a reflectarray, resulting in decreased signal strength, a lower signal-to-noise ratio and degraded system performance. Non-uniform loss distribution from variable patch sizes results in uneven power distribution and compromises the performance of a reflectarray, causing high sidelobes and a lower signal-to-noise ratio. Further, the irregularities introduced by the use of variable-sized elements violate the assumption of an infinite array, especially on the area where phase wrapping occurs; such a violation of the infinite array approximation can lead to deviations in the radiation pattern and degradation of the beam-steering capabilities of a reflectarray.
Instead, described herein introduces reconfigurability directly into a phase-delay element (via a variable length phase delay line element), which overcomes the various challenges associated with typically-used variable size conductive patches, including as improved bandwidth and reduced fabrication costs with lower precision requirements that result technology described herein. One implementation of the technology described herein is directed to a monolithic integration of the element using chalcogenide materials, such as germanium antimony telluride (GST) alloys. Usage of this material offers advantages such as negligible power consumption through pulsed actuation and reduced design and external wiring.
It should be understood that any of the examples and/or descriptions herein are non-limiting. Thus, any of the embodiments, example embodiments, concepts, structures, functionalities or examples described herein are non-limiting, and the technology may be used in various ways that provide benefits and advantages in communications and computing in general. It also should be noted that terms used herein, such as “maximize” “optimize” or “optimal” and the like only represent objectives to move towards a more maximal or optimal state, rather than necessarily obtaining ideal results.
Reference throughout this specification to “one embodiment,” “an embodiment,” “one implementation,” “an implementation,” etc. means that a particular feature, structure, characteristic and/or attribute described in connection with the embodiment/implementation can be included in at least one embodiment/implementation. Thus, the appearances of such a phrase “in one embodiment,” “in an implementation,” etc. in various places throughout this specification are not necessarily all referring to the same embodiment/implementation. Furthermore, the particular features, structures, characteristics and/or attributes may be combined in any suitable manner in one or more embodiments/implementations. Repetitive description of like elements employed in respective embodiments may be omitted for sake of brevity.
The detailed description is merely illustrative and is not intended to limit embodiments and/or application or uses of embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding sections, or in the Detailed Description section.
One or more embodiments are now described with reference to the drawings, wherein like referenced numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the one or more embodiments. It is evident, however, in various cases, that the one or more embodiments can be practiced without these specific details.
Further, it is to be understood that the present disclosure will be described in terms of a given illustrative architecture; however, other architectures, structures, materials and process features, and steps can be varied within the scope of the present disclosure.
Example embodiments of the subject disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which example components, graphs and/or operations are shown. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. However, the subject disclosure may be embodied in many different forms and should not be construed as limited to the examples set forth herein.
A controller 114, e.g., having some processing and storage capabilities (block 116) located at the reconfigurable intelligent surface 106 obtains or determines the individual phase shift values 112. Each of the unit cells 104(1,1)-104(m,n) includes a phase shifter as described herein, e.g., on the back surface of each unit cell. The phase shifters each comprises a number of single-pole, multiple-throw switches that are based on phase change material (chalcogenide) elements (component parts of the switches).
One or more intended uses of the technology described herein is for millimeter wave (mmWave) applications. With mmWave phase shifters, size and power consumption are significant criteria. For these reasons, a chalcogenide material-based phase shifter is designed and implemented with the advantages of monolithic integration and reduction in power consumption.
In general, a voltage or current pulse changes the resistance of the chalcogenide material from a low-resistance (conductive) state to a high-resistance (non-conductive) state or vice-versa, depending on the energy level and duration of the pulse. Significantly, once the chalcogenide material is in one of the states, the chalcogenide material remains in that state, without needing further power to maintain or refresh the state, that is, there is no power consumption after reconfiguration. Such an ability to latch chalcogenide elements in a state is facilitated via a pulse code modulation-based phase shifter, which is employed in one example implementation described herein. Thus, it is straightforward to construct a single-pole, multi-throw switch with individually controllable chalcogenide material elements with “open” position(s) corresponding to the high-resistance state(s) and a closed position corresponding to the low-resistance state, with only power consumed for changing the switch position.
Based on the individual phase shift values 112, the controller 114 controls a heater network 118 to change the resistances states of the chalcogenide elements, which in this implementation results in basically changing the “throw positions” of the switches formed with those chalcogenide elements. Note that only the chalcogenide elements that need changing need to be pulsed, e.g., if a switch is already in the correct position as a result of a previous phase shift scenario, which the controller 114 can evaluate with respect to the needed states corresponding to the just-received phase shift values, there is no need to pulse the chalcogenide elements that make up that particular switch.
Described herein is incorporating reconfigurability into the phase-delay elements, which is unlike prior solutions that avoid phase-delay elements because of prior lack of reconfigurability, (and instead use elements with variable size patches, despite their many drawbacks). Reconfigurability is accomplished as described herein by selecting among different lengths of phase delay elements using chalcogenide-based switches.
As can be seen in
The components of the second sub-path B are somewhat similar to those of sub-path A, except that the third switch 443 is connected to the common port t0
As can be seen, changing the four switches' chalcogenide element states to select among (e.g., “mix and match”) the candidate path lengths/transmission lines results in a phase delay of one of: of 0, 20, 40, 60, 80, 100, 120, 140 or 160 degrees. For example, to configure 80 degrees of phase shift, the chalcogenide elements' states are changed (if necessary) such that the path from the RF input to the RF output is via transmission paths t1 and t3.
Note that for loss compensation, in one implementation the widths of the transmission lines increase with the length of the transmission line. This reduces the variation of the loss that would otherwise occur without different widths.
As can be readily appreciated,
Numerical experiments were conducted to evaluate the performance between elements with variable size (as typically used), and elements with variable phase-delay line elements as described herein.
In sum, described herein in general is providing reconfigurability to reflectarrays with phase-delay elements by the utilization of PCM-based mm Wave phase shifters, instead of using elements with variable size. This phase-delay-based element technology brings several advantages, including that the use of phase-delay elements offers reduced phase truncation errors, reduced deviation from infinite array approximation, and reduced phase range errors. At the same time, the use of PCM-based phase shifts offers the elimination of soldered components, fast switching, significant reduction in power consumption, area saving, and digital reconfigurability. By incorporating chalcogenide materials, the design process is simplified, reconfigurability is achieved, and the inherent benefits of using phase-delay lines are maintained.
One or more example embodiments can be embodied in a system, such as represented in the example operations of
At least two of the chalcogenide material elements can form a chalcogenide material-based single-pole, multiple throw switch.
The path length of the variable-length conductive phase-delay transmission line element can correspond to a selected conductive path, selected by the phase shifter from among a group of candidate conductive paths, by determining respective conductive or non-conductive states of respective chalcogenide material elements of the chalcogenide material elements. Respective candidate conductive paths can correspond to respective different phase shift amounts, and the respective candidate conductive paths can have respective different conductive path widths that correspond to the respective different phase shifts.
The phase shifter can include a pulse code modulation-based controller coupled to a heater network to individually determine the respective conductive or non-conductive states of the respective chalcogenide material elements. The phase shift can be a first phase shift, and the pulse code modulation-based controller phase can apply pulsed energy to latch the respective conductive or non-conductive states of the respective chalcogenide material elements without applying further energy until the variable phase-shift unit cell is changed from the first phase shift to a second phase shift that is different from the first phase shift.
A subgroup of the chalcogenide material elements can be configured as a single-pole, multiple-throw switch, and controlling the phase shifter to change the phase shift can include switching among conductive and non-conductive states of the subgroup of the chalcogenide material elements to select the path length between the RF input terminal and the RF output terminal from among multiple different candidate path lengths corresponding to multiple switch positions of the multiple-throw switch. The subgroup can be a first subgroup configured as a first single-pole, multiple-throw switch at a beginning of the path length, a second subgroup of the chalcogenide material elements can be configured as a second single-pole, multiple-throw switch, and controlling the phase shifter to change the phase shift can include switching among conductive and non-conductive states of the second subgroup of the chalcogenide material elements to determine an end of the path length.
The candidate path lengths can include a first candidate path length that corresponds to a first amount of phase delay, a second candidate path length that corresponds to a second amount of phase delay, and a third candidate path length that corresponds to a reference phase delay; the first candidate path length, the second candidate path length, and the third candidate path length can be different from one another.
A first subgroup of the chalcogenide material elements can be configured as a first single-pole, multiple-throw switch, a second subgroup of the chalcogenide material elements can be configured as a second single-pole, multiple-throw switch, a third subgroup of the chalcogenide material elements can be configured as a third single-pole, multiple-throw switch, and a fourth subgroup of the chalcogenide material elements can be configured as a fourth single-pole, multiple-throw switch. Controlling of the phase shifter to change the phase shift can include switching among conductive and non-conductive states of the first subgroup and among conductive and non-conductive states of the second subgroup to select a first sub-path length from among multiple different candidate first sub-path lengths that correspond to multiple throw positions of the first single-pole, multiple-throw switch and multiple throw positions of the second single-pole, multiple-throw switch. Controlling of the phase shifter to change the phase shift can include switching among conductive and non-conductive states of the third subgroup and among conductive and non-conductive states of the fourth subgroup to select a second sub-path length from among multiple different candidate second sub-path lengths that correspond to multiple throw positions of the third single-pole, multiple-throw switch, and multiple throw positions of the second single-pole, multiple-throw switch. An output terminal of the second single-pole, multiple-throw switch can be coupled to an input terminal of the third single-pole, multiple-throw switch to add the first sub-path length to the second sub-path length to determine the path length between the RF input terminal and the RF output terminal.
The variable phase-shift unit cell can be one unit cell of a group of unit cells that form a reconfigurable intelligent surface, and the phase shift of the unit cell can determine part of a beam reflected as a beam by the reconfigurable intelligent surface from an electromagnetic wave impinging on the reconfigurable intelligent surface. The group of unit cells can include respective unit cells comprising respective conductive metal portions; the respective conductive metal portions can be matching or substantially matching in size.
One or more example embodiments, such as corresponding to example operations of a method, are represented in
Changing the respective states of the respective individual chalcogenide components can include controlling a controllable heater network that selectively transfers heat to at least some of the respective individual chalcogenide components.
The transmission line path length can correspond to a first sub-path length of the phase-delay line corresponding to a first amount of phase shift, and a second sub-path length of the phase-delay line corresponding to a second amount of phase shift. Changing the respective states of the respective chalcogenide components can include controlling at least some of the respective states to add the first sub-path length of the phase-delay line to the second sub-path length of the phase-delay line to vary the transmission line path length of the variable phase-delay line element.
The transmission line path length can include a first sub-path length plus a second sub-path length, and changing the respective states of the respective chalcogenide components can include controlling at least some of the respective states to change the first sub-path length to a different first sub-path length.
One or more example embodiments can be embodied in a unit cell, such as described and represented herein. The unit cell can include a conductive patch, a phase delay element coupled to the conductive patch, and a phase shifter, the phase shifter including respective switches comprising respective chalcogenide material parts in respective low-resistance or high-resistance states, the phase shifter changing at least some of the respective low-resistance or high-resistance states of the respective chalcogenide material parts to select among available transmission paths that determine a length of the phase delay element, resulting in a phase shift of the unit cell with respect to redirecting an electromagnetic wave impinging on the unit cell.
The phase shifter can include a pulse code modulation-based controller that controls a heater network for changing the at least some of the respective low-resistance or high-resistance states of the respective chalcogenide material parts.
The length of the phase delay element can include a first sub-path length determined by the phase shifter, and a second sub-path length determined by the phase shifter.
The unit cell can be one unit cell of a group of unit cells that form a reconfigurable intelligent surface, and the phase shift of the unit cell can determine part of a beam reflected by the reconfigurable intelligent surface based on an electromagnetic wave impinging on the unit cell.
As can be seen, the technology described herein provides a unit cell with a variable phase change element that overcomes many of the issues with variable element patch size solutions. The phase-delay unit-cells described herein enable a linear phase profile across the array, which is highly desirable as it allows for precise control and manipulation of the electromagnetic wavefront across the array, leading to improved beamforming and beam-steering capabilities. The phase-delay unit-cells described herein offer improved bandwidth compared to variable-size unit-cells, because the linearity of the phase profile enables a wider range of phase shifts, allowing for broader frequency coverage and enhanced performance across a larger bandwidth. The use of phase-delay unit-cells reduces the sensitivity to fabrication imperfections, which reduces the error and fabrication cost; phase-delay unit-cells rely on accurate phase control, which is typically easier to achieve in fabrication. Phase-delay unit-cells can achieve better impedance matching, resulting in reduced power losses and improved overall efficiency of the reconfigurable intelligent surface. Phase-delay unit-cells offer a more uniform distribution of losses throughout the reconfigurable intelligent surface; (in contrast, with variable-size unit-cells, the non-uniformity of element sizes leads to non-uniform power distribution and uneven losses across the array, causing performance degradation). With phase-delay unit-cells as described herein, the power distribution is more balanced, resulting in improved performance consistency.
Further, phase-delay unit-cells helps mitigate the infinite array approximation violation by maintaining a more consistent and regular array structure, improving the applicability of theoretical models and simplifying system design. This is due to less geometrical structure being changed across unit-cells. As a result, the technology described herein provides significant prospects in enhancing the performance and efficiency of reconfigurable intelligent surface technology in mmWave/6G applications.
The above description of illustrated embodiments of the subject disclosure, comprising what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as those skilled in the relevant art can recognize.
In this regard, while the disclosed subject matter has been described in connection with various embodiments and corresponding Figures, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below.
As it employed in the subject specification, the term “processor” can refer to substantially any computing processing unit or device comprising, but not limited to comprising, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit, a digital signal processor, a field programmable gate array, a programmable logic controller, a complex programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Processors can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor may also be implemented as a combination of computing processing units.
As used in this application, the terms “component,” “system,” “platform,” “layer,” “selector,” “interface,” and the like are intended to refer to a computer-related resource or an entity related to an operational apparatus with one or more specific functionalities, wherein the entity can be either hardware, a combination of hardware and software, software, or software in execution. As an example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration and not limitation, both an application running on a server and the server can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which is operated by a software or a firmware application executed by a processor, wherein the processor can be internal or external to the apparatus and executes at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, the electronic components can comprise a processor therein to execute software or firmware that confers at least in part the functionality of the electronic components.
In addition, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances.
While the embodiments are susceptible to various modifications and alternative constructions, certain illustrated implementations thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the various embodiments to the specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope.
In addition to the various implementations described herein, it is to be understood that other similar implementations can be used or modifications and additions can be made to the described implementation(s) for performing the same or equivalent function of the corresponding implementation(s) without deviating therefrom. Still further, multiple processing chips or multiple devices can share the performance of one or more functions described herein, and similarly, storage can be effected across a plurality of devices. Accordingly, the various embodiments are not to be limited to any single implementation, but rather are to be construed in breadth, spirit and scope in accordance with the appended claims.
