The present disclosure relates generally to analog to digital converters.
An analog-to-digital converter (A/D or ADC) is an electronic device that can convert analog signal information (e.g. amplitude or phase) to a digital (e.g. numerical) value representative of the analog signal. These devices enable a central processing unit to carry out processing functions in a more quantized mathematical domain without the need for downstream analog devices.
Signal processing systems utilizing A/D converters, including complex A/D converters (CADCs), have various functionality requirements. Such requirements may include a track and hold, or sample and hold operation performed on an analog input signal, as well as precise timing operations, in addition to the A/D conversion process. Clock generators, for example, are used to synchronize sample and hold amplifiers with an ADC. The sample and hold amplifiers follow an input analog signal of interest until a control signal from the clock causes the amplifier to freeze and hold the time varying analog signal (for a given time interval). The same clock signal also strobes the ADC to convert the held or “frozen” sample to a digital value. This digital data can then be buffered and read out to memory for further processing. The time it takes for the sample and hold amplifiers and ADC to perform the operation and be ready for the next value is the A/D sample rate.
Standard A/D conversion systems are too slow to directly digitize ultra high frequency and microwave RF signals. These frequency ranges are typically in the second and third Nyquist regions of the converter, including military frequency bands up to 20-40 GHz. Accordingly, these systems must utilize several analog down conversion steps before the signal is sufficiently low in frequency to allow for digitization. In addition to limited or low sample rates, A/D converters further hinder signal processing operations due to their limited resolution, measured by the effective number of bits or ENOB. In order to improve ADC resolution, various architectures including pipeline ADCs have been developed. Digitally programmable ADCs have been developed to support certain processing requirements such as multi-band and multi-mode operation. One such example is a digitally programmable sub-ranging ADC, which incorporates the improved resolution of pipeline-based architectures with the ability to operate in various modes (e.g. 5 bit, 9 bit and 13 bit). However, these systems typically incorporate analog multiplexers MUXs in a primary analog signal path of sub-ranging ADC system in order to reconfigure the system for different operating resolutions. A drawback of this approach is that these MUXs must possess a dynamic range greater than or equal to that of the converter as a whole. Further, because the MUXs are always in the primary signal path, they will necessarily add noise, and degrade the noise, settling, and dynamic range of the converter.
Alternative converter topologies are desired which accommodate multi-band and multi-mode operation, in addition to being digitally programmable, and preferably without one or more of the above-described limitations.
In one embodiment, a reconfigurable wideband analog-to-digital converter (ADC) system is provided. The system comprises a first converter stage having a first signal path including a first sample and hold circuit for sampling an input signal at a first resolution, and a second signal path responsive to the input signal and arranged in parallel with the first signal path. The second signal path includes a second sample and hold circuit for sampling the input signal at a second resolution. A first ADC is also included for generating a digital representation of the signal sampled by the first converter stage. A control circuit is arranged between the first and second sample and hold circuits and the input of the ADC for selectively providing the signal sampled by one of the first or second sample and hold circuit to the input of the ADC.
In another embodiment, a reconfigurable ADC system comprises: 1) a first converter stage including a first sample and hold circuit for sampling an input signal at a first resolution and a second sample and hold circuit arranged in parallel with the first sample and hold circuit for sampling the input signal at a second resolution; 2) a second converter stage including a third sample and hold circuit arranged in series with the first converter stage; and 3) a third converter stage including a fourth sample and hold circuit arranged in series with the first and second converter stages. A control circuit is arranged in parallel with a primary signal path defined between an input of the first converter stage and an output of the third converter stage, and configured to selectively provide an output of the first or second sample and hold circuit to the input of an ADC.
a is a simplified schematic diagram of a digitally programmable sub-ranging ADC according to embodiments of the present disclosure.
b is a section view of a portion of the digitally programmable sub-ranging ADC of
a is a simplified schematic diagram of a reconfigurable sub-ranging ADC according to an embodiment of the present disclosure.
b is a simplified diagram of a reconfigurable ADC and DAC used in the sub-ranging ADC of
a and 11b are simplified schematic diagrams of a reconfigurable ADC according to an embodiment of the present disclosure.
It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, many other elements found in ADCs and their associated clock generation systems, including digitally programmable sub-ranging ADCs. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein. The disclosure herein is directed to all such variations and modifications known to those skilled in the art.
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. Furthermore, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout several views.
Embodiments of the present disclosure include improved ADC architectures that support multiple operational bandwidths as well as multiple modes of operation. This ADC architecture is based on sub-ranging ADC architectures, which have historically addressed both narrowband, high dynamic range applications for radar, as well as moderate bandwidth for communications applications.
A timing generation system 22 is responsive to an input clock signal 24 for generating various delayed versions of the input clock signal, embodied as clock signals fphi0-fphi6. As illustrated, these clock signals are used to control the operation of, and more specifically the on/off timing of, the components of ADC system 10, including buffer and hold amplifiers 13-15″ and ADCs 17-17′″. Bits sampled from each ADC 17,17′,17″ from each stage are provided to digital error correction components such as digital error correction processor 25 for generating a digital output signal 26 representative of input signal 11. As the bits from each ADC 17-17″″ are generated at different times during the conversion process, processor 25 time-aligns all of the bits by delaying the bits of ADC 17 and ADC 17′ such that they align with bits generated by ADC 17″ in time. Processor 25 is configured to digitally add all of the bits, and output a digital representation of sampled and held input signal 11, which is accomplished at the output of buffer amplifier 13.
Traditional ADC clocking schemes used to generate, for example, the delayed clock signals fphi0-fphi6 illustrated in
ADC applications, including those used in communications, electronic warfare, and radar systems, have diverse instantaneous bandwidth, resolution, dynamic range, and signal-to-noise requirements.
A drawback of this approach is that MUXs 21,21′,21″ are arranged directly in the critical primary signal path of ADC system 20. For example, at least at the front end of ADC system 20, MUX 21 must possess a dynamic range greater than or equal to that of the converter as a whole. Further, because MUXs 21,21′,21″ are always in the primary signal path, they will, by default, add noise, and degrade the noise, settling, and dynamic range of the converter, in comparison to the nominal converter shown in
Using the base-line architecture of sub-ranging ADC system 10 of
Sub-ranging ADC system 80 is configured to support multi-band, multi-mode operation. For example, the ADC clock rate is variable in order to support nearly two decades of instantaneous bandwidth requirements (e.g. 50 MHz to 1 GHz). However, it is difficult to digitally reconfigure a single front end sample and hold circuit for the ADC without compromising the performance of the sample and hold in any mode of operation. In one embodiment, the front end of ADC system 80 is configured for processing along two signal paths: a high dynamic range (HDR) or high resolution path 60 and high speed path 61. High resolution signal path 60 comprises first and second sample and hold circuits 50,50′, including respective first sample and hold amplifier pair 51,53 and second sample and hold amplifier pair 51′,53′. Likewise, high speed path 61 comprises first and second sample and hold circuits 52,52′, including respective first sample and hold amplifier pair 56,57 and second sample and hold amplifier pair 56′,57′. Each path is communicatively coupled to analog input signal 11. In this way, each of paths 60,61 may be independently configured and optimized for performance according to the requirements of the particular application.
Sub-ranging ADC system 80 is further configured to enable changing the digital resolution of the converter without sacrificing performance through the use of MUXs arranged in the critical signal path. Due to the separate high resolution path 60 and high speed path 61, respective first sample and hold circuits 50,52, of each of these signal paths remain separate. Depending on which configuration ADC system 80 is operating (e.g. high speed or high resolution), the output of one of these first sample and hold circuits will be selectively passed to a coarse quantizer comprising ADC 87 and DAC 88 via control circuit 62 for performing the first sampling pass. The placement of control circuit 62 in this coarse path, as opposed to the main signal path of ADC system 80 (e.g. between input signal 11, through each sample and hold circuit, to a last ADC 87″), relaxes the performance requirements of control circuit 62, thus enabling its implementation without compromising overall performance. In order for first sampling pass to accommodate different possible resolutions, the signal to ADC 87 is controlled through a digitally programmable variable attenuator 86. Additionally, the gain of ADC 87 (e.g. Q level) is digitally programmable via gain control 89. These two adjustments provide two degrees to freedom, allowing the resolution of the ADC to grow or shrink without requiring circuit modifications.
Referring again to the main signal path of ADC system 80, in order to select high speed path 61 or high resolution path 60, a second multiplexing operation is required. However, this multiplexing is accomplished via a control circuit, including two selectively active emitter follower paths 90,91, rather than by placing an additional MUX in the primary signal path as described above with respect to
Still referring to
The same topology for digitally programmable signal attenuation and quantizer gain is used in the second and third sampling stages or passes, as illustrated. More specifically, the second pass includes amplifier 64, buffer amplifier 65, sample and hold amplifiers 66,67, a second variable attenuator 86′ for controlling the input to signal to ADC 87′ and a DAC 88′, and a gain controller 89′ for controlling gain ADC 87′. The third and final sampling pass likewise includes amplifier 64′, a buffer amplifier 65′, and a variable attenuator 86″ for controlling ADC 87″. A third digitally programmable gain controller 89″ is also provided for controlling the operation of ADC 87″. As illustrated, the resolution of each of the three sampling passes can be digitally programmable, thereby providing flexibility to the converter's overall resolution.
For low resolution, low bandwidth applications, the bandwidth of all the wideband circuits must be reduced. This reduction allows noise to be reduced/minimized, as well as provides for additional settling time due to the reduced sampling rate. As discussed, it is not desirable to perform this bandwidth reduction in the critical front end high performance sample and hold circuits of the ADC. In the illustrated embodiments of
In the high resolution mode of the ADC, increasing the compensation capacitor is accomplished by turning on BW control circuit 70 (e.g. a NMOS switch) for the first summing amplifier and BW control circuits 70′ for the second summing amplifier. For the high resolution mode, the input bandwidth is reduced, as is the sample rate. Thus, for this mode, the bandwidth of the summing amplifier may be reduced, as a result of the increased settling time afforded to the amplifier. Additionally, a lower bandwidth reduces the root mean square (RMS) noise contribution of each summing amplifier, thereby improving the overall signal-to-noise ratio (SNR) of the overall ADC. It should be noted that it is possible to increase the compensation capacitor further for BW control circuit 70″ compared to BW control circuit 70. This is due at least in part to the second summing amplifier being connected further down the chain in the sub-ranging ADC. Thus, the performance requirements for this amplifier are reduced over the requirements for the first summing amplifier. The third sample/hold performance requirements are reduced compared to the first two sample holds. By increasing the capacitance (C) of the hold capacitor, reductions in the sample/hold bandwidth and the RMS noise are realized. By way of example, increasing the capacitance by a factor of 2-4 will reduce the overall bandwidth of the sample and hold by a similar factor, as bandwidth is proportional to the value of 1/C.
Moreover, as the root-mean-square (RMS) noise of the sample and hold is proportional to
the RMS noise will reduce by a factor of 1.44-2. Additionally, nonlinear pedestal and droop are reduced as the capacitance value increases. The performance requirements of the third pass quantizer are also reduced by the cascaded gain of the first and second buffer amplifiers 65,65′.
While offering numerous performance advantages, sub-ranging ADC system 80 of
In order to support the variable frequency clock needed for the ADC application of
Referring generally to
Still referring to
The digital output of state counter 109 is provided to a phase selector 111. Phase selector 111 may comprise a series of multi-bit DACs with digital inputs provided from state counter 109. Phase selector 111 is operative to output a plurality of control signals to respective delay lines 1031, 1032, 1033 . . . 103N for selectively controlling the delay imparted to input clock signal 24. The resulting delayed clock signals output from each delay line 1031, 1032, 1033 . . . 103N are provided to a logic circuit 110 comprising a plurality of buffer amplifiers for generating the desired remaining clock signals (e.g. fphi0-fphi6) for control of the subsequent sampling functions of ADC system 80 of
Referring generally to
More specifically, according to embodiments of the disclosure, clock edges 97 may be calibrated over process and temperature, and the resulting calibration data stored in look-up tables to provide for real-time correction of timing errors in order to optimize ADC performance. In the same fashion that DACs are used in phase selector 111 to adjust phase in DLL 100 disclosed
Still referring to
Referring generally to
One or more temperature sensors 124, such as temperature-sensing diodes, may be provided for continuously monitoring the temperature of the ADC or local junction temperature of a die in the vicinity of the DLLs. Temperature measurements may be taken periodically via processor 121, can be used to adjust timing edges in real-time based on changes in temperature during normal operation using the values in the table look-up. Processor 121 may be configured to receive a real-time ADC temperature via temperature sensor 124, and associate the measured temperature with a known timing error stored on memory device 122. Processor 121 may be operative to provide one or more timing correction signals 125 based on the results of the comparison between measured temperature and the stored calibration data to DACs 96,96′ for correcting a known timing error or drift via amplifiers 95,95′. It should be understood that amplifiers 95,95′ provide for phase adjustment, thereby adjusting the edges of the clock waveforms. In one embodiment, DACs 96,96′, error amplifiers 95,95′, and control processor 121 and memory device 122 may be incorporated into logic circuit 110 of
Multiple methods may be employed to reconfigure the programmable sub-ranging ADCs described herein according to desired speed, power, resolution and noise requirements. This flexibility is generally achieved by implementing digital programmability into select components of the ADC, enabling a single ADC architecture to be used in many different applications. According to embodiments of the present disclosure, the DC current supplied to each converter element, the number of sub-ranging stages, the number of quantizer and DAC bits, the quantizer Q level and the DAC least significant bit (LSB) current level all may be programmable. This is in contrast to converters in the current commercial marketplace, which have no such capability to be reconfigured.
a and 8b illustrate an exemplary system and method for reconfiguring a sub-ranging ADC having a topology similar to that shown and described with respect to
In the exemplary illustrated configuration, a control signal 254 from control processor 252 may be used to reconfigure the digital error correction logic utilized by error correction processor 250, as well as deactivate amplifiers 213″,215″,219′, ADC 217″, DAC 218′ and all or part of ADC 217′, such that only first stage 212 and second stage 214 are operative, while third stage 216 is bypassed. As illustrated in more detail in
In order to raise or lower the power in the preamplifiers and comparators of the ADC and the DAC buffers, the bias current of these individual circuits must also be digitally programmable. However, the preamplifiers and comparators of the ADCs (e.g. preamplifiers 221 and comparators 222), as well as the buffer amplifiers (e.g. buffers 223) of the DACs, comprise resistive loads. Accordingly, as current in each of these circuits is reduced, for example, its output voltage, and output voltage swing, is also reduced. This voltage swing reduction can negatively impact the performance of the ADC. Referring generally to
a and 11b illustrate additional circuitry of an exemplary reconfigurable ADC or quantizer 217 according to an embodiment of the present disclosure. ADC 217 includes a resistive ladder 260 comprising a plurality of resistors 262. The quantizer Q level is set by the current supplied by a plurality of current sources 265,265′,265″,265′″ into the resistor 262 (Q=I*R). Accordingly, the resolution and the Q level of ADC 217 may be digitally programmable by adjusting the currents supplied these current sources. In order to adjust the resolution while adjusting the Q value, a plurality of current sources 265,265′,265″,265′″ and associated switches 266 are provided for selectively supplying current to resistive ladder 260. By way of example only, for full resolution and Q level operation of ADC 217, current sources 265 and 265′″ may be turned on and current sources 265′ and 265″ turned off via, for example, a control signal provided by control processor 252 of
While these systems and methods for reconfiguring a sub-ranging ADC have been shown and described as applied to the simplified sub-ranging ADC of
While the foregoing invention has been described with reference to the above-described embodiment, various modifications and changes can be made without departing from the spirit of the invention. Accordingly, all such modifications and changes are considered to be within the scope of the appended claims. Accordingly, the specification and the drawings are to be regarded in an illustrative rather than a restrictive sense. The accompanying drawings that form a part hereof, show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations of variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.
Number | Name | Date | Kind |
---|---|---|---|
4677422 | Naito | Jun 1987 | A |
4893124 | Tsuji et al. | Jan 1990 | A |
6094153 | Rumsey et al. | Jul 2000 | A |
6693573 | Linder | Feb 2004 | B1 |
6803873 | Motomatsu | Oct 2004 | B1 |
7221191 | Ali et al. | May 2007 | B2 |
7990185 | Tran et al. | Aug 2011 | B2 |
8085079 | Tran et al. | Dec 2011 | B2 |
20020014982 | Jonsson | Feb 2002 | A1 |
20040036453 | Rossi | Feb 2004 | A1 |
20050219101 | Kurose et al. | Oct 2005 | A1 |
20100060494 | Pedersen | Mar 2010 | A1 |
20100103009 | Imai | Apr 2010 | A1 |
20100117879 | Ozeki et al. | May 2010 | A1 |
20110187573 | Thomas et al. | Aug 2011 | A1 |
20120249348 | Siragusa | Oct 2012 | A1 |
20120286986 | Noguchi | Nov 2012 | A1 |
20130234870 | Hague et al. | Sep 2013 | A1 |
Entry |
---|
Willy Sansen, “CMOS ADC & DAC Principles”, KULeuven, ESAT-MICAS, Leuven, Belgium, 65 pages, Oct. 2005. |