Patent Application
20230361791
The present invention relates to wireless communications, and more particularly, to a reconfigurable wireless receiver using filters with different filter architecture, oscillators with different oscillator architecture, and/or a time-sharing phase-locked loop (PLL) core.
In many wireless communication systems, a radio-frequency (RF) signal may be down-converted to an intermediate-frequency (IF) signal or baseband signal prior to conversion to a digital signal for further digital processing. Filters are conventionally used to remove interference noise from the IF or baseband signal in order to decrease the signal's dynamic range which may be helpful in the subsequent conversion from an analog signal to a digital signal. A filter implemented using high performance filter architecture can achieve good interference rejection at the expense of high current consumption. When a wireless receiver is employed by a portable device powered by a battery device, the wireless receiver with high power consumption makes the portable device have shorter operation time. Thus, there is a need for an innovative wireless receiver structure with low power consumption and high receiver performance.
One of the objectives of the claimed invention is to provide a reconfigurable wireless receiver using filters with different filter architecture, oscillators with different oscillator architecture, and/or a time-sharing phase-locked loop (PLL) core.
According to a first aspect of the present invention, an exemplary sub-circuit of a reconfigurable wireless receiver is disclosed. The exemplary sub-circuit of the reconfigurable wireless receiver includes a down-conversion circuit and a plurality of filters. The down-conversion circuit is arranged to apply down-conversion to a first signal, and generate and output a plurality of second signals each derived from down-converting the first signal. The filters are coupled to the down-conversion circuit, and arranged to apply filtering to the second signals for generating a plurality of filter outputs, respectively, wherein the filters include a first filter and a second filter, and the first filter and the second filter have different filter architecture.
According to a second aspect of the present invention, an exemplary sub-circuit of a reconfigurable wireless receiver is disclosed. The exemplary sub-circuit of the reconfigurable wireless receiver includes a down-conversion circuit. The down-conversion circuit is arranged to apply down-conversion to a first signal, and generate and output a plurality of second signals each derived from down-converting the first signal. The down-conversion circuit includes a local oscillator (LO) signal generation circuit and a plurality of mixers. The LO signal generation circuit includes a plurality of signal paths, a phase-locked loop (PLL) core circuit, and a plurality of mixers. A plurality of oscillators are located at the signal paths, respectively. The oscillators are arranged to provide a plurality of local oscillator (LO) signals, respectively. The PLL core circuit is alternately coupled to the plurality of signal paths in a time-sharing manner. The mixers are arranged to receive the first signal, and generate and output the plurality of second signals according to the plurality of LO signals, respectively.
According to a third aspect of the present invention, an exemplary sub-circuit of a reconfigurable wireless receiver is disclosed. The sub-circuit of the reconfigurable wireless receiver includes a down-conversion circuit. The down-conversion circuit is arranged to apply down-conversion to a first signal, and generate and output a plurality of second signals each derived from down-converting the first signal. The down-conversion circuit includes a plurality of oscillators and a plurality of mixers. The oscillators are arranged to provide a plurality of local oscillator (LO) signals, wherein the oscillators include a first oscillator and a second oscillator, and the first oscillator and the second oscillator have different oscillator architecture. The mixers are arranged to receive the first signal, and generate and output the plurality of second signals according to the plurality of LO signals, respectively.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
The down-conversion circuit 106 is arranged to apply down-conversion to an RF signal S1 (which is obtained by passing an RF signal received by the antenna 102 through the LNA 104), and generate and output a plurality of down-converted signals S2 and S3, each derived from down-converting the RF signal S1. The oscillators 132 and 134 are arranged to provide a plurality of LO signals LO1 and LO2 to the mixers 124 and 126, respectively. In this embodiment, the oscillators 132 and 134 may have different oscillator architecture. For example, the oscillator 132 may be a voltage-controlled oscillator (VCO) implemented by an inductor-capacitor (LC) oscillator, and the oscillator 134 may be a ring oscillator implemented by inverters. Since structures and principles of the LC oscillator and the ring oscillator are known to those skilled in the pertinent art, further description is omitted here for brevity.
The mixers 124 and 126 are arranged to receive the RF signal S1, and generate and output the down-converted signals S2 and S3 according to the LO signals LO1 and LO2, respectively. For example, each of the down-converted signals S2 and S3 may be an IF signal or a baseband signal. The filters 108 and 110 are coupled between the down-conversion circuit 106 and the processing circuit 112, and arranged to apply filtering to the down-converted signals S2 and S3 for generating a plurality of filter outputs S2_F and S3_F, respectively. In this embodiment, the filters 108 and 110 may have different filter architecture. For example, the filter 108 may be a resistor-capacitor (RC) filter (e.g. an active filter composed of an operational amplifier along with resistors and capacitors), and the filter 110 may be a transconductance-capacitor (GmC) filter. Compared to the RC filter, the GmC filter has lower current consumption and poorer filter characteristics. Hence, the GmC filter can be used for a low power mode, and the RC filter can be used for a high performance mode. In this embodiment, the wireless receiver 100 is reconfigurable, and can adaptively enable one or both of the filters 108 and 110 for different scenarios, thus achieving power saving without sacrificing the receiver performance. Since structures and principles of the RC filter and the GmC filter are known to those skilled in the pertinent art, further description is omitted here for brevity.
For better comprehension of technical features of the present invention, the following assumes that the filter 108 is an RC filter (i.e. a filter with higher performance and higher power consumption), the filter is a GmC filter (i.e. a filter with lower performance and lower power consumption), the oscillator 132 is an LC oscillator (i.e. an oscillator with higher performance and higher power consumption), and the oscillator 134 is a ring oscillator (i.e. an oscillator with lower performance and lower power consumption). However, these are for illustrative purposes only, and are not meant to be limitations of the present invention.
The processor 146 is a digital circuit. For example, the processor 146 may be a digital baseband processor. When the filter output S2_F is generated from the filter 108, the filter output S2_F is converted from an analog domain to a digital domain by the ADC 142, such that a digital input S2_FD is fed into the processor 146 for further processing. Similarly, when the filter output S3_F is generated from the filter 110, the filter output S3_F is converted from an analog domain to a digital domain by the ADC 144, such that a digital input S3_FD is fed into the processor 146 for further processing. In addition to obtaining the transmitted data from the digital input S2_FD/S3_FD, the processor 146 may perform signal-to-noise ratio (SNR) evaluation and/or jamming detection according to the digital input S2_FD/S3_FD, to control mode switching of the wireless receiver 100. Specifically, the wireless receiver 100 may support a plurality of modes, and may enter different modes for different scenarios. That is, the wireless receiver 100 is reconfigurable, such that the hardware configuration of the wireless receiver 100 can be adaptively adjusted to meet requirements of different scenarios. In this way, the reconfigurable wireless receiver 100 can achieve low power consumption without sacrificing the receiver performance.
Please refer to
When the wireless receiver 100 operates under the first mode Mode1, the processing circuit 112 processes the filter output S3_F of the filter 110 to evaluate an SNR, and detects if the SNR reaches a predetermined threshold. When the SNR is equal to or above the predetermined threshold under the first mode Mode1, the processing circuit 112 (particularly, processor 146 of processing circuit 112) judges that the SNR is good, and instructs the wireless receiver 100 to leave the first mode Mode1 and enter a fourth mode Mode4, as illustrated in
In one exemplary design, when the wireless receiver 100 operates under the fourth mode Mode4, the mixer 124, the oscillator 132, the filters 108 and 110, and the ADC 142 may be disabled for power saving; the LNA 104, the PLL core circuit 136, the oscillator 134, the mixer 126, the ADC 144, and the processor 146 may be enabled for receiving the transmitted data; and the down-converted signal S3 arriving at the filter 110 is bypassed to the processing circuit 112 (particularly, ADC 144 of processing circuit 112) via a bypass path (not shown). Since the filter 110 is disabled, more power can be saved under the fourth mode Mode4.
In another exemplary design, when the wireless receiver 100 operates under the fourth mode Mode4, the mixer 124, the oscillator 132, the filter 108, and the ADC 142 may be disabled for power saving; the LNA 104, the PLL core circuit 136, the oscillator 134, the mixer 126, the filter 110, the ADC 144, and the processor 146 may be enabled for receiving the transmitted data; and a current consumed by the filter 110 is intentionally reduced for additional power saving.
When the wireless receiver 100 operates under the first mode Mode1, the processing circuit 112 further processes the filter output S3_F of the filter 110 to detect if jamming (interfering signal) exists. When jamming is detected under the first mode Mode1, the processing circuit 112 (particularly, processor 146 of processing circuit 112) judges that the filter 110 with a wide bandwidth fails to provide the needed interference rejection. Hence, the processor 146 instructs the wireless receiver 100 to leave the first mode Mode1 and enter a second mode Mode2, as illustrated in
When the wireless receiver 100 operates under the second mode Mode2, the LNA 104, the PLL core circuit 136, the mixer 124, the oscillator 132, the filter 108, the ADC 142, and the processor 146 may be enabled for receiving the transmitted data, and the oscillator 134, the mixer 126, the filter 110, and the ADC 144 may be disabled for power saving. In a case where the wireless receiver 100 is a GNSS receiver, a bandwidth of the filter 108 is configured to meet a requirement of receiving a plurality of different GNSS bands through the same filter 108. For example, with proper settings of the LO signal LO1 and the bandwidth of the filter 108 as illustrated in
When the wireless receiver 100 operates under the second mode Mode2, the processing circuit 112 processes the filter output S2_F of the filter 108 to detect if jamming (interfering signal) still exists. When jamming is detected under the second mode Mode2, the processing circuit 112 (particularly, processor 146 of processing circuit 112) judges that the filter 108 with a wide bandwidth fails to provide the needed interference rejection. Hence, the processor 146 instructs the wireless receiver 100 to leave the second mode Mode2 and enter a third mode Mode3, as illustrated in
When the wireless receiver 100 operates under the third mode Mode3, all of the LNA 104, the PLL core circuit 136, the mixers 124 and 126, the oscillators 132 and 134, the filters 108 and 110, the ADCs 142 and 144, and the processor 146 may be enabled. In other words, two receive (RX) paths are both enabled under the third mode Mode3, and the processor 146 processes both of the digital signals S2_FD and S3_FD to obtain transmitted data of different frequency bands. In a case where the wireless receiver 100 is a GNSS receiver, a bandwidth of the filter 108 is configured to meet a requirement of receiving only a first part of different GNSS bands through the same filter 108, and a bandwidth of the filter 110 is configured to meet a requirement of receiving only a second part of the different GNSS bands through the same filter 110. Compared to the filter 108 under the second mode Mode2, the filter 108 under the third mode Mode3 has a narrower bandwidth, thus leading to better interference rejection performance as well as lower current consumption. Similarly, compared to the filter 110 under the first mode Mode1, the filter 110 under the third mode Mode3 has a narrower bandwidth, thus leading to better interference rejection performance as well as lower current consumption.
Please refer to
To achieve more power reduction, the wireless receiver 100 may be designed to use oscillators 132 and 134 with different oscillator architecture. In some embodiments of the present invention, the oscillator 132 used for generating the LO signal LO1 to the mixer 124 (which is used for generating and outputting the down-converted signal S2 to the filter 108) may be an LC oscillator, and the oscillator 134 used for generating the LO signal LO2 to the mixer 126 (which is used for generating and outputting the down-converted signal S3 to the filter 110) may be a ring oscillator. Compared to the LC oscillator with an LC tank, the ring oscillator implemented by inverters has lower power consumption. Compared to the ring oscillator implemented by inverters, the LC oscillator with an LC tank has better oscillator characteristics. The LC oscillator is suitable for the high performance mode, while the ring oscillator is suitable for the low power mode. For example, when the wireless receiver 100 operates under the first mode Mode1 (i.e. low power mode), the oscillator 134 with lower power consumption is enabled, and the oscillator 132 with higher power consumption is disabled. For another example, when the wireless receiver 100 operates under the second mode Mode1 (i.e. high performance mode), the oscillator 132 with a high-accuracy LO output is enabled, and the oscillator 134 with a low-accuracy LO output is disabled.
To achieve more power reduction, the wireless receiver 100 may be designed to use a time-sharing PLL core for locking output frequencies of two oscillators 132 and 134 alternately. For example, when the wireless receiver 100 operates under the third mode Mode3, the PLL core circuit 136 is used to control the LO frequency of one of the LO signals LO1 and LO2, and is reused to control the LO frequency of the other of the LO signals LO1 and LO2. Compared to using two individual PLL circuits for setting the LO signals LO1 and LO2, using a single PLL core circuit for setting the LO signals LO1 and LO2 in a time-sharing manner can have lower power consumption as well as lower hardware cost.
The LO signal generation circuit 122 shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
