The present invention relates generally to a power converter, and more specifically, to reconstructing the output voltage of a power converter.
Power converters need to detect or reconstruct their output voltage in order to regulate the output voltage to a desired voltage. Power converters need to reconstruct the output voltage and keep it stable for during the switching cycle in order to regulate the output voltage to the desired voltage. Conventional power converters typically reconstruct the output voltage by way of an analog feedback loop using an opto-coupler or a sample-and-hold circuit.
However, as shown in
Therefore, there is a need for a power converter that can reconstruct its output voltage without using additional components such as opto-couplers or sample-and-hold circuits.
The present invention provides an AC-to-DC power converter, its controller, and a method that can reconstruct the output voltage of the AC-to-DC power converter without a sample-and-hold circuit or an opto-coupler. The AC-to-DC power converter generally includes a switch that electrically couples or decouples a load to or from a power source, and a switch controller coupled to the switch for controlling the on-times and off-times of the switch.
The switch controller includes an accumulation module for accumulating a difference value obtained by subtracting a first representation of an output voltage of the power converter corresponding to a first sampling timing from an output voltage value sampled at a second sampling timing subsequent to the first sampling timing to obtain a second representation of the output voltage of the power converter corresponding to the second sampling timing. A differencer may be provided in the switch controller to obtain the difference value.
In one embodiment, the accumulation module sets the second representation of the output voltage to a predetermined maximum value if the output voltage value sampled at the second sampling timing exceeds the predetermined maximum value. In another embodiment, the accumulation module sets the second representation of the output voltage to a predetermined minimum value if the output voltage value sampled at the second sampling timing is less than the predetermined minimum value.
In another embodiment of the present invention, the controller comprises a comparator and an accumulation module. The comparator includes a negative terminal coupled to a first representation of an output voltage of the power converter corresponding to a first sampling timing and a positive terminal coupled to an output voltage value sampled at a second sampling timing subsequent to the first sampling timing. The comparator compares the values on the positive and negative terminals, and outputs a positive value (typically, +1 or some other positive value) if the output voltage value sampled at the second sampling timing is greater than the first representation of the output voltage of the power converter corresponding to the first sampling timing or a negative value (typically, −1 or some other negative value) if the output voltage value sampled at the second sampling timing is less than the first representation of the output voltage of the power converter corresponding to the first sampling timing. The accumulation module accumulates the positive value or the negative value output from the comparator to obtain a second representation of the output voltage of the power converter corresponding to a second sampling timing.
The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.
The embodiments of the present invention will be described below with reference to the accompanying drawings. Like reference numerals are used for like elements in the accompanying drawings.
Referring to
The controller 300 receives various input parameters for use in controlling the switch Q1. The controller 300 receives a Vcc (supply voltage) via the startup resistor R8, a divided-down version (VSENSE) of the reflected secondary voltage on the auxiliary windings of the transformer T1, a reference voltage VREG of the controller 300, a zero voltage switching voltage Vzvs, an input voltage VIN which is a scaled version of VBULK, the primary current sense voltage ISENSE sensing the current flowing through switch Q1 in terms of a voltage across the network of resistors R4, R5, and R6, and Power Ground (PGND), and generates a control signal OUTPUT coupled to the switch Q1 for controlling the on-times and off-times of the switch Q1. The diode D5 rectifies the output voltage on the secondary windings of the transformer T1 and the capacitor C5 filters the output voltage signal on the secondary windings of the transformer T1 for outputting as V-OUT.
As shown in
As can be seen from
The accumulator 502 accumulates the differences between VSENSE sampled at the current sampling timing and the representation of VSENSE corresponding to the previous sampling timings to obtain the current representation of VSENSE at the current sampling timing. Thus, the accumulator 502 executes the following accumulation function:
S(n)=S(n−1)+ΔS(n),
where S(n) is the sum corresponding to the current sampling timing (cycle) representative of the value of VSENSE at the current sampling timing (tn), S(n−1) is the sum corresponding to the preceding sampling timing (cycle) representative of the value of VSENSE at the preceding sampling timing (tn−1), and ΔS(n) is the difference between VSENSE and S(n−1), i.e., ΔS(n)=VSENSE−S(n−1). Thus, S(n)=S(n−1)+ΔS(n)=S(n−1)+VSENSE−S(n−1)=VSENSE. Thus, the accumulator 502 provides S(n), i.e., a digital representation of VSENSE at the current sampling timing (tn) without any sample-and-hold circuitry. Since S(n) is obtained as a digital value, it is also compatible with the remaining components (not shown) of the switch controller 300 that digitally generate the on-timings (tON) and off-timings (tOFF) for the switch Q1 to regulate the output voltage V-OUT of the power converter. The accumulator 502 is clocked by the sampling timing signals (tn). The preceding sampling timing (tn−1) may immediately precede the current sampling timing (tn) or precede the current sampling timing (tn) by two or more cycles.
The D/A converter 506 receives S(n−1) corresponding to the preceding sampling timing (tn−1) as a digital value 504 and converts it to an analog value 507 corresponding to S(n−1). The analog value 507 of S(n−1) is compared to VSENSE in the comparator 510.
In one embodiment, the comparator 510 is a digital differencer that compares the magnitudes of the values of VSENSE to S(n−1) and outputs a digital value 512 representative of the difference between the two values, i.e., ΔS(n)=VSENSE−S(n−1). In another embodiment, the comparator 510 is a binary comparator that merely generates +1 (or some other positive value) if VSENSE is larger than S(n−1) or −1 (or some other negative value) if VSENSE is less than S(n−1) as its output 512.
The sampling period Δt is the difference in time between two successive sampling timings, i.e., Δt=tn−tn−1. In one embodiment, the sampling timings are regularly spaced such that the sampling period Δt is uniform for every switching cycle (n, n+1, n+2 . . . ). However, in other embodiments, the sampling timings need not be regularly spaced and Δt does not have to be uniform for every switching cycle.
In one embodiment, the sampling period Δt is set such that the sampling frequency (1/Δt) exceeds at least twice the frequency of VSENSE (to satisfy the Nyquist sampling theorem and generally avoid aliasing), regardless of whether the sampling period Δt is the uniform for every switching cycle. However, even with such sampling frequency (1/Δt) exceeding twice the frequency of VSENSE, it is still possible for aliasing to occur for periodic signals whose frequency is approximately the same as the sampling frequency (1/Δt).
Therefore, in another embodiment, the sampling frequency (1/Δt) is set such that the sampling frequency (1/Δt) is much higher than the frequency of VSENSE in order to avoid under-sampling. For example, the sampling frequency (1/Δt) is set at least 10 times higher than the frequency of VSENSE. If the sampling period Δt is not uniform, then the sampling frequency (1/Δt) is set such that the minimum of the sampling frequencies (1/Δt) is much higher than the frequency of VSENSE in order to avoid under-sampling. For example, the minimum of the sampling frequency (1/Δt) is set at least 10 times higher than the frequency of VSENSE.
In another embodiment, the switch controller 300 is also capable of detecting excessively high or low values of VSENSE that are out of range of the switch controller 300. Thus, the comparator 516 compares the value of VSENSE at the sampling timing (tn) to a predetermined maximum value for VSENSE (VSENSE,max) and generates a FlagMax signal 520 of “ 1” when the value of VSENSE at the sampling timing (tn) exceeds the predetermined maximum value for VSENSE (VSENSE,max). Otherwise, the comparator 516 generates a FlagMax signal 520 of “0.” The comparator 514 compares the value of VSENSE at the sampling timing (tn) to a predetermined minimum value for VSENSE (VSENSE,min) and generates a FlagMin signal 518 of “1” when the value of VSENSE at the sampling timing (tn) is less than the predetermined minimum value for VSENSE (VSENSE,min). Otherwise, the comparator 514 generates a FlagMin signal 518 of “0.” The accumulator 502 includes logic (not shown) that sets S(n) for the sampling timing (tn) to VSENSE,max when FlagMax 520 is “1” or to VSENSE,min when FlagMin 518 is “1.”
As the process starts 602, the switch controller 300 receives 604 the VSENSE sample sampled at the current sampling timing (tn). Then, the switch controller 300 determines 606 whether the sampled VSENSE value exceeds a predetermined maximum value, VSENSE, max. If the sampled VSENSE value exceeds the predetermined maximum value, VSENSE, max, the switch controller sets 608 S(n) to be equal to VSENSE, max. Then, the switch controller 300 determines 610 whether the sampled VSENSE value is less than a predetermined minimum value, VSENSE, min. If the sampled VSENSE value is less than the predetermined minimum value, VSENSE, min, then the switch controller sets 612 S(n) to be equal to VSENSE,min.
Finally, the switch controller accumulates 614 the differences between the VSENSE value sampled at the current sampling timing and the value representative of VSENSE corresponding to the preceding sampling timing, by performing S(n)=S(n−1)+ΔS(n), where S(n) is the sum corresponding to the current sampling timing (cycle) representative of the value of VSENSE at the current sampling timing (tn), S(n−1) is the sum corresponding to the preceding sampling timing (cycle) representative of the value of VSENSE at the preceding sampling timing (tn−1), and ΔS(n) is the difference between the sampled VSENSE value and S(n−1), i.e., ΔS(n)=VSENSE−S(n−1). Then, the process returns 604 to receive the sampled VSENSE value corresponding to the next sampling timing.
Although the present invention has been described above with respect to several embodiments, various modifications can be made within the scope of the present invention. For example, the present invention is not limited to any topology of AC-to-DC power converter, and can be used with flyback type AC-to-DC power converters, boost type AC-to-DC power converters, and the like. The accumulator 502 described herein may be implemented by digital logic circuits, state machines, or other types of circuitry to the extent that it can perform the accumulation functions as described herein. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.
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