Patent Application
20220126576
The present disclosure relates to a recording element substrate for a liquid ejection head, the liquid ejection head and a recording apparatus.
In general, a recording element substrate mounted on a liquid ejection head includes one time programmable (OTP) ROM for recording unique information such as product information and setting information. As an example of OTPROM, one of a fuse element and an antifuse element is used. Japanese Patent Application Laid-Open No. 2014-58130 describes, as OTPROM including an antifuse element, an example in which a resistor element is connected in parallel with the antifuse element in order to prevent erroneous recording.
In a configuration described in Japanese Patent Application Laid-Open No. 2014-58130, the resistance value of the resistor element connected in parallel with the antifuse element in order to prevent erroneous recording may deviate from a predetermined value causing a faulty reading of the antifuse element.
The present disclosure features a recording element substrate for a liquid ejection head, the recording element substrate including a storage section having an antifuse element and a first resistor connected in parallel with the antifuse element, and a first switch connected to the storage section, and a second resistor that is connected in parallel with the storage section and serves as a reference in rating information of the antifuse element, and a second switch connected to the second resistor.
Further features of the present disclosure will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
An aspect of the present disclosure is to provide a recording element substrate that can reduce the occurrence of faulty readings of an antifuse element.
The recording element substrate for a liquid ejection head, the liquid ejection head and a recording apparatus according to the present disclosure will be described below with reference to the accompanying drawings. The recording element substrate of a thermal type will be described as an example of the present disclosure. The present disclosure is not limited to the thermal type and may be applied to a piezo-type recording element substrate for a liquid ejection head.
Referring to
(The Circuits of the Recording Element Substrate)
Referring to
The ejection module 204 includes a pressure generating element (electrothermal transducer) Rh that generates energy for ejecting liquid from the ejection orifice (not illustrated) formed on the recording element substrate, a drive element MD1 for driving the pressure generating element Rh and a logic circuit AND1. The drive element MD1 is a MOS transistor in the present embodiment. In this configuration, the MOS transistor acts as a switch that determines whether a voltage is applied to the pressure generating element Rh. The logic circuit AND1 is an AND circuit for driving the drive element MD1 based on a signal from the control data supply circuit 201 and performs logical operations on a plurality of signals. The pressure generating element Rh is driven, that is, the pressure generating element Rh is energized to generate heat and bubbles are generated in ink so as to eject liquid from the ejection orifice, enabling recording. A power supply voltage VH (e.g., 24 V) is supplied to the pressure generating element Rh. A ground potential GNDH is supplied to the source of the MOS transistor MD1.
The memory module 206 includes an antifuse element Ca, a parallel resistance Rp (resistor) connected in parallel with the antifuse element Ca, a drive element MD2 for writing information in the antifuse element Ca and a logic circuit AND2. The antifuse element Ca holds information in a fixed manner by the supply of overvoltage. In other words, the antifuse element Ca acts as one time programmable (OTP) ROM that is programmable only one time. The antifuse element Ca is insulated before an overvoltage is supplied. When an overvoltage is supplied, the antifuse element Ca acts as a resistor element (resistor) and is energized. Thus, for example, the antifuse element Ca in an insulated state is rated as 0, whereas the antifuse element Ca in an energized state is rated as 1, enabling a memory function. The parallel resistance Rp is provided to prevent an overvoltage applied across the antifuse element Ca from a power supply voltage VID from causing erroneous writing of information in the antifuse element Ca even if the drive element MD2 is non-conducting. The drive element MD2 is, for example, a transistor. When information of 1 is recorded in the antifuse element Ca, the drive element MD2 is driven so as to apply a voltage to the antifuse element Ca. The applied voltage energizes the antifuse element Ca, so that the information of 1 is stored.
The power supply voltage VID (e.g., 24 V) is supplied to the antifuse element Ca and the ground potential GNDH is supplied to the source of the MOS transistor MD2.
Although the power supply voltage VID and the power supply voltage VH are on mutually independent lines, if the minimum value of a voltage required for writing in the antifuse element is not higher than the power supply voltage VH, the power supply voltage VH may be used along with, for example, a step-down circuit.
The memory correction module 208 includes a memory reference resistance Rref, a drive element MD3 for reading the memory reference resistance Rref, and a logic circuit AND3. In this configuration, the memory reference resistance Rref has the same resistance value as the parallel resistance Rp. The same resistance value means substantially the same resistance value, and the same resistance value holds even if there is a slight difference in resistance values due to a manufacturing error or the like. The memory correction module 208 is configured to reduce the occurrence of faulty reading of the antifuse element Ca, which will be specifically described later. The power supply voltage VID is supplied to the memory correction module 208 and the ground potential GNDH is supplied to the memory correction module 208. Although the power supply voltage VID and the power supply voltage VH are on mutually independent lines, if the minimum value of a voltage required for writing in the antifuse element Ca of the memory module 206 is not higher than the power supply voltage VH, the power supply voltage VH may be used along with, for example, a step-down circuit.
The control data supply circuit 201 is a circuit for driving the drive elements MD1, MD2 and MD3 and includes, for example, a shift register (not illustrated) and a latch circuit (not illustrated). Moreover, the control data supply circuit 201 includes a selection circuit that selects which one of the resistor element Rp or the resistor element Rref is to be subjected to voltage measurement during reading of the information of the antifuse element Ca, which will be described later. Alternatively, a circuit including a control data supply circuit, signal lines 202, 203 and 205 and a logic circuit may be referred to as a selection circuit. A clock signal (CLK), a data signal (DATA), a latch signal (LT) and a heat enable signal (HE) are input to the control data supply circuit 201 from the outside of the recording element substrate via the terminal of the recording element substrate. The data signal (DATA) includes information for selecting the ejection module 204, the memory module 206 and the memory correction module 208. The data signal (DATA) is serially input based on the clock signal (CLK).
The control data supply circuit 201 receives the data signal (DATA) and generates a block selection signal, a group selection signal and a switching signal based on the information included in the data signal (DATA). Based on these signals, the ejection module 204, the memory module 206 and the memory correction module 208 are selected and driven. To the logic circuits (AND1 to ANDS), the control data supply circuit 201 supplies the block selection signal via the signal line 202, supplies the group selection signal via the signal line 203, and supplies the switching signal via the signal line 205.
In order to drive the modules 204, 206 and 208 in a time-sharing manner, as illustrated in
In this embodiment, the multiple ejection modules 204 are divided into eight groups (G1, . . . , G8), each including three ejection modules. The present embodiment is not limited to this configuration. For example, the ejection modules may be divided into eight groups, each including 16 ejection modules.
The antifuse element Ca can be driven by using the signal line 202 and the signal line 203. At this point, the switching signal line 205 is used. The switching signal from the switching signal line 205 is used to switch between when to drive the antifuse element Ca and when to drive the ejection module 204. Thus, the block selection signal, the group selection signal and the switching signal are input to the logic circuit AND2 for the memory module. Subsequently, a signal (a control signal Sig in
The block selection signal, the group selection signal and the switching signal are similarly input to the logic circuit AND3 for the memory correction module. Subsequently, a signal (the control signal Sig in
Which one of the antifuse elements Ca of the memory modules 206 is to be chosen for writing information can be determined by the block selection signal, the group selection signal and the switching signal based on the signals CLK, DATA, LT and HE.
(Writing in the Antifuse Element)
Referring to
In addition to switching of SW1, the control unit 302 enables the generation of the clock signal (CLK), the data signal (DATA), the latch signal (LT) and the heat enable signal (HE) that are output to the control data supply circuit 201. The control unit 302 is made up of, for example, a CPU or an ASIC.
A terminal A is connected to a writing power supply installed in an inkjet recording apparatus or the like and a terminal B is connected to a ground installed in an inkjet recording apparatus or the like. When information is to be written in the antifuse element, the memory drive element MD2 is turned on by inputting a low-level signal as the control signal Sig. Thus, a high voltage VID is applied to a gate oxide film constituting the antifuse element Ca. This breaks the gate oxide film and brings the antifuse element Ca into conduction of electricity, achieving writing of information. The antifuse element Ca acts as a capacitance element before writing, whereas the antifuse element Ca acts as a resistor element Ra after writing. In the two memory modules 206, a memory module A indicates a state in which information is not written in the antifuse element Ca (in the absence of dielectric breakdown). A memory module B indicates a state in which information is written in the antifuse element and the antifuse element acts as the resistor element Ra (in the presence of dielectric breakdown).
(Reading Operation)
Referring to
In the present embodiment, when a constant current is supplied from the current source 207 to the terminal A, a Vout voltage generated on the terminal A is read by a recording apparatus or the like, so that a writing state of the antifuse element Ca is identified. First, in a state in which information is not written in the antifuse element Ca as in the memory module A, the antifuse element Ca is insulated. Thus, if the drive element MD2 has an on resistance value Rd2 and the current source 207 has a current value is, an output voltage Vouta is expressed by the following Formula 1:
Vouta=is×(Rp+Rd2) (Formula 1)
For example, in the case of is =30 μA, Rp=100 kΩ and Rd2=1 kΩ, the output voltage Vouta is about 3.0 V.
In a state in which information is written in the antifuse element Ca as in the memory module B, the antifuse element Ca acts as the resistor element Ra and thus if the memory drive element MD2 has the on resistance value Rd2, an output voltage Voutb is expressed by the following Formula 2:
Voutb=is×((Ra×Rp)/(Ra+Rp)+Rd2) (Formula 2)
For example, in the case of is =30 μA, Rp=100 kΩ, Rd2=1 kΩ and Ra=1 kΩ, the output voltage Voutb is 0.1 V or less.
If the drive element MD3 for the memory reference resistance has an on resistance Rd3, an output voltage Vref during reading of the memory correction module 208 is expressed by the following Formula 3:
Vref=is×(Rref+Rd3) (Formula 3)
For example, in the case of is =30 μA, Rref=100 kΩ and Rd3=1 kΩ, the output voltage Vref is about 3.0 V.
The writing state of the antifuse element Ca is identified by a judgment value D of the following Formula 4:
D=Vout/(Vref×r) (Formula 4)
where r is a variable for optionally determining a judgment threshold value. The judgment threshold value may be determined according to variations in resistance Ra after writing of the antifuse element Ca. Specifically, the maximum value of variations in Ra is about 20 kΩ during writing under a certain condition. If Rref has a center value of 100 kΩ, r=0.5 is set. At this point, the judgment values D of the memory modules A and B are determined as follows:
Da=Vouta/(Vref×0.5)=3.0/(3.0×0.5)=2.0
Db=Voutb/(Vref×0.5)=0.5/(3.0×0.5)=0.33
If the judgment value D is at least 1, the memory module is rated as unwritten, whereas if the judgment value D is less than 1, the memory module is rated as written. For example, the memory module A is rated as unwritten because a judgment value Da is at least 1. The memory module B is rated as written because a judgment value Db is less than 1. Although in this embodiment, the parallel resistance Rp and the memory reference resistance Rref are at the same value of 100 kΩ and a variable r is used for determination, Rref may be provided with such a resistance value that serves as a judgment threshold value and determination may be made by comparing Vout and Vref to see which is larger or smaller.
As described above, diffusion resistors are used for the parallel resistance Rp and the memory reference resistance Rref. The resistance value of the diffusion resistor considerably varies during manufacturing and greatly changes according to a temperature with a temperature coefficient of at least 1000 ppm/° C. For example, in the case of manufacturing variations of ±50% with a temperature characteristic of 4000 ppm/° C., the resistance value of the parallel resistance Rp is changed by 40% with a temperature change of 0 to 100° C. Thus, relative to a resistance value at 50° C., an output voltage is increased by 80% or is reduced by 60% according to manufacturing variations and temperature variations.
An impedance before writing of the antifuse element depends on the resistance value of the parallel resistance Rp and thus as indicated in
Vouta′=is ×(α×Rp+Rd2) (Formula 1′)
Vref′=is ×(α×Rref+Rd3) (Formula 3′)
If on resistances Rd2 and Rd3 of MD2 and MD3 are sufficiently small relative to the parallel resistance Rp and the memory reference resistance Rref, the resistance variation α is cancelled by (Formula 1′) and (Formula 3′) and thus the judgment value D based on the formulas is expressed by the following formula 4′:
D=Vouta′/(Vref×r)=Rp/(Rref×r) (Formula 4′)
This formula proves that even if the parallel resistance Rp and the memory reference resistance Rref show variations, the variations cancel each other out in the absence of relative variations at the same temperature, so that the judgment value D does not depend on variations in parallel resistance Rp. In some inkjet recording patterns, some of the recording elements Rh may intensively repeat heat generation so as to bias a temperature distribution in the recording element substrate. Thus, in order to reduce a difference in resistance value between the parallel resistance Rp and the reference resistance Rref due to a temperature, it is desirable to dispose the parallel resistance Rp and the reference resistance Rref next to each other. For example, it is desirable that the reference resistance Rref be disposed for each group for time-division driving and during reading, the memory module be read to calculate the judgment value immediately after the closest memory correction module is read. In the absence of the adjacent memory correction module, the judgment value D may be determined by predicting a Vref value according to the read values of the two or more memory correction modules, the positional relationship of the modules and an estimated temperature distribution.
Furthermore, in the present embodiment, it is expected to have the effect of cancelling variations in the current value of a reading circuit, variations in read voltage, and variations in the parasitic resistances of a wire and an electric contact in order to compare the measured values of Vout and Vref.
The present embodiment described a circuit configuration in which a node connected to the memory module and a node connected to the memory correction module serve as the common terminals A and B. The nodes may be connected as different terminals to an inkjet recording apparatus or the like.
In the present embodiment, the recording element Rh is an electrothermal transducer but may be a piezoelectric element.
Reference numeral 103 denotes a field oxide film having a LOCOS structure. Reference numeral 104 denotes a gate oxide film that is formed in the step of the gate oxide film of a CMOS transistor constituting a low voltage logic circuit.
Reference numerals 105a and 105b denote polysilicon layers. Reference numeral 105a serves as the gate electrode of the high-voltage NMOS transistor MD2 and reference numeral 105b serves as the electrode of a capacitor acting as the antifuse element Ca. Reference numerals 106a to 106e denote high-concentration n-type diffusion regions. Reference numeral 107 denotes a high-concentration p-type diffusion region. The polysilicon layer, the high-concentration n-type diffusion regions and the high-concentration p-type diffusion regions are formed by the same steps as the steps of a CMOS transistor constituting a low voltage logic circuit.
Reference numeral 108 denotes a contact portion and reference numerals 109a to 109d denote metal wires. The manufacturing method and structures of the metal wires 109a to 109d and the electrodes are not limited as long as the metal wires and the electrodes are electrically connected to one another.
The configuration of the high-voltage NMOS transistor will be described below. The gate electrode 105a is disposed on the gate oxide film 104 over the P-well region 101 and the N-well region 102a adjacent to each other. An overlapping region between the P-well region 101 and the gate electrode 105a serves as a channel region. The high-concentration n-type diffusion region 106a is a source electrode and the high-concentration p-type diffusion region 107 is a back gate electrode. The N-well region 102a extending to the bottom of the gate electrode 105 is disposed as an electric field relaxation region for a drain. The high-concentration n-type diffusion region 106b formed in the N-well region 102a serves as a drain electrode. Furthermore, the drain side of the gate electrode 105a hangs over the field oxide film 103 formed in an N-well 102, presenting a so-called LOCOS offset structure. Thus, even if the high-voltage NMOS transistor is placed in an off state, that is, the gate electrode has a voltage GND and the voltage of the drain electrode rises to the high voltage VID, a gate-drain breakdown voltage can be obtained.
The structure of the antifuse element Ca will be described below. The electrode 105b is disposed on the gate oxide film 104 over the N-well region 102b as the upper electrode of the antifuse element Ca. The high-concentration n-type diffusion region 106c is disposed as the lower electrode on the N-well region 102b.
In
The parallel resistance Rp will be described below. The parallel resistance Rp can be set at several tens kΩ or higher in order to increase a difference in impedance before and after writing. A diffusion resistor using diffusion is used as a high-resistance element.
The connection states of the electrodes will be described below. The metal wire 109a is connected to the source electrode and the back-gate electrode of the high-voltage NMOS transistor via the contact portion 108 and receives a GND potential. The metal wire 109b is connected to the gate electrode of the high-voltage NMOS transistor via the contact portion 108 and receives an output signal Vg input from an inverter circuit illustrated in
Referring to
In response to the output signal of a control data supply circuit 201, the memory modules 206 and the memory correction modules 208 are controlled in each of y groups, the group including the x memory modules 206 and the at least one memory correction module. Specifically, each of the memory modules 206 receives at least one bit of a block selection signal through a signal line 202, a group selection signal through a signal line 203 and a switching signal through a signal line 205, thereby driving the antifuse element Ca in a time-sharing manner. Each of the memory correction modules 208 similarly receives at least one bit of the block selection signal, the group selection signal and the switching signal, thereby driving a memory reference resistance Rref in a time-sharing manner. At this point, one of the ejection module 204 and the memory module 206 is selected to be driven by the switching signal and a logical configuration is obtained such that all pressure generating elements Rh and all the antifuse elements Ca are not driven at the same time. Likewise, one of the memory correction module 208 and the ejection module 204 is selected to be driven by the switching signal and a logical configuration is obtained such that all the pressure generating elements Rh and all the memory reference resistances Rref are not driven at the same time.
In the case of the 1-bit switching signal, x′≤n is established where x′ is the total number of antifuse elements Ca and memory reference resistances Rref in one memory group and n is the number of time-division selection signals and y≤m is established where y is the number of memory groups and m is the number of block selection signals. Alternatively, a recording element/the memory switching signal of multiple bits may be provided to control the antifuse elements Ca and the memory reference resistances Rref such that the number of antifuse elements Ca and memory reference resistances Rref exceeds (n×m).
A reading operation will be described below. A basic reading operation is identical to the reading operation of the first embodiment. However, in the configuration including the multiple memory correction modules 208, writing of the memory module 206 may be determined in comparison with the closest memory correction module 208 in consideration of manufacturing variations and a temperature distribution in the recording element substrate.
Referring to
As illustrated in
As illustrated in
Referring to
Also for the resistances Rs1 and Rs2 for generating comparison voltages, configurations are identical to configurations for the memory reference resistance Rref and the parallel resistance Rp. The memory reference resistance Rref and the resistances Rs1 and Rs2 for generating comparison voltages are changed according to the resistance value of the parallel resistance Rp, thereby preventing reliability from decreasing during reading. The same configuration specifically means the same diffusion resistor and more preferably a design having the same width and length.
The present disclosure can reduce the occurrence of faulty reading of the antifuse element.
While the present disclosure has been described with reference to exemplary embodiments, it is to be understood that the disclosure is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2018-247776 | Dec 2018 | JP | national |
This application is a Continuation of U.S. patent application Ser. No. 16/723,955, filed Dec. 20, 2019, which claims the benefit of Japanese Patent Application No. 2018-247776, filed Dec. 28, 2018, both of which are hereby incorporated by reference herein in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16723955 | Dec 2019 | US |
| Child | 17569946 | US |
