Patent Application
20210191438
This application claims priority to India Provisional Application No. 201941053150, filed Dec. 20, 2019, which is hereby incorporated by reference.
One type of voltage regulator is a low drop-out (LDO) voltage regulator. Some LDO voltage regulators include an error amplifier that amplifies the difference between a reference voltage (which itself is generated by a separate error amplifier) and an output voltage from the regulator to thereby generate an error signal. The error amplifier continuously generates the output error signal which is used to adjust the gate-to-source voltage (VGS) of a transistor (sometimes referred to as a pass-FET (field effect transistor)) to modulate the current to a bad powered by the regulator, thereby regulating the output voltage.
Some LDO voltage regulators include a reference voltage generator circuit that can scale (up or down) the magnitude of the reference voltage commensurate with the intended magnitude for the output voltage. The reference voltage may have noise superimposed on it due to noise generated by, for example, a bandgap voltage source and a separate error amplifier (separate from the error amplifier that controls the pass-FET) used to generate the scaled reference voltage. As the reference voltage is increased, the magnitude of the reference voltage's noise also increases. Because of reference voltage noise, some LDO voltage regulators include a low-pass filter to attenuate the noise. The bandwidth of the low-pass filter is fairly small. In one example, the 3-dB roll-off frequency for the low-pass filter is 1 Hz.
In one example, a circuit includes a reference voltage generator circuit and a regulation loop circuit having an output voltage terminal. The regulator circuit further includes a fault detection circuit having a first input terminal coupled to the output voltage regulator terminal of the regulation loop circuit. The fault detection circuit asserts, on an output terminal of the fault detection circuit, a fault flag signal responsive to a voltage on the first input terminal falling below a first threshold. A programmable filter is coupled between the reference voltage generator circuit and the regulation loop circuit and is coupled to the fault detection circuit. The programmable filter has a configurable time constant. The programmable filter responds to an assertion of the fault flag signal by decreasing the time constant.
For a detailed description of various examples, reference will now be made to the accompanying drawings in which:
The reference voltage generator circuit 110 includes a bandgap voltage source 111 which produces a bandgap voltage (VBG), a first error amplifier 112, a transistor M_PASS1, and resistors R1 and R2. A bandgap voltage source is a temperature independent voltage reference circuit that produces a fixed voltage regardless of power supply variations, temperature changes and circuit loading from a device. A Brokaw bandgap reference circuit is one such circuit. Transistor M_PASS1 is implemented in this example as a p-type metal oxide semiconductor field effect transistor (PFET transistor) having a gate, a source, and a drain. The voltage on the drain of M_PASS1 is VREF1. Resistors R1 and R2 are connected in series between the drain of M_PASS1 and ground. The series combination of R1 and R2 forms a voltage divider 117 to generate a feedback voltage, VFB, which is proportional to VREF1. The feedback voltage VFB is coupled to a positive input of the error amplifier 112 in this example. The bandgap voltage source 111 is coupled to the negative input of the error amplifier 112. The error amplifier 112 generates an error signal, ERROR1, on the output of the error amplifier 112 which is coupled to the gate of M_PASS1. The error amplifier 112, M_PASS1, and the voltage divider of R1 and R2 form a control loop. The error amplifier 112 amplifies the difference between VFB (derived from VREF1) and VBG (produced by the bandgap voltage source 111) to generate error signal ERROR1. Responsive to VFB being larger than VBG, ERROR1 will increase, and responsive to VFB being smaller than VBG, ERROR1 will decrease.
A decrease in VFB will cause a decrease in the voltage level of ERROR1 thereby causing an increase in the VGS of M_PASS1. An increase in the VGS of M_PASS1 causes an increase in the drain current through M_PASS1 and thus an increase in the current to the voltage divider 117, thereby increasing VREF1. Conversely, an increase in VFB will cause an increase in the voltage level of ERROR1 thereby causing a decrease in the VGS of M_PASS1. A decrease in the VGS of M_PASS1 causes a decrease in the drain current through M_PASS1 and thus a decrease in the current to the voltage divider of R1 and R2, thereby decreasing VREF1. VREF1 is regulated in this manner.
The control loop formed by the error amplifier 112, M_PASS1, and the voltage divider of R1 and R2 helps to sure that VFB will be approximately equal to VBG from the bandgap voltage source 111. The voltage level of VREF1 can be scaled up and down by modulating the resistance of resistor R1 in the voltage divider 117. Resistor R1 may be implemented as a resistor ladder and a corresponding digital switch for each resistive branch of the ladder. The digital switches can be opened or closed by values stored in a storage device (e.g., read only memory) that itself is programmed during manufacturing. For a given current through the voltage divider 117 and with a fixed R2 resistance, an increase in the resistance of R1 will result in an increase in the voltage of VREF1, while a decrease in the resistance of R1 will result in a decrease in the value of VREF1.
The programmable filter 130 includes a programmable resistor R3 coupled to a capacitor C1 to thereby form an RC-based low-pass filter. The programmable resistor R3 has terminals 131, 132, and 133. Terminal 131 is coupled to the drain of M_PASS1 and thus receives VREF1 from the reference voltage generator circuit 110. Terminal 132 is coupled to C1 and provides a filtered version of VREF1 (labeled as VREF) to the regulation loop circuit 150. Terminal 133 is a control input of the programmable resistor R3 and can be used to set the resistance of R3. In one example the programmable resistor R3 comprises a resistor network with switches that can be opened or closed to configure the resistor network for a target resistance. Other implementations for programmable resistors are possible as well.
The regulation loop circuit 150 comprises a second error amplifier 152 coupled to transistor M_PASS2. Like M_PASS1, M_PASS2 also may be implemented as a PFET transistor having a gate, a source, and a drain. The output 151 of error amplifier 152 is coupled to the gate of M_PASS2. The source of M_PASS2 is coupled to a terminal 154 which receives VIN. The drain of M_PASS2 is the output voltage terminal 155 of the voltage regulator circuit 100 and provides the regulated output voltage VOUT to any load connected thereto. In
The output voltage terminal 155 is coupled to the positive input of error amplifier 152 as a feedback signal. The filtered reference voltage VREF is coupled to the negative input of the error amplifier 152. The error amplifier 152 amplifies the difference between VREF and VOUT to generate an error signal, ERROR2, which is then used to drive the gate of M_PASS2. Responsive to VOUT increasing, ERROR2 will increase, and responsive to VOUT decreasing, ERROR2 will decrease. An increase in VOUT will cause an increase in the voltage level of ERROR2 thereby causing a decrease in the VGS of M_PASS2. A decrease in the VGS of M_PASS2 causes a decrease in the drain current through M_PASS2 and thus a decrease in the load current IL to the load thereby decreasing VOUT. Conversely, a decrease in VOUT will cause a decrease in the voltage level of ERROR2 thereby causing an increase in the VGS of M_PASS2. An increase in the VGS of M_PASS2 causes an increase in the drain current through M_PASS2 and thus an increase in the load current IL thereby increasing VOUT. VOUT is regulated in this manner.
Voltage regulators are designed for a particular range of VIN. VIN must be within the specified range for the voltage regulator to adequately regulate VOUT to its target level. During run-time when VIN is within the specified operational range, the effective resistance of programmable resistor R3 (i.e., the resistance between its terminals 131 and 132) is configured for a resistance large enough that the 3-dB cutoff frequency is relatively low (e.g., 1 Hz). Setting the 3-dB cutoff frequency at a relatively low frequency (for adequate filtering of the aforementioned noise) means that the RC time constant of the programmable filter 130 is relatively high.
The UVLO and EN logic 160 monitors an enable (EN) signal 167. The EN signal 167 enables and disables the voltage regulator circuit 100. The EN signal is, in some examples, an externally-provided signal (external to the integrated circuit containing the voltage regulator circuit 100). The UVLO and EN logic 160 may include a digital inverter or Schmitt trigger circuit to identify that the EN signal 167 has a rising or falling edge. When the voltage level on the EN signal 167 is lower than a pre-defined enable threshold, the LDO will be turned or maintained off by the UVLO and EN logic 160. The UVLO and EN logic 160 includes a comparator to determine when the EN signal 167 falls below the enable threshold. Responsive to the EN signal 167 falling below the enable threshold, the UVLO and EN logic 160 configures R3 for a smaller resistance so that, as described herein, the voltage regulator 100 can more quickly return to normal operation when the enable signal 167 again recovers to a normal operating level.
The UVLO and EN logic 160 also monitors VIN for a UVLO threshold. The UVLO threshold is a voltage lower than the nominal range of VIN and represents a level below which the voltage regulator 100 cannot adequately power internal circuitry of the voltage regulator. The UVLO and EN logic 160 includes a comparator to determine when VIN drops below the UVLO threshold. Responsive to VIN dropping below the UVLO threshold, the UVLO and EN logic 160 configures R3 for a smaller resistance so that, as explained above, the voltage regulator 100 can more quickly return to normal operation when VIN again recovers to a normal operating level. In one example, VOUT is 5 V and the drop-out voltage is 300 mV. The drop-out voltage is the headroom voltage above the target output regulated voltage VOUT that VIN must maintain. For VOUT equal to, for example, 5 V and with a 100 mV drop-out voltage, VIN must be at least 5.1 V (e.g., 5.1 V to 10 V) in such an example. In one example, the UVLO threshold is 1.6 V.
A brown-out event is an event in which VIN decreases below the minimum level of its target normal operating range but remains higher than the UVLO threshold. In the example of VOUT being 5 V, the UVLO threshold being 1.6 V, and a drop-out voltage of 100 mV, a brown-out event would be characterized by VIN being between 1.6 V and 5.1 V. In this latter range, VIN is not so low as to trigger a UVLO response by the UVLO and EN logic 160. Accordingly, the frequency response or time constant of the programmable filter 130 is not modified in the example of
The brown-out effect is illustrated in
At 216, the brown-out event ends and VIN quickly returns to its previous level 210 (e.g., 6 V). However, because VIN did not drop below the UVLO threshold, the configuration of the programmable filter 130 (i.e., its 3-dB cutoff frequency and time constant) did not change. Accordingly, the recovery of the filtered reference voltage (VREF) relatively slowly increases and thus VOUT also slowly increases as shown in
Upon the short circuit condition of VOUT ending at 316, VREF overshoots rapidly as shown to voltage level 320. The overshoot of VREF is due to the output of the voltage of the regulator circuit (drain of M_PASS2) quickly charging back to its regulated level. This quick charge of the output couples to the filtered reference terminal (negative input of error amplifier 152) through CPARA and charges up higher than the required level. The change in the reference voltage VREF further pushes the output voltage to modulate slightly. After this transient event, the filtered reference VREF begins to discharge as shown at 322 to its nominal value based on the time constant of the programmable filter 130. The time constant is relatively large and accordingly the VREF decays slowly as shown. Because VREF experienced an overshoot and then slow decay back to its nominal value, VOUT also slowly decays back to its nominal value as shown at 325. Due to the programmable filter 130 configured for a fairly large time constant during normal operation, a brown-out condition of VIN (which remains above the UVLO threshold) or a short of VOUT will result in VOUT taking an undesirable amount of time to recover following the end of the brown-out or short-circuit conditions.
The programmable filter 430 includes programmable resistor R3 coupled to capacitor C1 as described above, but also includes a switch SW1 coupled in series with a resistor R4. The series combination of switch SW1 and resistor R4 is coupled in parallel with programmable resistor R3. When switch SW1 is closed, resistor R4 is in parallel with programmable resistor R3. In one example, the resistance of resistor R4 is substantially smaller than the resistance of programmable resistor R3. Accordingly, with switch SW1 closed, the effective resistance of the parallel combination of resistors R3 and R4 is close to, but below the resistance of R4. The change in the effective resistance of the programmable filter 430 from a larger resistance to, upon closure of switch SW1, a smaller resistance causes the 3-dB cutoff frequency of the filter to increase thereby reducing the associated time constant.
The switch SW1 includes a control terminal 435 coupled to an output 421 of delay control circuit 420. The fault detection circuit 410 includes terminals 411 and 412. VIN is coupled to terminal 411 and VOUT is coupled to terminal 412. The fault detection circuit 410 monitors the voltage levels of VIN and VOUT and generates a fault flag (FF) signal 415 on its output 414. The output 414 of the fault detection circuit 410 is coupled to an input 418 of the delay control circuit 420. The FF signal 415 is forced to a first logic state by the fault detection circuit 410 when neither VIN is below a threshold voltage level nor VOUT is below a threshold voltage level (the two threshold voltage levels may or may not be the same voltage level). When either or both VIN or VOUT drops below its corresponding threshold voltage level, the fault detection circuit 410 responds by asserting the FF signal 415 to a second logic state. The first logic state (neither VIN nor VOUT is below its threshold) may be logic low (0) and the second logic state (VIN or VOUT dropping below its threshold) may be logic high (1). In other implementations, the first logic state may be logic high (1) and the second logic state may be logic low (0).
In an example, the threshold voltage level to which VIN is compared is greater than the UVLO threshold implemented by the UVLO and EN logic 160 but below the minimum nominal level of VIN (i.e., the target regulated level for VOUT plus the drop-out voltage of the voltage regulator). In the numerical example described above, the UVLO threshold is 1.6 V, the drop-out voltage is 100 mV, the regulated level of VOUT is 5 V, and thus the threshold voltage level to which VIN is compared within the fault detection circuit 410 is greater than 1.6 V but less than 5.1 V. The threshold voltage level to which VOUT is compared is less than its regulated level. In one example, the threshold voltage level to which VOUT is compared is a value that is 50% of the regulated level for VOUT, but can have a value other than 0.5×VOUT.
As will be explained below, the delay control circuit 420 delays a deassertion of the FF signal 415. For example, if the FF signal 415 is normally logic low and is asserted high when either or both of VIN or VOUT drops below their respective threshold voltage level, the initial transition of the FF signal 415 from low to high is not delayed by the delay control circuit 420. However, when the fault condition terminates (e.g., VIN and VOUT returning to levels above their respective threshold voltages), the FF signal 415 transitions from the active fault state (logic high) back to logic low. This latter falling edge of the FF signal 415 is delayed by the delay control circuit 420. Accordingly, the output signal 425 (labeled as FF_DLY) generated by the delay control circuit 420 on its output 421 has a rising edge generally coincident with the initial rising edge of the FF signal 415 from the fault detection circuit, but has a falling edge that delayed from the falling edge of the FF signal 415. The additional delay implemented by the delay control circuit 420 maintains switch SW1 ON (closed) even after completion of the brown-out event to ensure proper recovery of filtered reference VREF.
The FF_DLY signal 425 is provided to the control input 435 of switch SW1. With FF_DLY signal 425 at a logic low level, the switch SW1 will be off (open). With FF_DLY signal 425 at a logic high level, the switch SW1 will be on (closed). As noted above, the logic polarity of the FF signal 415 can be the opposite from that described above. In general, switch SW1 is maintained in an off state when both VIN and VOUT are above their respective reference voltage levels, and switch SW1 is closed when either or both of VIN or VOUT have fallen below their respective reference voltage levels. Accordingly, when a VIN or VOUT fault occurs (VIN dropping below its nominal value of VOUT plus the drop-out voltage, or VOUT dropping below its threshold potentially indicating VOUT being shorted to ground), the FF signal 415 is asserted which, through the delay control circuit 420 causes switch SW1 to close. Closing SW1 causes a decrease in the time constant of the programmable filter 430 thereby permitting a much faster recovery of VOUT following cessation of the VIN or VOUT fault condition.
The VIN fault detect circuit 910 comprises a transistor coupled to M_PASS1 in a configuration to sense the drain current through M_PASS1, and accordingly is referred to as a sense transistor, MSNS. That is, the gate of MSNS is coupled to the gate of M_PASS1 and the source of MSNS is coupled to the source of M_PASS1 at terminal 411 (VIN). The size of MSNS (e.g., the ratio of its channel width (W) to its channel length (L)) may be the same or smaller than the size of M_PASS1. In any event, the drain current (ISNS) through MSNS is generally a function of the drain current through M_PASS1. The drain of MSNS is coupled to a current source IFIX1 (IFIX1 refers both to the current source device/circuit as well as to the current through the current source).
Referring to
Transistors MM1 and MM2 form a current mirror (mirror ratio equal to 1 or a ratio other than 1). The drain of transistor MA is coupled to the drain of transistor MM1. Current source IFIX 2 is coupled between VIN and the drain of transistor MM2. The input 923 of inverter 922 is coupled to the drain of transistor MM2. The output of inverter 922 is coupled to an input of OR gate 930.
The output of the inverter 1212 is coupled to a latch circuit 1209. The latch circuit 1209 includes NAND gates 1213 and 1214, a delay element 1220 (e.g., resistor R5 coupled to capacitor C3 as shown), and a Schmitt trigger 1221. The output of the latch circuit 1209 comprises a signal called LATCH_OUT generated on the output of NAND gate 1213 and a signal (LATCH_OUT_DELAYED) generated on the output of the Schmitt trigger 1221. The LATCH_OUT_DELAYED signal is a delayed and inverted (by Schmitt trigger 1221) tversion of LATCH_OUT, with the amount of time delay being a function of the time constant formed by the combination of resistor R5 and capacitor C3. In one example, the amount of delay of between a rising edge of LATCH_OUT and the corresponding falling edge of LATCH_OUT_DELAY is 125 ns. Signal FF_BAR is provided to an input of NAND gate 1214, and functions to reset latch circuit 1209.
LATCH_OUT and LATCH_OUT_DELAYED are provided to inputs of an AND gate 1216. The output signal from AND gate 1216 is a clock signal (CLOCK) which is coupled to an input of a counter 1240 and to an input of an OR gate 1230. CLOCK is asserted high by AND gate 1216 when both LATCH_OUT and LATCH_OUT_DELAY are simultaneously high. The output signal of the counter 1240 (COUNTER_HIGH) is provided to an input of an inverter 1245, and the output signal from inverter 1245 is FF_DLY. The counter 1240 is configured to count a prescribed number of pulses of CLOCK (e.g., rising edges). In one implementation, the counter 1240 is configured to count 32 pulses of CLOCK in order for it to transition its output signal, COUNTER_HIGH, from a logic low state to a logic high state. When the counter 1240 reaches its terminal count, COUNTER_HIGH transitions to logic high and FF_DLY 425 transitions to logic low.
In addition to receiving the FF 415 signal through inverters 1233 and 1235 (FF 415 slightly delayed by the propagation delay of inverters 1233 and 1235), the OR gate 1218 also receives COUNTER_HIGH on another input. The output of OR gate 1218 is coupled to an input of OR gate 1230, the output of which is the DISCHARGE signal as noted above.
The delay control circuit 420 also includes an inverter 1232 and an AND gate 1234. COUNTER_HIGH is provided to the input of inverter 1232, the output of which is coupled to an input of AND gate 1234. The FF_BAR signal is provided to another input of AND gate 1234. The output of AND gate 1234 is coupled to enable (EN) input of comparator 1210. Driving the EN input of the comparator 1210 high enables the comparator and forcing the EN input low disables the comparator. When the counter 1240 reaches its terminal count, COUNTER_HIGH becomes logic high, which through inverter 1232, causes the output of AND gate 1234 to become logic low thereby disabling the comparator 1210. Accordingly, when the counter 1240 reaches its terminal count, DISCHARGE is asserted high through OR gate 1230 which causes V_CAP to be pulled low, and the comparator 1210 is disabled.
DISCHARGE is initially low which causes transistor M1200 to be off thereby permitting V_CAP to ramp up as shown at 1315. When V_CAP reaches the level of the bandgap reference voltage (V_BG), COMP_OUT becomes logic high as shown at 1320. Each pulse of COMP_OUT causes the latch circuit 1209 to generate a wider pulse 1324 for LATCH_OUT (the pulse width (PW) of which is a function of the RC time constant of resistor R5 and capacitor C3). LATCH_OUT_DELAY comprises a corresponding negative pulse 1325 delayed form the positive pulse 1324 of LATCH_OUT (delayed by PW).
When both LATCH_OUT and LATCH_OUT_DELAY are both simultaneously high, AND gate 1216 forces CLOCK high as shown at 1330. Once CLOCK becomes high, OR gate 1230 forces DISCHARGE high, which causes transistor M1200 to turn on thereby discharging capacitor C2 and, as shown at 1335, pulling V_CAP low. When a CLOCK pulse ends, DISCHARGE is again forced low, which turns off transistor M1200 and the process repeats.
Counter 1240 counts the preconfigured number of pulses (four in the example of
Upon the subsequent rising edge 1311 of FF 415, COUNTER_HIGH transitions from high to low as indicated by falling edge 1345. While FF 415 is high, FF_BAR is low as shown at 1316, Due to inverter 1245, FF_DLY has a falling edge (1360). Accordingly, upon FF 415 becoming high, there is little or no delay for the corresponding rising edge 1360 of FF_DLY 425.
The example voltage regulator of
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201941053150 | Dec 2019 | IN | national |
