RECURSIVE TYPE-IV DISCRETE COSINE TRANSFORM SYSTEM

Abstract

A recursive type-IV discrete cosine transform system includes a first permutation device, a recursive type-III discrete cosine/sine transform device, a cosine/sine factor generation device, a recursive type-II discrete cosine/sine transform device, a second permutation device. The first permutation device performs two-dimensional order permutation operation on N digital signals for generating N two-dimensional first temporal signals. The recursive type-III discrete cosine/sine transform device repeats a type-III discrete cosine/sine transform for generating second temporal signals. The cosine/sine factor generation device sequentially performs cosine/sine factor multiplication and corresponding addition operations for generating third temporal signals. The recursive type-II discrete cosine/sine transform device repeats a type-II discrete cosine/sine transform for generating fourth temporal signals. The second permutation device performs a one-dimensional order permutation operation for generating N one-dimensional output signals. The N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform on the N digital input signals.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefits of the Taiwan Patent Application Serial Number 101100102, filed on Jan. 2, 2012, the subject matter of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the technical field of digital signal processing and, more particularly, to a recursive type-IV discrete cosine transform (DCT) system.

2. Description of Related Art

With the development of digital signal processing technologies, various messages and media information can be conveniently obtained in daily living. A variety of modified discrete cosine transforms (MDCTs) and inverse modified discrete cosine transforms (IMDCTs) are widely used in various audio codec standards.

The audio codec standards include MP3, AAC, AC-3, TwinVQ, Ogg, for example. The MDCT and IMDCT operations in an audio codec occupy a very large portion of the entire operational complexity. If the MDCT/IMDCT is implemented with a same approach, sharing the hardware can be achieved on design for reducing the hardware requirement and the MDCT/IMDCT operational complexity.

For a high-efficiency Advanced Audio Coding (HE-AAC) audio codec, it uses high-quality spectral band replication (HQ-SBR) or low-power spectral band replication (LP-SBR) technologies in which complex-domain analysis quadrature mirror filter-banks (complex AQMFs) and synthesis quadrature mirror filter-banks (complex SQMFs) can be derived as the DCT of type III (DCT-III) and DCT-II kernel methods. Therefore, for implementing an aspect of AQMF and SQMF co-architecture in design, in addition to the MDCT and IMDCT computation, the operation of DCT-IV/DCT-III/DCT-II supports is accounted an essential key in hardware design.

However, the typical recursive architecture for IMDCT implementations has the disadvantages of having numerous operational periods and the overtime computation and being difficult to implement a co-architecture design for different operations such as the MDCT, AQMF at a decoder and the SQMF at an encoder. When the typical recursive architecture requires increasing the bit rate, only the hardware or the timing can be increased. However, the increased hardware indicates to increase the cost, and the increased timing indicates the high power consumption. In addition, for concurrently having the MDCT, AQMF, SQMF operational capabilities, it needs to design different hardware architectures for the operations, which also indicates the additional cost for hardware design.

Although the recursive discrete Fourier transforms (RDFTs) have developed for many years and thus advanced, it is still required for further reducing the operational complexity and hardware cost and increasing the data computational performance.

Therefore, it is desirable to provide an improved RDFT system to mitigate and/or obviate the aforementioned problems.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a recursive type-IV discrete cosine transform system, which has a low operational complexity, a low amount of used multiplication coefficients, and a high performance data computation.

According to a feature of the present invention, a recursive type-IV discrete cosine transform system is provided, which includes a first permutation device, a recursive type-III discrete cosine/sine transform device, a cosine/sine factor generation device, a recursive type-II discrete cosine/sine transform device, and a second permutation device. The first permutation device receives N digital input signals and performs a two-dimensional order permutation operation on the N digital signals for generating N two-dimensional first temporal signals, where N is a positive integer. The recursive type-III discrete cosine/sine transform device is an m-point recursive type-III discrete cosine/sine transform device connected to the first permutation device in order to receive the N first temporal signals and repeat a type-III discrete cosine/sine transform c times on the N first temporal signals for generating c second temporal signals each with m points, where N=m×c, and m, c are a positive integer. The cosine/sine factor generation device is connected to the recursive type-III discrete cosine/sine transform device in order to sequentially perform cosine/sine factor multiplication and corresponding addition operations on the m-point second temporal signals for generating c third temporal signals with m points. The recursive type-II discrete cosine/sine transform device is a c-point recursive type-II discrete cosine/sine transform device connected to the cosine/sine factor generation device in order to receive the third temporal signals and repeat a type-II discrete cosine/sine transform in times for generating m fourth temporal signals each with c points. The second permutation device is connected to the recursive type-II discrete cosine/sine transform device in order to receive the fourth temporal signals and perform a one-dimensional order permutation operation on the fourth temporal signals for generating N one-dimensional output signals, wherein the N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform on the N digital input signals.

According to another feature of the present invention, a recursive type-IV discrete cosine transform system is provided, which includes a first permutation device, a modified recursive type-III discrete cosine/sine transform device, a recursive type-II discrete cosine/sine transform device, and a second permutation device. The first permutation device receives N digital input signals and performs a two-dimensional order permutation operation on the N digital signals for generating N two-dimensional first temporal signals, where N is a positive integer. The modified recursive type-III discrete cosine/sine transform device is connected to the first permutation device and has a first and a second operational modes such that in the first operational mode a type-III discrete cosine/sine transform is repeated c times on the N first temporal signals for generating c second temporal signals each with m points, where N=m×c, and m, c are a positive integer. The recursive type-II discrete cosine/sine transform device is connected to the modified recursive type-III discrete cosine/sine transform device and has a first and a second operational modes such that in the first operational mode a third temporal signal is received and a type-II discrete cosine/sine transform is repeated m times on the third temporal signal for generating m fourth temporal signals each with c points. The second permutation device is connected to the recursive type-II discrete cosine/sine transform device in order to receive the fourth temporal signals and perform a one-dimensional order permutation operation on the fourth temporal signals for generating N one-dimensional output signals, wherein the N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform on the N digital input signals.

Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a recursive type-IV discrete cosine transform system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a DCT-IV (discrete cosine transform of type-IV) operation according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of input data mapping according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a relationship between indexes n₀, k₁ according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a relationship between an m-point DCT-III/DST-III and a c-point DCT-II/DST-II according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a pipelined DCT-IV according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of using additional adder and registers according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of using additional adder and registers according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a DCT-III/DST-III hardware architecture according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a hardware architecture corresponding to equation (56) according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of using additional adder and registers according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a DCT-II/DST-II hardware architecture according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a recursive type-IV discrete cosine transform system according to another embodiment of the present invention;

FIG. 14 is a schematic diagram of a cosine/sine factor generation device according the present invention;

FIG. 15 is a schematic diagram of a hardware action of inputting upper half data in a folding operation according to the present invention;

FIG. 16 is a schematic diagram of a hardware action of inputting lower half data in a folding operation according to the present invention;

FIGS. 17(A) and 17(B) are schematic diagrams of a complete intermediate-stage operation architecture according to the present invention;

FIG. 18 is a schematic diagram of operations corresponding to halt cycles according to the present invention;

FIG. 19 is a schematic diagram of a modified recursive type-III discrete cosine/sine transform device according to the present invention;

FIG. 20 is a schematic diagram of a recursive type-II discrete cosine/sine transform device according to the present invention;

FIG. 21 is a schematic diagram of using common multiplexers according to the present invention; and

FIGS. 22(A) and 22(B) are schematic diagrams of using common multipliers and adders according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a schematic diagram of a recursive type-IV discrete cosine transform system 100 according to an embodiment of the present invention. The system 100 includes a first permutation device 110, a recursive type-III discrete cosine/sine transform device 120, a cosine/sine factor generation device 130, a recursive type-II discrete cosine/sine transform device 140, and a second permutation device 150.

The first permutation device 110 receives N digital input signals and performs a two-dimensional order permutation operation on the N digital signals for generating N two-dimensional first temporal signals, where N is a positive integer.

The recursive type-III discrete cosine/sine transform device 120, which is an m-point recursive type-III discrete cosine/sine transform device, is connected to the first permutation device 110 in order to receive the N first temporal signals and repeat a type-III discrete cosine/sine transform c times on the N first temporal signals for generating c second temporal signals each with m points, where N===m×c, and m, c are each a positive integer.

The cosine/sine factor generation device 130 is connected to the recursive type-III discrete cosine/sine transform device 120 in order to sequentially perform cosine/sine factor multiplication and corresponding addition operations on the m-point second temporal signals for generating c third temporal signals with m points.

The recursive type-II discrete cosine/sine transform device 140, which is a c-point recursive type-II discrete cosine/sine transform device, is connected to the cosine/sine factor generation device 130 in order to receive the third temporal signals and repeat a type-II discrete cosine/sine transform m times for generating m fourth temporal signals each with c points.

The second permutation device 150 is connected to the recursive type-II discrete cosine/sine transform device 140 in order to receive the fourth temporal signals and perform a one-dimensional order permutation operation on the fourth temporal signals for generating N one-dimensional output signals, wherein the N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform (DCT-IV) on the N digital input signals.

For implementing a common architecture or co-architecture of analysis and synthesis filter-banks, the invention uses a DCT-IV kernel method to implement the modified DCT (MDCT) and inverse MDCT (IMDCT).

The MDCT and IMDCT math models are defined respectively in equation (1) and equation (2), where k ranges from zero to (N/2)−1, n ranges from zero to N−1, and M=N/2.

$\begin{array}{cc}{X}_c\left[k\right]=\sum _{n=0}^{N-1}x\left[n\right]\times \cos \left(\frac{\left(2n+1+M\right)\left(2k+1\right)\pi }{2N}\right),& \left(1\right)\\ {\hat{x}}_c\left[n\right]=\sum _{k=0}^{\frac{N}{2}-1}X_c\left[k\right]\times \cos \left(\frac{\left(2n+1+M\right)\left(2k+1\right)\pi }{2N}\right).& \left(2\right)\end{array}$

After an order permutation, the above equations are rewritten as equation (3) and equation (4):

$\begin{array}{cc}{X}_c\left[k\right]-\sum _{n=0}^{N/2-1}{\mathrm{Pre}}_c\left[n\right]\times \cos \left(\frac{\left(2n+1\right)\left(2k+1\right)\pi }{2N}\right),& \left(3\right)\\ {\mathrm{Post}}_c\left[n\right]=\sum _{k=0}^{N/2-1}X_c\left[k\right]\times \cos \left(\frac{\left(2n+1\right)\left(2k+1\right)\pi }{2N}\right),& \left(4\right)\\ \mathrm{where}& \\ {\mathrm{Pre}}_c\left[n\right]=-\left(x\left[n+\frac{3N}{4}\right]+x\left[\frac{3N}{4}-1-n\right]\right){}_{n=0\mathrm{to}N/4-1}& \\ {\mathrm{Pre}}_c\left[n\right]=\left(x\left[n-\frac{N}{4}\right]-x\left[\frac{3N}{4}-1-n\right]\right){}_{n=N/4\mathrm{to}N/2-1},& \left(5\right)\\ {\mathrm{Post}}_c\left[n\right]{}_{n=0\mathrm{to}N/4-1}=-{\hat{x}}_c\left[\frac{3N}{4}-1-n\right]=-{\hat{x}}_c\left[n+\frac{3N}{4}\right].& \left(6\right)\end{array}$

From equation (3) and equation (4), it is clearly known that the MDCT and IMDCT operation can be changed into a DCT-IV operation. In case of effectively sharing and reducing the DCT-IV operation, the computational complexity can be relatively reduced for the processes.

As compare with a parallel architecture, a recursive circuit has the advantages of small area, low power consumption, and flexible point number, but it also has the disadvantages of excess operational periods and overtime computation. For audio codec applications, such as long windows of Advanced Audio Coding (AAC; 2048 points), TwinVQ (4096 points), Ogg (up to 8192 points), the real-time computational requirement is difficult to be achieved due to the high point numbers.

Accordingly, the present invention applies a variable transform in a DCT-IV operation to thereby increase the speed of recursive architecture, and in this case an original one-dimensional computation equation is divided into two-dimensional operations to thereby shorten the cycle of a recursive operation.

An M-point DCT-IV math model is defined in equation (7) as follows.

$\begin{array}{cc}X\left[k\right]=\sum _{n=0}^{M-1}x\left[n\right]\times \cos \left(\frac{\left(2n+1\right)\left(2k+1\right)\pi }{4M}\right),& \left(7\right)\end{array}$

where M=n×k. Assume n=n₀+c×n₁ and k=m×k₀+k₁, and plug it in equation (7), so

$\begin{array}{cc}X\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}+\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}+\frac{\left(2n_0+1\right)k_0\pi }{2c}\right),X\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \left\{\cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}+\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)-\sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}+\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\right\}=X_c\left[m\times k_0+k_1\right]-X_c\left[m\times k_0+k_1\right],& \left(8\right)\\ \mathrm{where}& \\ X_c\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}\cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}+\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right),& \left(9\right)\\ \mathrm{and}& \\ X_s\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}\sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}+\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right).& \left(10\right)\end{array}$

Upon the trigonometric functions' sum identities, Equation (3) can be expanded as:

$\begin{array}{cc}{X}_c\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}\cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \left\{\cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)-\sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\right\}=\sum _{n_0=0}^{c-1}\cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)\{\left[\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\times \cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\right]-[\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\times \sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\}=X_{c0}\left[m\times k_0+k_1\right]-X_{c1}\left[m\times k_0+k_1\right],& \left(11\right)\\ \mathrm{where}& \\ X_{c3}\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\times \cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right),& \left(12\right)\\ \mathrm{and}& \\ X_{c1}\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\times \sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right).& \left(13\right)\end{array}$

Similarly, upon the trigonometric functions' sum identities, Equation (10) can be expended as:

$\begin{array}{cc}{X}_s\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}\sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \left\{\sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)+\cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\right\}=\sum _{n_0=0}^{c-1}\sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)\{\left[\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \cos (\frac{\left(2k_1+1\right)n_1\pi }{2m})\right]+[\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \hspace{1em}\cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)]\}=X_{s0}\left[m\times k_0+k_1\right]+X_{s1}\left[m\times k_0+k_1\right],& \left(14\right)\\ \mathrm{where}& \\ X_{s0}\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c1}\sum _{n_1=0}^{m1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\times \sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right),& \left(15\right)\\ \mathrm{and}& \\ X_{s1}\left[m\times k_0+k_1\right]=\sum _{n_0-0}^{c1}\sum _{n_1-0}^{m1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\times \cos \left(\frac{\left(2n_01\right)\left(2k_11\right)\pi }{4M}\right)\times \sin \left(\frac{\left(2n_01\right)k_0\pi }{2c}\right).& \left(16\right)\end{array}$

By considering a change of the index k₀, the kernel operation in equation (12), equation (13), equation (15), equation (16) is defined as:

$\begin{array}{cc}A\left(n_0,k_1,k_0\right)=\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),& \left(17\right)\\ B\left(n_0,k_1,k_0\right)=\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1k_0}\times x\left[n_0+c\times n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right).& \left(18\right)\end{array}$

If k₀ is an odd number,

$\begin{array}{cc}A\left(n_0,k_1,1\right)=\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1}\times x\left[n_0+c\times n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),& \left(19\right)\\ B\left(n_0,k_1,1\right)=\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1}\times x\left[n_0+c\times n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right).& \left(20\right)\end{array}$

If k₀ is an even number,

$\begin{array}{cc}A\left(n_0,k_1,0\right)=\sum _{n_1=0}^{m-1}x\left[n_0+c\times n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),& \left(21\right)\\ B\left(n_0,k_1,0\right)=\sum _{n_1=0}^{m-1}x\left[n_0+c\times n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right).& \left(22\right)\end{array}$

From equation (19) and equation (21), it is known that the change of k₀ only has two types of A(n₀, k₁, 1) and A(n₀, k₁, 0) with respect to A(n₀, k₁, k₀). Similarly, from equation (20) and equation (22), it is known that the change of k₀ only has two types of B(n₀, k₁, 1) and B(n₀, k₁, 0) with respect to B(n₀, k₁, k₀). Such a feature can relatively reduce the computational amount of Equation (17) and Equation (18).

Let k₁=m−1−k₁, and plug it in equation (19) to thereby derive the relation between equation (19) and equation (21), so as to have:

$\begin{array}{cc}\begin{array}{c}A\left(n_0,m-1-k_1,1\right)=\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1}\times x\left[n_0+c\times n_1\right]\times \\ \cos \left(n_1\pi \frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\\ =\sum _{n_1=0}^{m-1}{\left(-1\right)}^{2n_1}\times x\left[n_0+c\times n_1\right]\times \\ \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\\ =\sum _{n_1-0}^{m-1}x\left[n_0+c\times n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\\ =A\left(n_0,k_1,0\right).\end{array}& \left(23\right)\end{array}$

Similarly, let k₁=m−1−k₁, and plug it in Equation (20) to thereby derive the relation between Equation (20) and Equation (22), so

$\begin{array}{cc}\begin{array}{c}B\left(n_0,m-1-k_1,1\right)=\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_1}\times x\left[n_0+c\times n_1\right]\times \\ \sin \left(n_1\pi \frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\\ =\sum _{n_1=0}^{m-1}{\left(-1\right)}^{2n_1+1}\times x\left[n_0+c\times n_1\right]\times \\ \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\\ =-\sum _{n_1-0}^{m-1}x\left[n_0+c\times n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)\\ =-B\left(n_0,k_1,0\right).\end{array}& \left(24\right)\end{array}$

Accordingly, from equation (23) and equation (24), we have:

A(n₀,k₁,1)=A(n₀,m−1−k₁,0)  (25)

B(n₀,k₁,1)=−B(n₀,m−1−k₁,0).  (26)

By means of equation (25) and equation (26), the operations of equation (19) and equation (20) can be simplified.

By plugging the results in equation (12), equation (13), equation (15), equation (16), we have:

$\begin{array}{cc}{X}_{c0}\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}A\left(n_0,k_1,k_0\right)\times \cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right),& \left(27\right)\\ X_{c1}\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}B\left(n_0,k_1,k_0\right)\times \sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right),& \left(28\right)\\ X_{s0}\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}A\left(n_0,k_1,k_0\right)\times \sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right),& \left(29\right)\\ X_{s1}\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}B\left(n_0,k_1,k_0\right)\times \cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\times \sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right).& \left(30\right)\\ \mathrm{Since}& \\ \begin{array}{c}X\left[m\times k_0+k_1\right]=X_c\left[m\times k_0+k_1\right]-X_s\left[m\times k_0+k_1\right]\\ =\left(X_{c0}\left[m\times k_0+k_1\right]-X_{c1}\left[m\times k_0+k_1\right]\right)-\\ \left(X_{s0}\left[m\times k_0+k_1\right]+X_{s1}\left[m\times k_0+k_1\right]\right),\end{array}& \end{array}$

we have:

$\begin{array}{cc}{X}_c\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}T_c\left(n_0,k_1,k_0\right)\times \cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right),& \left(31\right)\\ \mathrm{and}& \\ T_c\left(n_0,k_1,k_0\right)-A\left(n_0,k_1,k_0\right)\times \cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)-B\left(n_0,k_1,k_0\right)\times \sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right).& \left(32\right)\\ \mathrm{while}& \\ X_s\left[m\times k_0+k_1\right]=\sum _{n_0=0}^{c-1}T_s\left(n_0,k_1,k_0\right)\times \sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right),& \left(33\right)\\ \mathrm{and}& \\ T_s\left(n_0,k_1,k_0\right)-A\left(n_0,k_1,k_0\right)\times \sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)+B\left(n_0,k_1,k_0\right)\times \cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right).& \left(34\right)\end{array}$

By summarizing the derivations, it is seen that the input signals pass through the DCT-II process of equation (21) and the DCT-III process of equation (22), then are multiplied by the respective cosine and sine factors in equation (32) and equation (34), and finally pass through the DCT-II process of equation (31) and the DCT-II process of equation (33). Thus, the faster DCT-IV operation is obtained.

Let n−0˜M−1, k=0˜M−1, M=m×c, n₀−0˜c−1, k₀=0˜c−1, n₁=0˜m−1, and k₁=U˜m−1, the complete M-point DCT-IV method can be written into the steps as follows.

1. The input signals are based on n=n₀+c×n₁ to be arranged as a two-dimensional order permutation.

2. The arranged data (the permutation) is input to an m-point DCT-III/DST-III hardware.

3. The resultant transformed by the m-point DCT-III/DST-II hardware is operated with the cosine and sine factors.

4. The resultant after the operation is input to a c-point DCT-III/DST-III hardware.

5. The results transformed by the c-point DCT-III and DST-III hardware are subtracted and permuted based on k=m×k₀+k₁.

Steps (1) and (5), which are regarded as pre- and post-processing, essentially perform the permutation, addition, and subtraction operations, and steps (2)-(4) are the operations of the kernel hardware architecture. The steps above are shown in FIG. 2 in which is a schematic diagram of a DCT-IV (discrete cosine transform of type-IV) operation according to an embodiment of the embodiment. In addition, in FIG. 2, it is easy to see that step (2) requires repeating the m-point DCT-III/DST-III c times. In this case, c DCT-III/DST-III circuits are required in case of only using the hardware in implementation. Such an implementation requires more hardware sources and is difficult to adjust the hardware resources for different points. Therefore, for supporting multiple audio standards with different points, the invention uses a DCT-III/DST-III hardware to repeat the operation c times, and for different points, only the number of operations is adjusted. Similarly, step (4) requires repeating the c-point DCT-II/DST-II operation m times, and it is implemented by repeating the operation m times on a DCT-II/DST-II hardware.

As cited above, the invention divides the M-point DCT-IV operation into an m-point DCT-III/DST-III operation and a c-point DCT-II/DST-II operation. In viewing FIG. 2, it is seen that the result of the m-point DCT-III/DST-III operation is operated with the cosine and sine factors to thereby become an input data for the c-point DCT-II/DST-II operation. Therefore, the complete architecture can be generally divided into three stages, the first stage indicating the m-point DCT-III/DST-III operation, the immediate stage indicating the cosine and sine factor operation, and the second stage indicating the c-point DCT-II/DST-II operation. Thus, the invention can arrange a sequence of data operations for allowing each stage to independently perform and increasing the performance in a pipelined form.

At first, the input data of the sequence is arranged into a two-dimensional order permutation based on n=n₀+c×n₁, as shown in FIG. 3 in which is a schematic diagram of input data mapping according to an embodiment of the embodiment. Next, the computational order firstly sets k₁, n_o to a respective initial value, then adds n_o by one after an m-time recursion, and finally repeats the addition until n_o=c−1, which indicates that the c m-point DCT-III/DST-III operations are complete. Next, the c results can be delivered to a next-stage for performing c-point DCT-II/DST-II operations, adding k₁ by one, and setting n_o, to zero, as shown in FIG. 4 in which is a schematic diagram of the relationship between the indexes n₀, k₁ according to an embodiment of the embodiment. As cited above, it is known that such an operation can make the data streams independent, so the pipeline can work completely, as shown in FIG. 5 in which is a schematic diagram of the relationship between the m-point DCT-II/DST-III and the c-point DCT-II/DST-II operations according to an embodiment of the embodiment.

The duration required for a pipeline depends on which stage of circuit requires the highest time in operation. In practice, the operating speed of the first stage has to be smaller than or equal to that of the second stage, i.e., m≧c. In addition, when m=c, the pipeline can achieve the optimal efficiency. FIG. 6 is a schematic diagram of a pipelined DCT-IV according to an embodiment of the present invention.

With the pipelined scheme, the number of cycles is improved by c times as compared with the conventional method. However, a certain number of registers are relatively increased for an exchange. Since the data transfer between the stages requires the registers for storing, the number of registers required for the architecture is determined by c. Namely, the number of registers is increased with increasing the multiple of speeding.

Upon FIG. 2, the DCT-II/DST-III hardware architecture is designed. The design is focused on how to provide a recursive DCT-III/DST-III hardware architecture with a low operational period to thereby improve the slow-speed recursive architecture in the prior art. In addition, on the hardware design, the sharing scheme is expected, which can allow the designed hardware to concurrently have the DCT-III and DST-III operational capabilities to thereby reduce the hardware cost.

Equation (35) and Equation (36) are defined as m-point DCT-III and DST-III math models respectively. For input signals y[n₁] and z[n] and output signals Y_DCT-III[k₁] and Z_DCT-III[k₁], n₁=0˜m−1, k₁=0˜m−1,

$\begin{array}{cc}{Y}_{\mathrm{DCT}-\mathrm{III}}\left[k_1\right]=\sum _{n_1=0}^{m-1}y\left[n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),& \left(35\right)\\ Z_{\mathrm{DST}-\mathrm{III}}\left[k_1\right]=\sum _{n_2=0}^{m-1}z\left[n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right).& \left(36\right)\end{array}$

For different applications, the m-point number can be odd or even, which is separately discussed as follows.

(A) m is an Odd Number

If m is an odd number, Equation (35) is rewritten as Equation (37), Equation (38), and Equation (39):

$\begin{array}{cc}{Y}_{\mathrm{DCT}-\mathrm{III}}\left[k_1\right]=\sum _{n_2=0}^{m-1}y\left[n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-3\right)/2,& \left(37\right)\\ Y_{\mathrm{DCT}-\mathrm{III}}\left[m-1-k_1\right]=\sum _{n_1=0}^{m-1}{\left(-1\right)}^{n_2}\times y\left[n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-3\right)/2,& \left(38\right)\\ Y_{\mathrm{DCT}-\mathrm{III}}\left[\left(m-1\right)/2\right]=y\left[0\right]-y\left[2\right]+y\left[4\right]-y\left[6\right]+,\dots ,-y\left[m-1\right].& \left(39\right)\end{array}$

From equation (37), equation (38), and equation (39), it is known that the data throughput per transformation (DTPT) in equation (35) is doubled, so that only m×(m−1)/2 cycles are required for completing the m-point DCT-III computation, but the operation in equation (39) requires using additional adders and registers, as shown in FIG. 7 in which is a schematic diagram of using the additional adder and registers according to an embodiment of the embodiment. In this case, when the operation in equation (39) is implemented with a common hardware, as shown in FIG. 9 in which is a schematic diagram of the DCT-III/DST-III hardware architecture according to an embodiment of the present invention, the computational period to be required for DCT-III includes m×(m+1)/2 cycles.

Similarly, equation (36) can be rewritten as equation (40), equation (41), and equation (42).

$\begin{array}{cc}{z}_{\mathrm{DST}-\mathrm{III}}\left[k_1\right]=\sum _{n_1=0}^{m-1}z\left[n_1\right]\times \sin \left(\frac{\left(2k+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-3\right)/2,& \left(40\right)\\ Z_{\mathrm{DST}-\mathrm{III}}\left[m-1-k_1\right]=\sum _{n_1=0}^{m-1}{\left(-1\right)}^{N_2\stackrel{)}{–}1}\times z\left[n_1\right]\times \sin \left(\frac{\left(2k+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-3\right)/2,& \left(41\right)\\ Z_{\mathrm{DST}-\mathrm{III}}\left[\left(m-1\right)/2\right]=z\left[1\right]-y\left[3\right]+y\left[5\right]-y\left[7\right]+,\dots ,+y\left[m-2\right].& \left(42\right)\end{array}$

From equation (40), equation (41), and equation (42), it is known that the DTPT in equation (36) is doubled, so only m×(m−1)/2 cycles are required for completing the m-point DCT-III computation, but the operation in equation (42) requires using additional adders and registers, as shown in FIG. 8 in which is a schematic diagram of using the additional adder and registers according to an embodiment of the embodiment. In this case, when the operation in equation (42) is implemented with a common hardware, as shown in FIG. 9, the computational period to be required for DCT-III includes m×(m+1)/2 cycles.

Next, for allowing DST-III and DCT-III to share the cosine coefficients, Equation (43) is derived from Equation (40), and Equation (44) is derived from Equation (41).

$\begin{array}{cc}{Z}_{\mathrm{DST}-\mathrm{III}}\left[k_1\right]={\left(-1\right)}^{R_s}\times \sum _{n_2=0}^{m-1}z\left[m-n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-3\right)/2.& \left(43\right)\\ Z_{\mathrm{DST}-\mathrm{III}}\left[m-1-k_1\right]={\left(-1\right)}^{k_2}\times \sum _{n_2-0}^{m-1}{\left(-1\right)}^{m-n_2+1}\times z\left[m-n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-3\right)/2.& \left(44\right)\end{array}$

From Equation (43) and Equation (44), it is known that the cosine coefficients for DCT-II can be shared by simply ordering the input signals for DST-III and adjusting the positive and negative signs to thereby produce the operational result for DST-III and save the hardware cost.

(B) m is an Even Number:

If m is an even number, equation (35) can be rewritten as equation (45) and equation (46):

$\begin{array}{cc}{Y}_{\mathrm{DCT}-\mathrm{III}}\left[k_1\right]=\sum _{n_2=0}^{m-1}y\left[n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-1\right)/2.& \left(45\right)\\ Y_{\mathrm{DCT}-\mathrm{III}}\left[m-1-k_1\right]=\sum _{n_2=0}^{m-1}{\left(-1\right)}^{n_2}\times y\left[n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-1\right)/2.& \left(46\right)\end{array}$

From equation (45) and equation (46), it is known that the DTPT in equation (35) is doubled, so only m²/2 cycles are required for completing the m-point DST-III computation.

Similarly, equation (36) can be rewritten as equation (47) and equation (48):

$\begin{array}{cc}{Z}_{\mathrm{DST}-\mathrm{III}}\left[k_1\right]=\sum _{n_1=0}^{m-1}z\left[n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-1\right)/2.& \left(47\right)\\ Z_{\mathrm{DST}-\mathrm{III}}\left[m-1-k_1\right]=\sum _{n_2=0}^{m-1}{\left(-1\right)}^{n_2+1}\times z\left[n_1\right]\times \sin \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-1\right)/2.& \left(48\right)\end{array}$

Next, for allowing DST-III and DCT-III to share the cosine coefficients, equation (49) is derived from equation (47), and equation (50) is derived from equation (48):

$\begin{array}{cc}{Z}_{\mathrm{DST}-\mathrm{III}}\left[k_1\right]={\left(-1\right)}^{k_2}\times \sum _{n_1-0}^{m-1}z\left[m-n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)\left(m-n_1\right)\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-1\right)/2.& \left(49\right)\\ Z_{\mathrm{DST}-\mathrm{III}}\left[m-1-k_1\right]={\left(-1\right)}^{k_2}\times \sum _{n_1=0}^{m-1}{\left(-1\right)}^{(m-n_2+1}\times z\left[m-n_1\right]\times \cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right),\mathrm{for}k_1=0~\left(m-1\right)/2.& \left(50\right)\end{array}$

From equation (49) and equation (50), it is known that the cosine coefficients for DCT-III can be shared by simply ordering the input signals for DST-III and adjusting the positive and negative signs to thereby produce the operational result for DST-III and save the hardware cost.

Finally, upon equation (51) and equation (52), the Chebyshev polynomials are:

cos(n₁θ_k2)=2 cos(θ_k1)cos((n₁−1)θ_k1)−cos((n₁−2)θ_k2),  (51)

sin(n₁θ_k1)=2 cos(θ_k2)sin((n₁−1)θ_k2)−sin((n₁−2)θ_k1),  (52)

where

${\theta }_{k_1}=\frac{\left(2k_1+1\right)\pi }{2m}.$

Expanding the Chebyshev polynomials, we have:

$\begin{array}{cc}\cos \left(\frac{\left(2k_1+1\right)n_1\pi }{2m}\right)=2\times \cos \left(\frac{\left(2k_1+1\right)\pi }{2m}\right)\cos \left(\frac{\left(2k_1+1\right)\left(n_1-1\right)\pi }{2m}\right)-\cos \left(\frac{\left(2k_1+1\right)\left(n_1-2\right)\pi }{2m}\right).& \left(53\right)\end{array}$

The initial values, cos((2k₁+1)π/2m), 1, cos((2k₁+1)(−1)π/2m), respectively for three cosine functions at the right side of the equality in equation (53) in the invention can be obtained by plugging n₁=1.

Since cos((2k₁+1)(−1)π/2m)=cos((2k₁+1)π/2m), the cosine coefficients with a same k1 and different n1 can be generated by the recursive operation in equation (53), with accessing cos((2k₁+1)π/2m) and the memory requirement of m words only.

Next, plugging equation (53) in equation (37), equation (38), equation (43), equation (44), equation (45), equation (46), the method with the low operation cycle and DCT-III/DST-III operational capabilities is obtained. In addition, the operations in equation (39) and equation (50) require addition only, which can be implemented by the common adders with other operations. In this case, the hardware architecture is designed as that shown in FIG. 9.

In FIG. 9, y[n₁] indicates the input signal Input1, and z[n₁] indicates the input signal Input2.

When m is an odd number, the output signal Output1 corresponds to the result operated in equation (37) or equation (39), the output signal Output2 corresponds to the result operated in equation (38), the output signal Output3 corresponds to the result operated in equation (44), and the output signal Output4 corresponds to the result operated in equation (43) or equation (42).

When m is an even number, the output signal Output1 corresponds to the result operated in equation (45), the output signal Output2 corresponds to the result operated in equation (46), the output signal Output3 corresponds to the result operated in equation (48), and the output signal Output4 corresponds to the result operated in equation (47). The parameters corresponding to the output signals in FIG. 9 are shown in Table 5.3.1 as follows.

TABLE 5.3.1
DCT-III/DST-III hardware and method relative table
Hardware I/O Corresponding Parameters
Input1       x(n0, n1)
Input2       x(n0, m − n1)
Output1      A(n0, k1, 0), A(n0, m − 1 − k1, 1)
Output2      A(n0, m − 1 − k1, 0), A(n0, k1, 1)
Output3      B(n0, m − 1 − k1, 0), −B(n0, k1, 1)
Output4      B(n0, k1, 0), −B(n0, m − 1 − k1, 1)
P.S.: n0 = 0~c − 1, n1 = 0~m − 1, k1 = 0~(m + 1)/2 when m is an odd number, and k1 − 0~m/2 when m is an even number.

As cited above, the recursive type-III discrete cosine/sine transform device 120 is implemented by sharing the hardware, and the computational period includes m×(m+1)/2 cycles.

As shown in FIG. 9, the recursive type-II discrete cosine/sine transform device 120 includes first to sixth registers 901-906, first to fifth adders 931-935, a first 3-to-1 multiplexer 951, a second 3-to-1 multiplexer 952, a first multiplier 971, a second multiplier 972, and a fourth multiplier 974.

Upon FIG. 2, the DCT-II/DST-II hardware architecture is designed. The design is focused on how to provide a recursive DCT-II/DST-II hardware architecture with a low operational period to thereby improve the slow-speed recursive architecture in the prior art. In addition, on the hardware design, the sharing scheme is expected, which can allow the designed hardware to concurrently have the DCT-II and DST-II operational capabilities to thereby reduce the hardware cost.

Equation (54) and Equation (55) are defined as m-point DCT-II and DST-II math models respectively. For input signals p[n₀] and q[n₀] and output signals P_DCT-II[k₀] and Q_DCT-II[k₀], where n₀=0˜c−1, k₀=0˜c−1,

$\begin{array}{cc}{P}_{\mathrm{DCT}-\mathrm{II}}\left[k_0\right]=\sum _{n_0=0}^{c-1}p\left[n_0\right]\times \cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right).& \left(54\right)\\ Q_{\mathrm{DST}-\mathrm{II}}\left[k_0\right]-\sum _{n_0=0}^{c-1}q\left[n_0\right]\times \sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right).& \left(55\right)\end{array}$

For different applications, the c-point number can be odd or even, which is separately discussed as follows.

(A) c is an Odd Number

If c is an odd number, Equation (54) can be rewritten as Equation (56), Equation (57):

$\begin{array}{cc}{P}_{\mathrm{DCT}-\mathrm{II}}\left[0\right]=p^{\left(1\right)}\left[0\right]+p^{\left(1\right)}\left[1\right]+,\dots ,+p^{\left(1\right)}\left[\left(c-1\right)/2-1\right]+p\left[\frac{c-1}{2}\right],& \left(56\right)\\ P_{\mathrm{DCT}-\mathrm{II}}\left[k_0\right]=\sum _{n_0=0}^{\left(c-1\right)/2-1}p^{\left(1\right)}\left[n_0\right]\times \cos \left(\frac{\left(2n_0+1\right)k\pi }{2c}\right)+\mathrm{tmp}0\times p\left[\frac{c-1}{2}\right],& \left(57\right)\\ \mathrm{where}p^{\left(1\right)}\left[n_0\right]-p\left[n_0\right]+{\left(-1\right)}^{k_0}p\left[c-1-n_0\right],\mathrm{and}\mathrm{tmp}0=\{\begin{array}{cc}1,& \mathrm{mod}\left(k_0,4\right)=0\\ -1,& \mathrm{mod}\left(k_0,4\right)=2\\ 0,& \mathrm{mod}\left(k_0,4\right)=1\mathrm{or}3.\end{array}& \left(58\right)\end{array}$

From equation (56), equation (57), it is known that the input data p[n₀] in equation (54) is operated with equation (58) to produce p⁽¹⁾[n₀], which has a half of data amount than the original, so the computational period required for DCT-II includes (c−1)/2×c cycles only, but the operation in equation (56) requires using additional adders and registers, as shown in FIG. 10 in which is a schematic diagram of the hardware architecture corresponding to equation (56) according to an embodiment of the embodiment. In this case, when the operation in equation (56) is implemented with a common hardware, as shown in FIG. 12 in which is a schematic diagram of the DCT-II/DST-II hardware architecture according to an embodiment of the embodiment, the computational period to be required for DCT-II includes (c+1)/2×c cycles.

Similarly equation (55) can be rewritten as equation (59), equation (60), and equation (61) as follows:

$\begin{array}{cc}Q_{\mathrm{DST}-\mathrm{II}}\left[0\right]=0,& \left(59\right)\\ Q_{\mathrm{DST}-\mathrm{II}}\left[k_0\right]=\sum _{n_0=0}^{\left(c-1\right)/2-1}q^{\left(1\right)}\left[n_0\right]\times \sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)+\mathrm{tmp}1\times q\left[\frac{c-1}{2}\right],& \left(60\right)\\ \mathrm{where}q^{\left(1\right)}\left[n_0\right]=q\left[n_0\right]+{\left(-1\right)}^{k_0+1}q\left[c-1-n_0\right],\mathrm{and}\mathrm{tmp}1=\{\begin{array}{cc}1,& \mathrm{mod}\left(k_0,4\right)=1\\ -1,& \mathrm{mod}\left(k_0,4\right)=3\\ 0,& \mathrm{mod}\left(k_0,4\right)=0\mathrm{or}2.\end{array}& \left(61\right)\end{array}$

From equation (59), equation (60), it is known that the input data q[n₀] in equation (55) is operated with equation (61) to thereby produce q⁽¹⁾[n₀], which has a half of data amount than the original, so the computational period required for DST-II includes (c−1)/2×c cycles only.

Next, the cosine function is derived from the sine function in the DST-II method, so the cosine coefficients in the DCT-II method can be shared in the hardware implementation as follows.

$\begin{array}{cc}{Q}_{\mathrm{DST}-\mathrm{II}}\left[c-k_0\right]=\sum _{n_0=0}^{\left(c-1\right)/2-1}{\left(-1\right)}^{n_0}\times q^{\left(2\right)}\left[n_0\right]\times \cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)+\mathrm{tmp}1\times q\left[\frac{c-1}{2}\right],& \left(62\right)\\ \mathrm{where}q^{\left(2\right)}\left[n_0\right]=q\left[n_0\right]+{\left(-1\right)}^{c-k_0+1}q\left[c-1-n_0\right].& \left(63\right)\end{array}$

From equation (62), equation (53), it is known that the cosine coefficients for DCT-II can be shared by simply ordering the output signals and adjusting the positive and negative signs of the input signals for DST-II, to thereby produce the operational result for DST-II and save the hardware cost.

(B) c is an Even Number

If c is an even number, equation (54) can be rewritten as equation (64), equation (65) as follows.

$\begin{array}{cc}{P}_{\mathrm{DCT}-\mathrm{II}}\left[0\right]=p^{\left(1\right)}\left[0\right]+p^{\left(1\right)}\left[1\right]+,\dots ,+p^{\left(1\right)}\left[c/2-1\right],& \left(64\right)\\ P_{\mathrm{DCT}-\mathrm{II}}\left[k_0\right]=\sum _{n_0=0}^{c/2-1}p^{\left(1\right)}\left[n_0\right]\times \cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right).& \left(65\right)\end{array}$

From Equation (64), Equation (65), it is known that the input data p[n₀] in Equation (54) is operated with Equation (58) to produce p⁽¹⁾[n], which has a half of data amount than the original, so the computational period required for DCT-II includes c/2×(c−1) cycles only, but the operation in Equation (56) requires using additional adders and registers, as shown in FIG. 11 in which is a schematic diagram of using additional adder and registers according to an embodiment of the embodiment. In this case, when the operation in Equation (56) is implemented with a common hardware, as shown in FIG. 12, the computational period to be required for DCT-II includes c²/2 cycles.

Similarly, Equation (55) can be rewritten as Equation (66), Equation (67) as follows:

$\begin{array}{cc}{Q}_{\mathrm{DST}-\mathrm{II}}\left[0\right]=0.& \left(66\right)\\ Q_{\mathrm{DST}-\mathrm{II}}\left[k_0\right]=\sum _{n_0=0}^{c/2-1}q^{\left(1\right)}\left[n_0\right]\times \sin \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right).& \left(67\right)\end{array}$

Next, the cosine function can be derived from the sine function in the DST-II method, so the cosine coefficients in the DCT-II method can be shared in the hardware implementation as follows:

$\begin{array}{cc}{Q}_{\mathrm{DST}-\mathrm{II}}\left[c-k_0\right]=\sum _{n_0=0}^{c/2-1}{\left(-1\right)}^{n_0}\times q^{\left(2\right)}\left[n_0\right]\times \cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right).& \left(68\right)\end{array}$

From equation (66), it is known that the cosine coefficients for DCT-II can be shared by simply ordering the output signals and adjusting the positive and negative signs of the input signals for DST-II to thereby produce the operational result for DST-II and save the hardware cost.

Finally, upon the Chebyshev polynomials, the following equations can be obtained:

$\begin{array}{cc}\cos \left(\frac{\left(2n_0+1\right)k_0\pi }{2c}\right)=2\times \cos \left(\frac{k_0\pi }{c}\right)\cos \left(\frac{\left(2n_0-1\right)k_0\pi }{2c}\right)-\cos \left(\frac{\left(2n_0-3\right)k_0\pi }{2c}\right).& \left(69\right)\end{array}$

The initial values, cos(k₀π/c), cos(k₀π/2c), cos(k₀(−1)π/2c) respectively for three cosine functions at the right side of the equality in Equation (69) in the invention can be obtained by plugging n₀=1. Since cos(k_n(−1)π/2c)=cos(k₀π2c), the cosine coefficients with a same k1 and different n1 can be generated by the recursive operation in Equation (69), with accessing cos(k₀π/c) and cos(k₀π/2c), and the memory requirement of 2c words only.

Plugging equation (69) in equation (57), equation (62), equation (65), equation (68), the method with the low operation cycle and DCT-III/DST-III operational capabilities is obtained. In this case, the derived method requires a hardware architecture designed as that shown in FIG. 12.

In FIG. 12, p⁽¹⁾[n₀] indicates the input signals Input1 and Input2, and q⁽¹⁾[n₀] indicates the input signals Input3 and Input4. When c is an odd number, the output signals Output1 and Output2 correspond to the result operated in equation (57) or equation (56), the output signals Output3 and Output4 correspond to the result operated in equation (62).

When c is an even number, the output signals Output1 and Output2 correspond to the result operated in equation (64) and equation (65), the output signals Output3 and Output4 correspond to the result operated in equation (68). The parameters corresponding to the output signals in FIG. 12 are shown in Table 5.4.1 as follows.

TABLE 5.4.1
DCT-II/DST-II hardware and method relative table
Hardware I/O Corresponding Parameters
Input1       Data after Tc(n0, k1, k0) operates in equation (39)
Input2       Data, after Tc(n0, m − k1 − 1, k0) operates in
             equation(39)
Input3       Data after T (n0, k1, k0) operates in equation (44)
Input4       Data after Ts(n0, m − k1 − 1, k0) operates in
             equation(44)
Output1      Xc(k0, k1)
Output2      X (k0, m − 1 − k1)
Output3      Xs(c − k0, k1)
Output4      X (  − k0, m − 1 − k1)
P.S.; kQ = 0~c − 1, k1 = 0~(m + 1)/2 when m is an odd number, k1 =  ~m/2 when m is an even number.
indicates data missing or illegible when filed

As cited above and shown in FIG. 12, it is known that the recursive type-II discrete cosine/sine transform device 140 can be implemented in a common hardware, and the computational period includes c×(c+1)/2 cycles, the recursive type-II discrete cosine/sine transform device 140 includes seventh to twelfth registers 1217-1222, sixth to tenth adders 1236-1240, a third 3-to-1 multiplexer 1253, a fourth 3-to-1 multiplexer 1254, a third multiplier 1273, a fifth multiplier 1275, a sixth multiplier 1276, a seventh multiplier 1277, and an eighth multiplier 1278.

As cited above, an M-point DCT-V operation in the invention is divided into an m-point DCT-III/DST-III operation and a c-point DCT-II/DST-II operation. Namely, the input signals pass through the first stage of DCT-III/DST-III and sequentially the second stage of DCT-II/DST-II. However, the operation in the immediate stage of cosine and sine factors is required before the signals input to the second stage. The hardware architectures respectively for the first and the second stages are aforementioned, and the operation in the immediate stage of cosine and sine factors and corresponding hardware design are described in detail as follows.

FIG. 13 is a schematic diagram of the recursive type-IV discrete cosine transform system 1300 according to another embodiment of the embodiment. In FIG. 13, the system 1300 includes a first permutation device 1310, a modified recursive type-III discrete cosine/sine transform device 1320, a recursive type-II discrete cosine/sine transform device 1330, and a second permutation device 1340. The system 130 merges the immediate cosine and sine factor operations to the modified recursive type-III discrete cosine/sine transform device 1320.

The first permutation device 1310 receives N digital input signals and performs a two-dimensional order permutation operation on the N digital signals for generating N two-dimensional first temporal signals, where N is a positive integer.

The modified recursive type-III discrete cosine/sine transform device 1320 is connected to the first permutation device 1310 and has a first and a second operational modes such that in the first operational mode a type-II discrete cosine/sine transform is repeated c times on the N first temporal signals for generating c second temporal signals each with m points, where N=m×c, and m, c are a positive integer.

The recursive type-II discrete cosine/sine transform device 1330 is connected to the modified recursive type-III discrete cosine/sine transform device 1320 and has a first and a second operational modes such that in the first operational mode a third temporal signal is received and a type-II discrete cosine/sine transform is repeated m times on the third temporal signal for generating m fourth temporal signals each with c points.

The second permutation device 1340 is connected to the recursive type-II discrete cosine/sine transform device 1330 in order to receive the fourth temporal signals and perform a one-dimensional order permutation operation on the fourth temporal signals for generating N one-dimensional output signals, wherein the N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform on the N digital input signals.

From equation (32) and equation (34), it is known that the result of the first stage of DCT-II and DST-III operations is multiplied by the cosine and sine factors defined as follows:

Cosine Factor:

$\begin{array}{cc}\cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right).& \left(70\right)\end{array}$

Sine Factor:

$\begin{array}{cc}\sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right).& \left(71\right)\end{array}$

From equation (70) and equation (71), it is seen that, with n₀=0˜c 1, k₁=0˜m−1, and M=m×c, the M-point DCT-IV requires M cosine factors and M sine factors, i.e., the memory capacity of 2M words is required for accessing the cosine and sine factors. To reduce a size of memory, the cosine and sine factor generation device, i.e., a cosine and sine coefficient generator, is designed in the invention.

First, since the first stage of hardware architecture generates two DCT-II and two DST-III operational results every in cycles, as shown in Table 5.3.1. Thus, the results (data) are multiplied by the corresponding cosine and sine factors defined in equation (72), such that the immediate stage of operations is complete as the four factors are concurrently generated.

$\begin{array}{cc}\{\begin{array}{c}\cos \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\\ \sin \left(\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M}\right)\\ \cos \left(\frac{\left(2n_0+1\right)\left(2\left(m-k_1-1\right)+1\right)\pi }{4M}\right)\\ \sin \left(\frac{\left(2n_0+1\right)\left(2\left(m-k_1-1\right)+1\right)\pi }{4M}\right)\end{array}\mathrm{for}n_0=0~c-1\mathrm{if}m\mathrm{is}\mathrm{even},\mathrm{for}k_1=0~m/2\mathrm{if}m\mathrm{is}\mathrm{odd},\mathrm{for}k_1=0~\left(m+1\right)/2.& \left(72\right)\end{array}$

It is known in FIG. 2 that the output order of the first stage of output data first sets the index k₁=0 and changes the index n₀ from zero to c−1, then sets k₁=1 and changes n₀ from zero to c−1, and finally repeats to set k₁ to a fixed value and change n₀ from zero to c−1 until k₁=m−1, which indicates the first stage of output data is completely output. Upon such an architecture, DTPT=2, and the data corresponding to the indexes k₁ and m−1−k₁ can be concurrently generated, so the cosine and sine factor generation device in the invention can output the coefficients meeting with the output order of the first stage of output data.

For a more clear derivation, some parameters in the invention are defined as:

${\theta }_f=\frac{\left(2k_1+1\right)\pi }{4M},{\theta }_b=\frac{\left(2\left(m-k_1-1\right)+1\right)\pi }{4M}.$

Upon the trigonometric functions' sum identities:

$\hspace{1em}\{\begin{array}{c}\cos \left(\alpha +\beta \right)=\cos \alpha \times \cos \beta -\sin \alpha \times \sin \beta \\ \sin \left(\alpha +\beta \right)=\sin \alpha \times \cos \beta +\cos \alpha \times \sin \beta ,\end{array}$

equation (72) can be derived to the recursion as follows:

$\begin{array}{cc}\{\begin{array}{c}\cos \left(\left(2n_0+1\right){\theta }_f\right)=\cos \left(\left(2n_0-1\right){\theta }_f\right)\times \cos \left(2{\theta }_f\right)-\sin \left(\left(2n_0-1\right){\theta }_f\right)\times \sin \left(2{\theta }_f\right)\\ \sin \left(\left(2n_0+1\right){\theta }_f\right)=\sin \left(\left(2n_0-1\right){\theta }_f\right)\times \cos \left(2{\theta }_f\right)+\cos \left(\left(2n_0-1\right){\theta }_f\right)\times \sin \left(2{\theta }_f\right)\\ \cos \left(\left(2n_0+1\right){\theta }_b\right)=\cos \left(\left(2n_0-1\right){\theta }_b\right)\times \cos \left(2{\theta }_b\right)-\sin \left(\left(2n_0-1\right){\theta }_b\right)\times \sin \left(2{\theta }_b\right)\\ \sin \left(\left(2n_0+1\right){\theta }_b\right)=\sin \left(\left(2n_0-1\right){\theta }_b\right)\times \cos \left(2{\theta }_b\right)+\cos \left(\left(2n_0-1\right){\theta }_b\right)\times \sin \left(2{\theta }_b\right).\end{array}& \left(73\right)\end{array}$

From the recursion above, it is easy to discover that the initial values cos(θ_f), sin(θ_f), cos(θ_b), sin(θ_b) and cos(2θ_f), sin(2θ_f), cos(2θ_b), sin(2θ_b) are required for completing the operation. The number of initial values can influence the ROM size, i.e., the more the number of initial values is, the more the number of words required for ROM. For reducing the number of initial values, the recursion is derived as follows:

$\begin{array}{cc}\{\begin{array}{c}\cos \left(2{\theta }_f\right)=\cos \left({\theta }_f\right)\times \cos \left({\theta }_f\right)-\sin \left({\theta }_f\right)\times \sin \left({\theta }_f\right)\\ \sin \left(2{\theta }_f\right)=\sin \left({\theta }_f\right)\times \cos \left({\theta }_f\right)+\cos \left({\theta }_f\right)\times \sin \left({\theta }_f\right)\\ \cos \left(2{\theta }_b\right)=\cos \left({\theta }_b\right)\times \cos \left({\theta }_b\right)-\sin \left({\theta }_b\right)\times \sin \left({\theta }_b\right)\\ \sin \left(2{\theta }_b\right)=\sin \left({\theta }_b\right)\times \cos \left({\theta }_b\right)+\cos \left({\theta }_b\right)\times \sin \left({\theta }_b\right).\end{array}& \left(74\right)\end{array}$

where only the initial values cos(θ_f), sin(θ_f), cos(θ_b), sin(θ_b) are used to generate a same k₁ and different n_o for the cosine and sine factors since cos(2θ_f), sin(2θ_f), cos(2θ_b), sin(2θ_b) can be calculated in equation (74). Therefore, the recursive relations are:

$n_0=0\text{:}\{\begin{array}{c}\cos \left({\theta }_f\right)\\ \sin \left({\theta }_f\right)\\ \cos \left({\theta }_b\right)\\ \sin \left({\theta }_b\right)\end{array},n_0=1\text{:}\{\begin{array}{c}\cos \left(3{\theta }_f\right)=\cos \left({\theta }_f\right)\times \cos \left(2{\theta }_f\right)-\sin \left({\theta }_f\right)\times \sin \left(2{\theta }_f\right)\\ \sin \left(3{\theta }_f\right)=\sin \left({\theta }_f\right)\times \cos \left(2{\theta }_f\right)+\cos \left({\theta }_f\right)\times \sin \left(2{\theta }_f\right)\\ \cos \left(3{\theta }_b\right)=\cos \left({\theta }_b\right)\times \cos \left(2{\theta }_b\right)-\sin \left({\theta }_b\right)\times \sin \left(2{\theta }_b\right)\\ \sin \left(3{\theta }_b\right)=\sin \left({\theta }_b\right)\times \cos \left(2{\theta }_b\right)+\cos \left({\theta }_b\right)\times \sin \left(2{\theta }_b\right)\end{array},n_0=2\text{:}\{\begin{array}{c}\cos \left(5{\theta }_f\right)=\cos \left(3{\theta }_f\right)\times \cos \left(2{\theta }_f\right)-\sin \left(3{\theta }_f\right)\times \sin \left(2{\theta }_f\right)\\ \sin \left(5{\theta }_f\right)=\sin \left(3{\theta }_f\right)\times \cos \left(2{\theta }_f\right)+\cos \left(3{\theta }_f\right)\times \sin \left(2{\theta }_f\right)\\ \cos \left(5{\theta }_b\right)=\cos \left(3{\theta }_b\right)\times \cos \left(2{\theta }_b\right)-\sin \left(3{\theta }_b\right)\times \sin \left(2{\theta }_b\right)\\ \sin \left(5{\theta }_b\right)=\sin \left(3{\theta }_b\right)\times \cos \left(2{\theta }_b\right)+\cos \left(3{\theta }_b\right)\times \sin \left(2{\theta }_b\right)\end{array},⋮n_0=c-1\text{:}\{\begin{array}{c}\cos \left(\left(2c-1\right){\theta }_f\right)=\cos \left(\left(2c-3\right){\theta }_f\right)\times \cos \left(2{\theta }_f\right)-\sin \left(\left(2c-3\right){\theta }_f\right)\times \sin \left(2{\theta }_f\right)\\ \sin \left(\left(2c-1\right){\theta }_f\right)=\sin \left(\left(2c-3\right){\theta }_f\right)\times \cos \left(2{\theta }_f\right)+\cos \left(\left(2c-3\right){\theta }_f\right)\times \sin \left(2{\theta }_f\right)\\ \cos \left(\left(2c-1\right){\theta }_b\right)=\cos \left(\left(2c-3\right){\theta }_b\right)\times \cos \left(2{\theta }_b\right)-\sin \left(\left(2c-3\right){\theta }_b\right)\times \sin \left(2{\theta }_b\right)\\ \sin \left(\left(2c-1\right){\theta }_b\right)=\sin \left(\left(2c-3\right){\theta }_b\right)\times \cos \left(2{\theta }_b\right)+\cos \left(\left(2c-3\right){\theta }_b\right)\times \sin \left(2{\theta }_b\right).\end{array}$

The hardware architecture can be implemented with reference to FIG. 14 in which is a schematic diagram of a cosine/sine factor generation device according to the embodiment.

TABLE 5.5.1
Hardware estimation of cosine and sine factor generation device
Multiplier	Adder	Rom
8	4	2m

Table 5.5.1 indicates the hardware estimation of cosine and sine factor generation device. It is known from Table 5.5.1 that the ROM size can be reduced from 2M to 2m, i.e., 1/c than the original, which is relatively improved in memory requirement, but the price is eight additional multipliers and four additional adders. To overcome this, the inventive architecture is further improved.

Cosine and sine factors' multiplication operation and data folding process:

Upon equation (32) and equation (34), the results of a DCT-III and DST-III operation are multiplied by the cosine and sine factors, and the results after the multiplication take an addition or subtraction operation to one another. Next, it is known from equation (58) and equation (63) that the data is folded to reduce the data amount to a half and input to the second stage of DST-II/DST-II operations. The cited above is the immediate stage of operations and generally divided into three steps as follows:

1. The input signals are multiplied by the cosine and sine factors respectively.

2. The signals multiplied by the cosine factor and by the sine factor are added or subtracted to one another.

3. The results after the operation in step (2) are folded.

The data after completing the immediate stage is stored in the registers. Since the folding operation reduces the data amount to a half, only [c/2] records of data are required in access. In addition, the immediate stage of operations can update the data of the registers, and the second stage of operations needs to repeatedly provide the immediate values c time to the registers, so that the data of the registers cannot be updated continuously. In this case, the number of registers is additionally doubled. Accordingly, c registers are required for the results of a folding operation. As to the hardware action of the folding operation, an example of c as even numbers is described as follows: generating c−1 data in step 2 and sequentially storing the 0-th to (c/2−1)-th records of data directly in the registers, as shown in FIG. 15 in which is a schematic diagram of the hardware action of inputting the upper half data in the folding operation according to the embodiment. The (c/2)-th to (c−1)-th records of data are operated with the data in the registers, and the results are stored back to the registers, as shown in FIG. 16 in which is a schematic diagram of a hardware action of inputting lower half data in the folding operation according to the embodiment.

Next, plugging equation (12) and equation (14) in equation (58) and equation (63), the relation can be obtained as follows.

T _c′(n₀,k₁,0)=T_c(n₀,k₁,0)+T_c(c−n₀−1,k₁,0),

T _c′(n₀,m−k₁−1,0)=T_c(n₀,m−k₁−1,0)+T_c(c−n₀−1,m−k₁−1,0),

T _c′(n₀,k₁,1)=T_c(n₀,k₁,1)+T_c(c−n₀−1,k₁,1),

T _c′(n₀,m−k₁−1,1)=T_c(n₀,m−k₁−1,1)+T_c(c−n₀−1,m−k₁−1,1),

T _s′(n₀,k₁,0)=T_s(n₀,k₁,0)+T_s(c−n₀−1,k₁,0),

T _s′(n₀,m−k₁−1,0)=T_s(n₀,m−k₁−1,0)+T_s(c−n₀−1,m−k₁−1,0),

T _s′(n₀,k₁,1)=T_s(n₀,k₁,1)+T_s(c−n₀−1,k₁,1),

T _s′(n₀,m−k₁−1,1)=T_s(n₀,m−k₁−1,1)+T_s(c−n₀−1,m−k₁−1,1),  (75)

where

• • if c is even, for n₀=0˜c/2−1
  • if c is odd, for n₀=0˜(c−1)/2−1
  • if m is even, for k₁=0˜m/2 1
  • if m is odd, for k₁=0˜(m−1)/2−1.

With reference to the relation above, 8c registers are totally required, and the corresponding hardware architectures are shown in FIG. 17(A) and FIG. 17(B). FIGS. 17(A) and 17(B) are schematic diagrams of a complete intermediate-stage operation architecture according to the embodiment, where

${\theta }_{M1}=\frac{\left(2n_0+1\right)\left(2k_1+1\right)\pi }{4M},{\theta }_{M2}=\frac{\left(2n_0+1\right)\left(2\left(m-k_1-1\right)+1\right)\pi }{4M}.$

TABLE 5.5.2
Cosine and sine factors' multiplication
operation and data folding process
Multiplier	Adder	Register
16	16	8c

Table 5.5.2 indicates the cosine and sine factors' multiplication operation and data folding process. It is known from Table 5.5.3 that the hardware cost for the immediate stage of operations is relatively high. To overcome this, the architecture is further improved.

As cited, it is discovered that the hardware cost for the immediate stage of operations is relatively high, which requires 24 multipliers and 20 adders in total. It is also easy to see in Table 5.5.3 that the multipliers of the immediate stage occupy 75% of the entire architecture while the adders occupy 67%, such that a total of 32 multipliers and 30 adders are required for the entire architecture, which is not expected in the invention because, though the operational speed or bit rate of the recursive architecture is relatively increased, the price is the huge hardware resources. Thus, reducing the hardware is further required for reducing the negative effect of the method.

TABLE 5.5.3
Hardware resource analysis
	Multiplier	Adder
	First-stage	3	5
	DCT-III/DST-III
	Second-stage	5	5
	DCT-II/DST-II
	Immediate-stage	24	20
	operations
	Entire architecture	32	30

First, the feature of the immediate-stage operations is first observed, where the input data is the results obtained from the first-stage operations, i.e., the immediate stage is operated only when the first stage generates the output data. As cited above, the first stage generates the output data every m cycles, such that the immediate stage is operated every m cycles. Upon the feature, the proposed solution uses the first and second stages of hardware to support the immediate-stage operations, and in this case the first and second stages of circuits are halted to increase more operational time. Namely, after the first stage generates the output data every m cycles, the first and second stages of circuits are halted. The hardware action on halting is described as follows:

1. The first halt cycle uses 3 multipliers, one adder in the first stage, and five multipliers, three adders in the second stage to thereby complete the operations of the aforementioned cosine and sine factor generation device.

2. The second halt cycle uses four multipliers, five adders in the first stage, and four multipliers, three adders in the second stage to thereby complete the operations of T_c′(n₀,k₁,0), T_c′(n₀,k₁,1), T_s′(n₀,k₁,0) T_s′(n₀,k₁,1) in FIGS. 17(A) and 17(B).

3. The third halt cycle uses four multipliers, five adders in the first stage and four multipliers, three adders in the second stage to thereby complete the operations of T_c′(n₀,m−k₁−1,0), T_c′(n₀,m−k₁−1,1), T_s′(n₀,m−k₁−1,0), T_s′(n₀,m−k₁−1,1) in FIGS. 17(A) and 17(B).

FIG. 18 is a schematic diagram of the operations corresponding to the halt cycles according to the embodiment. As shown in FIG. 18, with three halt cycles, the hardware architecture in the first and the second stages can be shared to thereby replace the 24 multipliers and 20 adders required for the immediate stage.

FIG. 19 is a schematic diagram of the modified recursive type-III discrete cosine/sine transform device according to the embodiment. FIG. 20 is a schematic diagram of the recursive type-II discrete cosine/sine transform device according to the embodiment. With reference to FIGS. 19 and 20, each halt cycle uses the multipliers and adders in the first and the second stages, and the corresponding hardware is shown in Table 5.5.4.

TABLE 5.5.4
Corresponding hardware of each halt cycle
Halt Cycle	Multiplier Number	Adder Number
1	1.2.3.4.5.6.7.8	1.6.7.9
2	1.2.3.4.5.6.7.8	1.2.3.4.5.6.7.9
3	1.2.3.4.5.6.7.8	1.2.3.4.5.6.7.9

The concept of the common hardware is to provide different input signals in hardware at different time points, and thus additional multiplexers are used to control the select lines of the added multiplexers to thereby select the different input data. Therefore, the purpose of sharing the hardware is achieved. It is known in Table 5.5.5 that a number of transistors of a multiplexer (MUX) are far fewer than that of an adder and of a multiplier, so the effectiveness is very high while the multiplexers are used to reduce a number of used multipliers and adders,

TABLE 5.5.5
Transistor number of 24-bit component
	Component	Latch	Adder	Multiplier	Multiplexer
	Transistors	240	672	18624	192

In addition, the more the hardware is shared, the more the number of added multiplexers, but different hardware may have a same input signal corresponding to a same multiplexer, i.e., the different hardware may come from the same multiplexer. Such a multiplexer with the cited feature is shown in FIG. 20. For example, the multipliers with Number 1 and Number 5 commonly use the multiplexer which selects cos(θ_f) or cos(2θ_f) as an output. Thus, the input signal of the multipliers with Number 1 and Number 5 only requires sharing the multiplexer with com_mux1 shown in FIG. 21.

As shown in FIG. 19, when the recursive type-III discrete cosine/sine transform device 1320 and the recursive type-II discrete cosine/sine transform device 1330 are in the second operational mode, the devices 1320 and 1330 sequentially perform cosine/sine factor multiplication and corresponding addition operations on the c in-point second temporal signals for generating the c third temporal signals each with m points sequentially.

As shown in FIG. 19, the recursive type-III discrete cosine/sine transform device 1320 includes first to sixth registers 1911-1916, first to fifth adders 1931-1935, a 3-to-1 multiplexer 1951, a second 3-to-1 multiplexer 1952, a first multiplier 1971, a second multiplier 1972, and a fourth multiplier 1974.

As shown in FIG. 20, the recursive type-II discrete cosine/sine transform device 1330 includes seventh to twelfth registers 2017-2020, sixth to tenth adders 2036-2040, a third 3-to-1 multiplexer 2051, a fourth 3-to-1 multiplexer 2052, a third multiplier 2073, a fifth multiplier 2075, a sixth multiplier 2076, a seventh multiplier 2077, and an eighth multiplier 2078.

FIG. 21 is a schematic diagram of using common multiplexers according to the embodiment. In FIG. 21, the output signal of a common or shared multiplexer is output to a multiplexer in front of the multipliers. FIGS. 22(A) and 22(B) are schematic diagrams of using common multipliers and adders according to an embodiment of the embodiment. As shown in FIGS. 22(A) and 22(B), multiplier numbering and adder numbering are shown in FIGS. 19 and 20, where a same number indicates the same multiplier or adder. In addition, FirstStage_node in FIGS. 22(A) and 22(B) indicates the original input signals of the multipliers or adders in the first stage of circuit at the DCT-III/DST-III operations, SecondStage_node indicates the original input signals of the multipliers or adders in the second stage of circuit at the DCT-II/DST-II operations, and FirstStage_out1, FirstStage_out2, FirstStage_out3, FirstStage_out4 indicate the DCT-III/DST-III output signals after the first-stage operation, as shown in Table 5.3.1.

As shown in FIGS. 22(A) and 22(B), in a non-halt cycle, every circuit outputs the original signals of the DCT-III/DST-III in the first stage or DCT-II/DST-II in the second stage. In a halt cycle, all hardware supports the immediate stage of operations, and the output signals of each circuit are shown in Table 5.5.6. The common hardware scheme proposed in the invention can effectively reduce the hardware requirement, and a comparison is shown in Table 5.5.7 in which the number of multipliers and the number of adders are used with and without the common hardware design.

TABLE 5.5.6
Outputs of common hardware in different halt cycles
	First Halt	Second Halt	Third Halt
	Cycle	Cycle	Cycle
	Output1	Cos2θ	Tc(n0, k1, 0)	Ts(n0, m −
		Cos(2n0 + 1)θ		1 − k1, 1)
	Output2	Cos2θb	Ts(n0, k1, 1)	Tc(n0, m −
		Cos(2n0 + 1)θ		1 − k1, 0)
	Output3	Sin2θ	Ts(n0, k1, 0)	Tc(n0, m −
		Sin(2n0 + 1)θ		1 − k1, 1)
	Output4	Sin2θ	Ts(n0, k1, 1)	Ts(n0, m −
		Sin(2n0 + 1)θb		1 − k1, 0)
	Output5	FirstStage_node	T′c(n0, k1, 0)	T′c(n0, m −
				1 − k1, 0)
	Output6	FirstStage_node	T′s(n0, k1, 1)	T′s(n0, m −
				1 − k1, 1)
	Output7	FirstStage_node	T′c(n0, k1, 1)	T′c(n0, m −
				1 − k1, 1)
	Output8	FirstStage_node	T′s(n0, k1, 0)	T′s(n0, m −
				1 − k1, 0)
	indicates data missing or illegible when filed

TABLE 5.5.7
Multiplier and adder number
	Multiplier	Adder
	Non-Common Hardware Design	32	30
	Common Hardware Design	8	10

Hardware Action and Cycle Number Estimation:

For implementing the proposed method in the invention, it is known as cited that the input data is pre-processed and sequentially input to the first stage of hardware architecture to operate. The first-stage hardware performs m-point DCT-III/DST-III operations and, upon the improved method and architecture, every m cycles can generate two records of data in transformation. The data generated in every m cycles passes through c cycles in the first stage to produce two sets of c-point data, and accordingly M-point outputs are generated for completing all data operations in the first-stage architecture. In this case, referring again to FIG. 2, the number of cycles is shown as follows.

m×c×[m/2].  (76)

As cited, it is known that the c-point DCT-II/DST-II operations are performed by the second-stage hardware and, upon the improved method and architecture, every [c/2]cycles can generate two records of data in transformation. Accordingly, M-point outputs are generated for completing all data operations in the second-stage architecture. In this case, referring again to FIG. 2, the number of cycles is shown as follows.

[c/2]×c×[m/2].  (77)

The invention uses a pipelined architecture to implement the required hardware in which the first stage generates the c-point data. The c-point data is operated with the immediate-stage cosine/sine factors to thereby introduce the data into the second stage. By pipelining, the first stage and the second stage of circuits can be concurrently operated as shown in FIG. 6, and the operational periods of the entire architecture are shown in Table 5.6.1 as follows.

TABLE 5.6.1
Cycles of M-point DCT-IV operation (no common hardware)
	m
c	Even	Odd
Even	$m\times c\times \frac{m}{2}+\frac{c}{2}\times c$	$m\times c\times \frac{m+1}{2}+\frac{c}{2}\times c$
Odd	$m\times c\times \frac{m}{2}+\frac{c+1}{2}\times c$	$m\times c\times \frac{m+1}{2}+\frac{c+1}{2}\times c$

In the invention, the cosine and sine factor accesses require an overlarge memory, so that the circuits used for the factor generation device relatively reduce the ROM size and additionally increase the multipliers and adders. In addition, since the immediate-stage operations also require a lot of hardware, the first stage and the second stage are re-designed to share the hardware to thereby reduce the number of adders and multipliers, as shown in Table 5.5.6. However, the operational period is slightly increased due to the common hardware, as shown in Table 5.6.2.

TABLE 5.6.2
M-point DCT-IV operational period (with commonhardware)
	m
c	Even	Odd
Even	$\left(m+3\right)\times c\times \frac{m}{2}+\frac{c}{2}\times c$	$\left(m+3\right)\times c\times \frac{m+1}{2}+\frac{c}{2}\times c$
Odd	$\left(m+3\right)\times c\times \frac{m}{2}+\frac{c+1}{2}\times c$	$\left(m+3\right)\times c\times \frac{m+1}{2}+\frac{c+1}{2}\times c$

• • From Table 5.6.2, it is seen that the whole operational period is dependent of m and c values. There are many types for dividing an M-point DCT-IV into m-point and c-point combinations, but the main point worth discussing is which type of m-point and c-point combination can make the entire hardware to have the highest performance and the smallest operational period.

First, the processing speed of the first stage in the pipelined hardware architecture cannot be greater than that of the second stage, otherwise the following stages cannot process the data output by the previous stage in real-time so as not to operate the entire architecture smoothly. For optimally operating the pipelined architecture, the first stage and the second stage needs to have a same operational period, and the number of points to be divided, i.e., m and c, can influence the operational period of the first stage and of the second stage. Next, it is known from Equation (76) and Equation (77) that the second-stage operational period is half the first-stage operational period. For an example of m, c as an even, when the first stage and second stage have a same operational period, the equality is derived from Equation (76) and Equation (77) as follows.

$\begin{array}{cc}m=\frac{c}{2}.& \left(78\right)\end{array}$

Equation (78) indicates that such an architecture has the highest performance when the number of points in the second stage is double that in the first stage. Thus, the number of points in this architecture is distributed to the second stage greater than the first stage as far as possible, but in cannot be small than c/2 to avoid that the second-stage operational period is greater than the first-stage operational period.

The proposed method and architecture is described. For an example of m, c as an even, as compared with N2/2 cycles required for the typical recursive architecture, it is known in Table 5.6.2 that the number of cycles required for the inventive design is:

$\begin{array}{cc}\left(m+3\right)\times c\times \frac{m}{2}+\frac{c}{2}\times c=\left(m+3\right)\times \frac{N}{4}+\frac{c^2}{2}.& \left(79\right)\end{array}$

As cited, the kernel hardware for the recursive type-III discrete cosine/sine transform device 120 and the recursive type-II discrete cosine/sine transform device 140 in the invention can support the DCT-IV/DCT-II/DCTIII/DST-II/DST-III operations concurrently and merge the pre- and post-processing operations for the first permutation device 110 and the second permutation device 150 to implement the IMDCT/MDCT/AQMF/SQMF operations to thereby gain the co-architecture design of analysis and synthesis filter-banks. Therefore, the operational period is relatively improved, as compared other recursive algorithms.

Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.

Claims

1. A recursive type-IV discrete cosine transform system, comprising: a first permutation device for receiving N digital input signals and performing a two-dimensional order permutation operation on the N digital signals to generate N two-dimensional first temporal signals, where N is a positive integer;a recursive type-III discrete cosine/sine transform device which is an m-point recursive type-III discrete cosine/sine transform device connected to the first permutation device for receiving the N first temporal signals and repeating a type-III discrete cosine/sine transform c times on the N first temporal signals to generate c second temporal signals each with m points, where N=m×c, and m, c are each a positive integer;a cosine/sine factor generation device connected to the recursive type-III discrete cosine/sine transform device for sequentially performing cosine/sine factor multiplication and corresponding addition operations on the m-point second temporal signals to generate c third temporal signals each with m points;a recursive type-II discrete cosine/sine transform device which is a c-point recursive type-II discrete cosine/sine transform device connected to the cosine/sine factor generation device for receiving the third temporal signals and repeating a type-II discrete cosine/sine transform m times to generate m fourth temporal signals each with c points; anda second permutation device connected to the recursive type-II discrete cosine/sine transform device for receiving the fourth temporal signals and performing a one-dimensional order permutation operation on the fourth temporal signals for generating N one-dimensional output signals,wherein the N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform on the N digital input signals.

2. The recursive type-IV discrete cosine transform system as claimed in claim 1, wherein the recursive type-III discrete cosine/sine transform device is implemented in a common hardware architecture.

3. The recursive type-IV discrete cosine transform system as claimed in claim 2, wherein a computational period of the recursive type-III discrete cosine/sine transform device comprises m×(m+1)/2 cycles.

4. The recursive type-IV discrete cosine transform system as claimed in claim 3, wherein the recursive type-II discrete cosine/sine transform device is implemented in a common hardware architecture.

5. The recursive type-IV discrete cosine transform system as claimed in claim 4, wherein a computational period of the recursive type-II discrete cosine/sine transform device comprises c×(c+1)/2 cycles.

6. The recursive type-IV discrete cosine transform system as claimed in claim 5, wherein the recursive type-III discrete cosine/sine transform device comprises first to sixth registers, first to fifth adders, a first 3-to-1 multiplexer, a second 3-to-1 multiplexer, a first multiplier, a second multiplier, and a fourth multiplier.

7. The recursive type-IV discrete cosine transform system as claimed in claim 6, wherein the recursive type-II discrete cosine/sine transform device comprises seventh to twelfth registers, sixth to tenth adders, a third 3-to-1 multiplexer, a fourth 3-to-1 multiplexer, a third multiplier, a fifth multiplier, a sixth multiplier, a seventh multiplier, and an eighth multiplier.

8. A recursive type-IV discrete cosine transform system, comprising: a first permutation device for receives N digital input signals and performing a two-dimensional order permutation operation on the N digital signals to generate N two-dimensional first temporal signals, where N is a positive integer;a modified recursive type-III discrete cosine/sine transform device connected to the first permutation device and having a first and a second operational modes such that in the first operational mode a type-III discrete cosine/sine transform is repeated c times on the N first temporal signals for generating c second temporal signals each with m points, where N=m×c, and m, c are each a positive integer;a recursive type-II discrete cosine/sine transform device connected to the modified recursive type-III discrete cosine/sine transform device and having a first and a second operational modes such that in the first operational mode a third temporal signal is received and a type-II discrete cosine/sine transform is repeated m times on the third temporal signal for generating m fourth temporal signals each with c points; anda second permutation device connected to the recursive type-II discrete cosine/sine transform device for receiving the fourth temporal signals and performing a one-dimensional order permutation operation on the fourth temporal signals to generate N one-dimensional output signals,wherein the N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform on the N digital input signals.

9. The recursive type-IV discrete cosine transform system as claimed in claim 8, wherein, in the second operational mode, the recursive type-III discrete cosine/sine transform device and the recursive type-II discrete cosine/sine transform device sequentially perform cosine/sine factor multiplication and corresponding addition operations on the c second temporal signals for generating c third temporal signals each with m points.

10. The recursive type-IV discrete cosine transform system as claimed in claim 9, wherein the recursive type-III discrete cosine/sine transform device comprises first to sixth registers, first to fifth adders, a first 3-to-1 multiplexer, a second 3-to-1 multiplexer, a first multiplier, a second multiplier, and a fourth multiplier.

11. The recursive type-IV discrete cosine transform system as claimed in claim 10, wherein the recursive type-II discrete cosine/sine transform device comprises seventh to twelfth registers, sixth to tenth adders, a third 3-to-1 multiplexer, a fourth 3-to-1 multiplexer, a third multiplier, a fifth multiplier, a sixth multiplier, a seventh multiplier, and an eighth multiplier.