Patent Application
20240297267
Embodiments of the disclosure generally relate to arrays of light emitting diode (LED) devices and methods of manufacturing the same. More particularly, embodiments are directed to light emitting diode devices, specifically an LED that maintains a true red wavelength, a high wall plug efficiency, and low forward voltage at current densities greater than 2 A/cm2.
A light emitting diode (LED) is a semiconductor light source that emits visible light when current flows through it. LEDs combine a P-type semiconductor with an N-type semiconductor. LEDs commonly use a III-group compound semiconductor. A III-group compound semiconductor provides stable operation at a higher temperature than devices that use other semiconductors. The III-group compound is typically formed on a substrate formed of sapphire or silicon carbide (SIC).
Red-emitting InGaN LEDs are of interest for microLED display applications. Although the InGaN materials system suffers from decreasing internal quantum efficiency at longer wavelengths it has the advantage of being relatively insensitive to surface recombination. Due to their high sensitivity to non-radiative surface recombination, there is evidence that LEDs built from the AlInGaP materials system underperform InGaN red LEDs in the regime of smaller LED dimensions (<10 microns) and lower operating current densities. Aside from potential advantages in red microLED efficiency, it is desirable to use InGaN (rather than AlInGaP) for the red emitters in displays to facilitate integration with green and blue emitters which are necessarily based on the InGaN materials system.
Current InGaN red epitaxy does not meet the performance criteria for microLED display applications. Two general challenges of the InGaN materials system are that the emission spectrum has a broad full-width half maximum (FWHM), and that the wavelength shifts to much shorter wavelength as the injected current density increases. Displays with high color quality require a true red emitter characterized by a dominant wavelength of 610 nm or longer. Due to the broad FWHM, the dominant wavelength of current red InGaN LEDs is at least 10 nm shorter than the peak wavelength. High efficiency “red” LEDs have emission spectra acceptable for displays only when the LED is operated at sufficiently low current density.
Accordingly, there is a need for improved LED devices which maintain a red wavelength over wider ranges of operating current density.
Embodiments of the disclosure are directed to LED devices and methods for manufacturing LED devices. In one or more embodiments, a light emitting diode (LED) device comprises: a quantum well comprising an indium gallium nitride (InGaN) well and a barrier layer, the indium gallium nitride (InGaN) well having an indium concentration greater than 18% mole fraction, the device having a dominant wavelength greater than 605 nm at a current density of greater than or equal to 2 A/cm2.
Other embodiments of the disclosure are directed to a light emitting diode (LED) system comprising: a light emitting diode (LED) array comprising: a nucleation layer on a substrate; an n-type layer on the nucleation layer; a quantum well on the n-type layer, the quantum well comprising an indium gallium nitride (InGaN) well and a gallium nitride (GaN) barrier layer, the indium gallium nitride (InGaN) well having an indium concentration greater than 18% mole fraction; and a plurality of p-type layers on the quantum well, the device having a dominant wavelength greater than 605 nm at a current density greater than or equal to 2 A/cm2.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. The embodiments as described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale. For example, the heights and widths of the mesas are not drawn to scale.
Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.
The term “substrate” as used herein according to one or more embodiments refers to a structure, intermediate or final, having a surface, or portion of a surface, upon which a process acts. In addition, reference to a substrate in some embodiments also refers to only a portion of the substrate, unless the context clearly indicates otherwise. Further, reference to depositing on a substrate according to some embodiments includes depositing on a bare substrate or on a substrate with one or more layers, films, features, or materials deposited or formed thereon.
In one or more embodiments, the “substrate” means any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. In exemplary embodiments, a substrate surface on which processing is performed includes materials such as silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon doped silicon oxides, germanium, gallium arsenide, glass, sapphire, and any other suitable materials such as metals, metal nitrides, III-nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, light emitting diode (LED) devices. Substrates in some embodiments are exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the film processing steps disclosed is also performed on an underlayer formed on the substrate, and the term “substrate surface” is intended to include such underlayer as the context indicates. Thus, for example, where a film/layer or partial film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.
The term “wafer” and “substrate” will be used interchangeably in the instant disclosure. Thus, as used herein, a wafer serves as the substrate for the formation of the LED devices described herein.
Embodiments described herein describe LED devices and methods for forming LED devices. In particular, the present disclosure describes LED devices and methods to produce LED devices which advantageously maintain a true red wavelength suitable for display application at a current density greater than or equal to 2 A/cm2. In one or more embodiments, the epitaxy design has a low forward voltage, high wall plug efficiency, and small reverse leakage current. The improved process is readily manufacturable in one epitaxy step using standard substrates and mass production MOCVD equipment.
Not all microLEDs manufactured from a given wafer (or set of wafers) can realistically be expected to have equal external quantum efficiency (EQE) values in the as-fabricated state and/or after a display has been in use for some time. Since there is realistically some variation in EQE between different pixels, it may be required to operate some of the microLEDs at higher current densities than others in order to maintain a consistent surface radiance over the entire area of the display. An epitaxy design that exhibits a change in emission color from red to orange with only a moderate increase in current density may not be desirable for practical applications.
The embodiments of the disclosure are described by way of the Figures, which illustrate devices and processes for forming devices in accordance with one or more embodiments of the disclosure. The processes shown are merely illustrative possible uses for the disclosed processes, and the skilled artisan will recognize that the disclosed processes are not limited to the illustrated applications.
One or more embodiments of the disclosure are described with reference to the Figures.
In one or more embodiments, a nucleation layer 104 and a defect reduction layer 106 are grown on a substrate 102, followed by an n-type layer 108. In some embodiments, a superlattice 110 comprised of alternating pairs of an indium gallium nitride (InGaN) layer 112 and a gallium nitride (GaN) layer 114 is grown over the n-type layer 108. In one or more embodiments, the superlattice 110 comprises a range of from 5 to 70 alternating pairs of an InGaN layer 112 and a GaN layer 114, or a range of from 10 to 50 alternating pairs of an InGaN layer 112 and a GaN layer 114. In one or more embodiments, the superlattice 110 comprises 40 pairs alternating pairs of an InGaN layer 112 and a GaN layer 114.
The substrate 102 may be any substrate known to one of skill in the art which is configured for use in the formation of LED devices. In one or more embodiments, the substrate 102 comprises one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, and the like. In one or more embodiments, the substrate 102 is a transparent substrate. In specific embodiments, the substrate 102 comprises sapphire. In one or more embodiments, the substrate 102 is not patterned prior to formation of the LEDs. Thus, in some embodiments, the substrate is 102 not patterned and can be considered to be flat or substantially flat. In other embodiments, the substrate 102 is a patterned substrate.
In one or more embodiments, the n-type layer 108 may comprise any Group III-V semiconductors, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as III-nitride materials. Thus, in some embodiments, the n-type layer 108 comprises one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), and the like. In a specific embodiment, the n-type layer 108 comprises gallium nitride (GaN). In one or more embodiments, the n-type layer 108 is doped with n-type dopants, such as silicon (Si) or germanium (Ge). The n-type layer 108 may have a dopant concentration significant enough to carry an electric current laterally through the layer. In some embodiments, the n-type layer 108 comprises a GaN contact layer.
In one or more embodiments, a nucleation layer 104 is formed on the substrate 102 prior to the defect reduction layer 106. In one or more embodiments, the nucleation layer comprises 104 a III-nitride material. In specific embodiments, the nucleation layer 104 comprises gallium nitride (GaN) or aluminum nitride (AlN).
In one or more embodiments, the layers of III-nitride material may be deposited by one or more of sputter deposition, atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE).
“Sputter deposition” as used herein refers to a physical vapor deposition (PVD) method of thin film deposition by sputtering. In sputter deposition, a material, e.g., a III-nitride is ejected from a target that is a source onto a substrate. The technique is based on ion bombardment of a source material, the target. Ion bombardment results in a vapor due to a purely physical process, i.e., the sputtering of the target material.
As used herein according to some embodiments, “chemical vapor deposition” refers to a process in which films of materials are deposited from the vapor phase by decomposition of chemicals on a substrate surface. In CVD, a substrate surface is exposed to precursors and/or co-reagents simultaneous or substantially simultaneously. A particular subset of CVD processes commonly used in LED manufacturing use metalorganic precursor chemical and are referred to as MOCVD or metalorganic vapor phase epitaxy (MOVPE). As used herein, “substantially simultaneously” refers to either co-flow or where there is overlap for a majority of exposures of the precursors.
In one or more embodiments, LED device 100 is manufactured by placing the substrate 102 in a metalorganic vapor-phase epitaxy (MOVPE) reactor so that the LED device layers are grown epitaxially.
In one or more embodiments, a multi-quantum well 116 is formed on the superlattice 110. The multi-quantum well 116 comprises pairs of a quantum barrier layer 118 and a quantum well 120. The quantum barrier layer 118 may comprise any suitable material known to the skilled artisan. In some embodiments, the quantum barrier layer 118 comprises a gallium nitride (GaN) layer. The quantum well 120 may comprise any suitable material known to the skilled artisan. In some embodiments, the quantum well 120 comprises indium gallium nitride (InGaN) wells. In one or more embodiments, the quantum well 120 has an indium concentration greater than 18% mole fraction.
The multi-quantum well 116 may comprise different layers of indium gallium nitride (InGaN) and gallium nitride (GaN). The emission color may be controlled by the relative mole fractions of indium (In) and gallium (Ga) in the InGaN layer and/or by the thicknesses of the multiple quantum wells, and by the compositions of the barrier layers.
The multi-quantum well 116 may be formed using any deposition technique known to one of skill in the art. The multi-quantum well 116 may comprise a sequence of multiple quantum wells emitting the same wavelength of light. In one or more embodiments, the multi-quantum well 116 emits light having a wavelength in a range of from greater than 605 nm to 700 nm.
In one or more embodiments, an individual quantum well 120 within the multi-quantum well 116 may have an InGaN thickness in a range of from about 0.5 nm to about 10 nm. In some embodiments, the first quantum well 120a has a thickness in a range of from 3 nm to 4 nm. The total number of quantum wells in the multi-quantum well 116 may be in a range of from 1 to 30. In some embodiments, there are two quantum wells 120a, 120b in the multi-quantum well 116.
In some embodiments, the active region is comprised of two quantum wells 120a, 120b. In some embodiments, the quantum wells 120a, 120b comprise indium gallium nitride (InGaN) wells. In one or more embodiments, the quantum wells 120a, 120b have an indium concentration greater than 18% mole fraction.
In one or more embodiments, a first quantum barrier layer 118a is under the first quantum well 120a. In some embodiments, the first quantum barrier layer 118a comprises gallium nitride (GaN). The first quantum barrier layer 118a can have a thickness in a range of from 10 nm to 30 nm, or in a range of from 18 nm to 22 nm.
In one or more embodiments, the second quantum barrier layer 118b comprises a first layer 118b1 and a second layer 118b2 to form a bi-layer structure. In some embodiments, the first layer 118b1 comprises a material selected from one or more of aluminum gallium nitride (AlGaN) and gallium nitride (GaN). In specific embodiments, the first layer 118b1 comprises aluminum gallium nitride (AlGaN). The aluminum gallium nitride (AlGaN) may contain from 15% to 25% mole fraction of aluminum (Al). The first layer 118b1 may have a thickness in a range of from 3 nm to 5 nm. In some embodiments, the second layer 118b2 comprises a material selected from one or more of aluminum gallium nitride (AlGaN) and gallium nitride (GaN). In specific embodiments, the second layer 118b2 comprises gallium nitride (GaN). The second layer 118b2 may have a thickness in a range of from 5 nm to 20 nm, or a range of from 15 nm to 18 nm.
In some embodiments, the quantum barrier layer 118 may be doped with a barrier dopant. The quantum barrier layer 118 may contain any suitable barrier dopant concentration.
In some embodiments, the quantum barrier layer 118 has a barrier dopant concentration in a range of from 5×1017 cm−3 to 5×1018 cm−3. The barrier dopant may be selected from one or more of silicon (Si), germanium (Ge), tin (Sn), and oxygen (O).
In one or more embodiments, a series of aluminum gallium nitride (AlGaN) layers 122a, 122b, 122c and gallium nitride (GaN) layers 124a, 124b are grown on the active region. In some embodiments, the aluminum gallium nitride layers 122a, 122b, 122c have a thickness in a range of from 1 nm to 10 nm. In some embodiments, as the distance away from the active region increases, the thickness of the aluminum gallium nitride layers 122a, 122b, 122c increases. The aluminum gallium nitride layers 124a, 124b may contain from 15% to 25% mole fraction of aluminum (Al). In some embodiments, the gallium nitride layers 124a, 124b have a thickness in a range of from 1 nm to 5 nm.
In one or more embodiments, a p-type layer 126 is grown over the aluminum gallium nitride (AlGaN) layer 122c. In one or more embodiments, the p-type layer 126 may comprise any Group III-V semiconductors, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as III-nitride materials. Thus, in some embodiments, the p-type layer 126 comprises one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), and the like.
In some embodiments, the p-type layer 126 comprises a doped p-type layers. The p-type layer 126 may be doped with any suitable p-type dopant known to the skilled artisan. In one or more embodiments, the p-type layer 126 may be doped with magnesium (Mg). In one or more embodiments, the p-type layer 126 comprises a magnesium doped p-type gallium nitride layer.
The disclosure is now described with reference to the following examples. Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.
An LED having an indium gallium nitride (InGaN) well and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 18% mole fraction. The device had a dominant wavelength of 612 nm at a current density of 1.2 A/cm2 and maintained a dominant wavelength greater than 605 nm at a current density of greater than or equal to 2 A/cm2.
An LED having an indium gallium nitride (InGaN) well and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 18% mole fraction. The device had a dominant wavelength of 610 nm at a current density of 1.2 A/cm2.
An LED having an indium gallium nitride (InGaN) well and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 18% mole fraction. The device had 10 superlattice pairs. The device had a dominant wavelength greater than 605 nm at a current density of greater than or equal to 2 A/cm2.
An LED having an indium gallium nitride (InGaN) well and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 18% mole fraction. The device had 40 superlattice pairs. The device had a dominant wavelength greater than 605 nm at a current density of greater than or equal to 6 A/cm2.
An LED having an indium gallium nitride (InGaN) well and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 18% mole fraction. The device had 50 superlattice pairs. The device had a dominant wavelength greater than 605 nm at a current density of greater than or equal to 6 A/cm2.
A key to obtaining LEDs with longer red wavelengths and high wall-plug efficiency (WPE) is the growth of a superlattice with multiple pairs of GaN and lower % In composition InGaN before the growth of the high % In composition active region.
An LED having an indium gallium nitride (InGaN) well and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 18% mole fraction. The device had 40 superlattice pairs. The device had a dominant wavelength greater than 605 nm at a current density of greater than or equal to 2 A/cm2.
An LED having an indium gallium nitride (InGaN) well and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 18% mole fraction. The device had 50 superlattice pairs. The device had a dominant wavelength greater than 605 nm at a current density of greater than or equal to 2 A/cm2.
A second key to obtaining LEDs with longer red wavelengths and high WPE is to optimize the design of the quantum barriers. The best performance was found for a barrier design with an AlGaN layer grown directly on the InGaN QW and a GaN layer that did not contain Al grown directly under the InGaN QW. As shown in
An LED having three indium gallium nitride (InGaN) wells and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 18% mole fraction. The device had 40 superlattice pairs. The device had a dominant wavelength greater than 605 nm at a current density of greater than or equal to 2 A/cm2.
When the number of quantum wells is increased to three or decreased to one, it makes only a minor difference in WPE. Without intending to be bound by theory, it is believed that all or most of the red light emission is generated in the well closet to the p-GaN contact layer. Also, while the optimized epitaxy design uses silicon doping in the barrier layers it is found that large changes can be made to the silicon concentration with at most a minor effect on WPE. For example, as shown in
An LED having an indium gallium nitride (InGaN) well and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 18% mole fraction. The device had 40 superlattice pairs. The device had a dominant wavelength greater than 605 nm at a current density of greater than or equal to 2 A/cm2.
The design of the barrier layer under the first QW is another example of a parameter that may be changed without a large impact on WPE. As shown in
An LED having an indium gallium nitride (InGaN) well and a barrier layer was prepared. The indium gallium nitride (InGaN) well had an indium concentration greater than 20% mole fraction. The device had a dominant wavelength of 612 nm at a current density of 1.2 A/cm2 and maintained a dominant wavelength greater than 605 nm at a current density of greater than or equal to 2 A/cm2.
Various embodiments are listed below. It will be understood that the embodiments listed below may be combined with all aspects and other embodiments in accordance with the scope of the invention.
Embodiment (a). A light emitting diode (LED) device comprising: a quantum well comprising an indium gallium nitride (InGaN) well and a barrier layer, the indium gallium nitride (InGaN) well having an indium concentration greater than 18% mole fraction, the device having a dominant wavelength greater than 605 nm at a current density of greater than or equal to 2 A/cm2.
Embodiment (b). The LED device of embodiment (a), wherein the device has a dominant wavelength in a range of from greater than 605 nm to 630 nm at a current density in a range of from greater than 2 A/cm2 to 100 A/cm2.
Embodiment (c). The LED device of embodiments (a) to (b), wherein the device has a forward voltage less than 2.4 V at the current density of greater than or equal to 2 A/cm2.
Embodiment (d). The LED device of embodiments (a) to (c), wherein the device has a wall-plug efficiency (WPE) greater than 3% at the current density greater than or equal to 2 A/cm2.
Embodiment (e). The LED device of embodiments (a) to (d), wherein the device has a reverse leakage current less than 0.01 A/cm2 at a bias of 15 V.
Embodiment (f). The LED device of embodiments (a) to (e), further comprising a superlattice structure on an n-type layer on a nucleation layer on a substrate, the superlattice structure comprising a first portion and a second portion of alternating pairs of an indium gallium nitride (InGaN) layer and a gallium nitride (GaN) layer, the quantum well on the superlattice structure.
Embodiment (g). The LED device of embodiments (a) to (f), wherein the second portion has a second dopant concentration of less than 5×1017 cm−3 and an indium concentration of less than 15% mole fraction.
Embodiment (h). The LED device of embodiments (a) to (g), wherein the first portion has a first dopant concentration in a range of from 1×1018 cm−3 to 5×1018 cm−3 and an indium concentration of less than 10% mole fraction.
Embodiment (i). The LED device of embodiments (a) to (h), wherein the first dopant and the second dopant are independently selected from one or more of silicon (Si), germanium (Ge), tin (Sn), and oxygen (O).
Embodiment (j). The LED device of embodiments (a) to (i), wherein the barrier layer comprises a first layer and a second layer, the first layer and second layer independently selected from one or more of aluminum gallium nitride (AlGaN) and gallium nitride (GaN).
Embodiment (k). The LED device of embodiments (a) to (j), wherein the barrier layer is doped with a barrier dopant in a range of from 5×1017 cm−3 to 5×1018 cm−3, the barrier dopant selected from one or more of silicon (Si), germanium (Ge), tin (Sn), and oxygen (O).
Embodiment (l). The LED device of embodiments (a) to (k), further comprising a plurality of p-type layers on the quantum well.
Embodiment (m). The LED device of embodiments (a) to (l), wherein the plurality of p-type layers comprise one or more of an aluminum gallium nitride (AlGaN) layer and a gallium nitride layer (GaN).
Embodiment (n). A light emitting diode (LED) device comprising: a nucleation layer on a substrate; an n-type layer on the nucleation layer; a quantum well on the n-type layer, the quantum well comprising an indium gallium nitride (InGaN) well and a barrier layer, the indium gallium nitride (InGaN) well having an indium concentration greater than 18% mole fraction; and a plurality of p-type layers on the quantum well, the device having a dominant wavelength greater than 605 nm at a current density greater than or equal to 2 A/cm2.
Embodiment (o). The LED device of embodiment (n), wherein the device has a forward voltage less than 2.4 V at the current density of greater than or equal to 2 A/cm2.
Embodiment (p). The LED device of embodiments (n) to (o), wherein the device has a wall-plug efficiency (WPE) greater than 3% at the current density of greater than or equal to 2 A/cm2.
Embodiment (q). The LED device of embodiments (n) to (p), wherein the device has a reverse leakage current less than 0.01 A/cm2 at a bias of 15 V.
Embodiment (r). The LED device of embodiments (n) to (q), further comprising a superlattice structure between the n-type layer and the quantum well, the superlattice structure comprising a first portion and a second portion of alternating pairs of an indium gallium nitride (InGaN) layer and a gallium nitride (GaN) layer.
Embodiment (s). The LED device of embodiments (n) to (r), wherein the second portion has a second dopant concentration of less than 5×1017 cm−3 and an indium concentration of less than 15% mole fraction, and the first portion has a first dopant concentration in a range of from 1×1018 cm−3 to 5×1018 cm−3 and an indium concentration of less than 10% mole fraction.
Embodiment (t). The LED device of embodiments (n) to (s), wherein the barrier layer comprises a first layer and a second layer, the first layer and second layer independently selected from one or more of aluminum gallium nitride (AlGaN) and gallium nitride (GaN).
The use of the terms “a” and “an” and “the” and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.
Reference throughout this specification to the terms first, second, third, etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another.
Reference throughout this specification to a layer, region, or substrate as being “on” or extending “onto” another element, means that it may be directly on or extend directly onto the other element or intervening elements may also be present. When an element is referred to as being “directly on” or extending “directly onto” another element, there may be no intervening elements present. Furthermore, when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element and/or connected or coupled to the other element via one or more intervening elements. When an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present between the element and the other element. It will be understood that these terms are intended to encompass different orientations of the element in addition to any orientation depicted in the figures.
Relative terms such as “below,” “above,” “upper,”, “lower,” “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
Reference throughout this specification to “one embodiment,” “certain embodiments,” “one or more embodiments” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases such as “in one or more embodiments,” “in certain embodiments,” “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.
Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure include modifications and variations that are within the scope of the appended claims and their equivalents.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2022/020505 | 3/16/2022 | WO |
