Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size

Abstract

Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size. A novel means is presented by which any desired turbo code block size can be employed when only requiring, in only some instances, a very small number of dummy bits. This approach also is directly adaptable to parallel turbo decoding, in which any desired degree of parallelism can be employed. Alternatively, as few as one turbo decoder can be employed in a fully non-parallel implementation as well. Also, this approach allows for storage of a reduced number of parameters to accommodate a wide variety of interleaves.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a communication system.

FIG. 2 illustrates an embodiment of a turbo encoder employing selectable interleaving.

FIG. 3 illustrates another embodiment of a turbo encoder employing selectable interleaving.

FIG. 4 illustrates an embodiment of many of the various parameters associated with various interleaves.

FIG. 5 and FIG. 6 illustrate other embodiments of a communication system.

FIG. 7 illustrates an embodiment of a turbo encoding method that employs selectable interleaving.

FIG. 8, FIG. 9, FIG. 10, and FIG. 11 illustrate performance diagrams of 7 different block sized turbo codes as simulated with Rel.6 interleaves and the novel ARP interleaves provided herein.

DETAILED DESCRIPTION OF THE INVENTION

Many communication systems incorporate the use of a turbo code. When performing decoding of turbo coded signals, there are a variety of means to do so. One means of decoding turbo coded signals is to perform parallel decoding such that a number of turbo decoders are arranged in parallel. In addition, such a parallel decoding approach often involves a number of memories that are also arranged in parallel.

However, there is a challenge to ensure that there are no read and write conflicts between the various turbo decoders and the various memories when performing this parallel decoding approach. When the conflicts during memory access are avoided, then that operation is referred to as contention-free.

While there are many potential applications that can employ turbo codes, means are presented herein that can be applied to the 3GPP channel code to support an arbitrary number of information bits. Some examples of the number of bits that can be supported using the various aspects of the invention presented herein are 40 to 5114 for WCDMA and HSDPA and more for LTE.

Additional information regarding the UTRA-UTRAN Long Term Evolution (LTE) and 3GPP System Architecture Evolution (SAE) can be found at the following Internet web site:

www.3gpp.org

Within the channel coding system in 3GPP LTE, there is a need and desire to supply and provide for a wide range of block sizes (i.e., turbo code block lengths). Furthermore, turbo decoding of this system generally needs to be implemented using a parallel decoding arrangement because of the very high data throughput and large block size desired. The parallel decoding requires the contention-free memory accessing (i.e., any one turbo decoder (of a group of parallel arranged turbo decoders) accesses only memory (of a group of parallel arranged memories) at any given time). Turbo coding was suggested for 3GPP LTE channel coding. For this coding system, the algebraic interleave referred to as the “almost regular permutation (ARP)” in reference [1] is considered as one of the candidates.

Within the context of channel coding systems in 3GPP LTE, the 3GPP Rel.6 employs turbo code interleaves that need 500 different interleaves. In addition, the prior art approach to comporting with Rel.6 has generally been to dedicate hardware to implement all of these different interleaves. This has proven to be very space consuming and cost inefficient. Moreover, in order to carry on parallel turbo decoding, the prior art approaches generally employ many dummy bits that are necessarily required when using the above mentioned interleaves according to the prior art approaches. By employing so many different interleaves in these approaches, there is necessarily a requirement for more hardware and memory.

The goal of digital communications systems is to transmit digital data from one location, or subsystem, to another either error free or with an acceptably low error rate. As shown in FIG. 1, data may be transmitted over a variety of communications channels in a wide variety of communication systems: magnetic media, wired, wireless, fiber, copper, and other types of media as well.

A novel approach is presented herein by which significantly reduced complexity ARP (almost regular permutation) interleaves are employed. In some embodiments, as few as 4 different interleaves can be employed while still accommodating all possible block sizes of turbo codes. Some of these benefits of this novel approach include significant reduction in hardware and complexity that is provided by employing a straightforward multiplication/scaling (i.e., with respect to the variable number P in normal ARP interleaves) becomes, and the storage of the interleave parameters is inherently very small. For example, instead of about 108 parameter required to be stored for Rel.6 interleaves as cited in reference [2], only 52 parameters are required using the novel approach presented herein. Moreover, the approach presented herein is much easier to implement, in that, a closed formula solution is provided for the interleaves, and this is much easier to implement than the approach presented by the Rel.6 interleaves.

In addition, this novel approach provides for flexible granularity with respect to the information block size that can be generated. The novel interleaves presented herein are suitable for all possible block size, and in only some instances is there any need at all to add a very small number of dummy bits. Many instances require no dummy bits at all. This is especially useful for parallel decoding since the pruning technique suggested in Rel.6 is not suitable for parallel decoding.

The performance of the interleaves presented herein are also better than or almost equal to those of Rel.6 interleaves (i.e., see at least FIGS. 8, 9, and 10 for some comparisons).

FIG. 1 is a diagram illustrating an embodiment of a communication system 100.

Referring to FIG. 1, this embodiment of a communication system 100 is a communication channel 199 that communicatively couples a communication device 110 (including a transmitter 112 having an encoder 114 and including a receiver 116 having a decoder 118) situated at one end of the communication channel 199 to another communication device 120 (including a transmitter 126 having an encoder 128 and including a receiver 122 having a decoder 124) at the other end of the communication channel 199. In some embodiments, either of the communication devices 110 and 120 may only include a transmitter or a receiver. There are several different types of media by which the communication channel 199 may be implemented (e.g., a satellite communication channel 130 using satellite dishes 132 and 134, a wireless communication channel 140 using towers 142 and 144 and/or local antennae 152 and 154, a wired communication channel 150, and/or a fiber-optic communication channel 160 using electrical to optical (E/O) interface 162 and optical to electrical (O/E) interface 164)). In addition, more than one type of media may be implemented and interfaced together thereby forming the communication channel 199.

Many of the embodiments presented herein employ various embodiments of the ARP (almost regular permutation) interleaves. An ARP (almost regular permutation) of information block size L=CW (i.e. C is a divider of L) introduced in reference [1] is defined by

i=π(j)=jP+θ+A(j mod C)P+B(j mod C)mod L

where P is relative prime to L, θ is a constant and A(x) and B(x) are integer function defined on {0,1, . . . ,C−1}. To insure the function defined the function is a permutation (i.e. one to one and on to), in [1] A(x) and B(x) are further restricted to

A(i)P+B(i)=C[α(i)P+β(i)], i=0, . . . , C−1

where α and β are integer functions. In this document, we call C the dithering cycle of the ARP.

Some problems with respect to parallel decoding of turbo codes is generated by the prior art approaches to perform the interleaving for the Rel. 6. In order to carry on degree m parallel decoding, a contention-free memory map, which maps the values output from the m parallel processors to the different memory banks, is needed. On the other hand, 3GPP LTE turbo coding has to support any block size from 40 up to 8192 or more. With the number of interleaves (about 500 interleaves in 3GPP TS 25.212 (V6.8.0, called Rel.6) [2]), the pruning technique is introduced which involves adding what is typically a significant number of dummy bits to the information block when the information block does not correspond to a given interleave size; these dummy bits are then pruned away from the output of the interleaved data block. However, this pruning technique causes problems on the contention-free map since the map is defined on the original (i.e., pre-pruned) interleave size. Therefore, pruning technique may be too difficult to implement efficiently. That means the dummy bits have to be sent to and launching into the communication channel. However, if the interleave is not chosen carefully, then the adding of dummy bits may cause a significant rate loss. For example, using Rel.6 interleave for a block size 2304 (listed in the simulation blocks for [3]) 216 (i.e., 9.3% of the total information block size) dummy bits need to be added.

FIG. 2 illustrates an embodiment of a turbo encoder 200 employing selectable interleaving. An information block 201, which includes at least one information bit, is provided to a dummy bit module 205. The dummy bit module 205 is operable to add a small number of dummy bits to the information block 201 based on a size of the information block 201. There are many embodiments that require no adding of any dummy bits whatsoever to the information block 201. The information block 201, which is then output from the dummy bit module 205 after any dummy bits have been selectively added thereto, is simultaneously provided to a top path and a bottom path. The top path includes a first constituent encoder 210, and the bottom path includes a selectable interleaver (π) 230 communicatively coupled to a second constituent encoder 220. A variety of interleaves may be performed as selected for the particular application within the selectable interleaver (π) 230. The selectable interleaver (π) 230 can include any number of interleaves, as shown by a first interleave (π1) 231, a second interleave (π2) 232, a third interleave (π3) 233, a fourth interleave (π4) 234, and up to an nth interleave (πn) 239. The outputs from the top and bottom paths are alternatively selected to form an encoded block 299.

It is noted that the number of interleaves within the selectable interleaver (π) 230 can be any desired number, and in some embodiments, the number of interleaves within the selectable interleaver (π) 230 includes 10 or fewer interleaves. The turbo encoder 200 is operable to encode any information block whose size is within a predetermined range (e.g., between block size “a” and block size “b”, where “a” and “b” are integer values and upper and lower bounds of the predetermined range, respectively. The predetermined range is divided into a plurality of regions such that each region of the plurality of regions (e.g., k regions) corresponds to one interleave of the plurality of interleaves. In other words, a first region employs a first interleave of the plurality of interleaves; a second region employs a second interleave of the plurality of interleaves. There is a one-to-one correspondence between each region and only one corresponding interleave of the plurality of interleaves.

FIG. 3 illustrates another embodiment of a turbo encoder 300 employing selectable interleaving. This embodiment is somewhat analogous to the previous embodiment. An information block 301, which includes at least one information bit, is provided to a dummy bit module 305. The dummy bit module 305 is operable to add a small number of dummy bits to the information block 301 based on a size of the information block 301. There are many embodiments that require no adding of any dummy bits whatsoever to the information block 301. The information block 301, which is then output from the dummy bit module 305 after any dummy bits have been selectively added thereto, is simultaneously provided to a top path and a bottom path. The top path includes a first constituent encoder 310, and the bottom path includes a selectable interleaver (π) 330 communicatively coupled to a second constituent encoder 320. A variety of interleaves may be performed as selected for the particular application within the selectable interleaver (π) 330. The selectable interleaver (π) 330 can include any number of interleaves, as shown by a first interleave (π1) 331, a second interleave (π2) 332, a third interleave (π3) 333, a fourth interleave (π4) 334, and up to an nth interleave (πn) 339. In some embodiments, only 4 interleaves are employed.

The outputs from the top (shown as T) and bottom (shown as B) paths are provided to a multiplexor (MUX) 340, whose selection is provided by a clock signal that is clocked at ½ the rate at which the input bits of the information block 301 are provided to the top and bottom paths. This way, the output of the MUX 340 alternatively selects the outputs from the top (shown as T) and bottom (shown as B) paths.

In some embodiment, these output encoded bits are then provided to a puncturing module 350. In certain embodiments, no puncturing is performed on the bits output from the MUX 340; they are all simply passed as output from the MUX 340. However, in other embodiments, puncturing is selectively performed to effectuate any number of criteria, including accommodating a particular code rate, a particular modulation type, among other considerations. A variety of encoded symbols 360 may then be then generated according to the outputs from the top and bottom paths; the bottom path being an interleaved path (i.e., as performed by one of the interleaves of the selectable interleaver (π) 330). It is noted that the selectable interleaver (π) 330 can also be implemented to change its operation as a function of time; for example, the selectable interleaver (π) 330 can employ the first interleave (π1) 331 during a first time or when encoding a first information block, and the selectable interleaver (π) 330 can employ the second interleave (π2) 332 during a second time, and so on.

These encoded symbols 360 of the encoded block may then be passed to a symbol mapper where the symbols are mapped according to the appropriate modulation (constellation and mapping).

It is noted that the selectable interleaver (π) 330 within the FIG. 2 may be implemented such that it operates to correspond the order of the input bits of the information block 301 with the order in which the encoded symbols 360 are output from this embodiment of turbo encoder. That is to say, the first output, encoded symbol corresponds to the first group of input bits (or first input symbol); the second output, encoded symbol corresponds to the second group of input bits (or second input symbol). Alternatively, the selectable interleaver (π) 330 may be implemented such that corresponding the order of the input bits (or symbols) need not necessarily correspond to the output order of the encoded symbols to the input order of the groups of input bits (or input symbols).

As with the previous embodiment, it is noted that the number of interleaves within the selectable interleaver (π) 330 can be any desired number, and in some embodiments, the number of interleaves within the selectable interleaver (π) 330 includes 10 or fewer interleaves. The turbo encoder 200 is operable to encode any information block whose size is within a predetermined range (e.g., between block size “a” and block size “b”, where “a” and “b” are integer values and upper and lower bounds of the predetermined range, respectively. The predetermined range is divided into a plurality of regions such that each region of the plurality of regions (e.g., k regions) corresponds to one interleave of the plurality of interleaves. In other words, a first region employs a first interleave of the plurality of interleaves; a second region employs a second interleave of the plurality of interleaves. There is a one-to-one correspondence between each region and only one corresponding interleave of the plurality of interleaves.

FIG. 4 illustrates an embodiment 400 of many of the various parameters associated with various interleaves. As shown above within various embodiments, a selectable interleaver (π) that is operable to employ any one of a plurality of interleaves (π1, π2, π3, etc.). Depending on the particular interleave (π) employed, various operational parameters of the turbo encoder are governed.

For example, depending on the information block size desired to be turbo encoded, an appropriate interleave (π) is selected and employed. In addition, based on the interleave (π) that is selected and employed, other operational parameters are then selected as well.

Looking at this embodiment 400, a first interleave (π1) 410 is operable to assist in the turbo encoding of block sizes from L1 to L2, as shown by reference numeral 411. A dithering cycle of C1, as shown by reference numeral 412, is also associated with the first interleave (π1) 410. The size of the first interleave (π1) is N1, as shown by reference numeral 413. The ARP itself that is employed for the first interleave (π1) 410 employs certain periodic function pairs (α1, β1) and offset (θ1), as shown by reference numeral 414. The first interleave (π1) 410 also provides a particular parallel degree (pd1) as shown by reference numeral 415. Also, the first interleave (π1) 410 will add, at most, a maximal number of dummy bits, as shown by reference numeral 416, which is a function of the information block size being turbo encoded. Each of a second interleave (π2) 420, a third interleave (π3) 430, and up to an nth interleave (πn) can also be associated with and govern similar operational parameters.

In one embodiment, a set of 4 base ARP interleaves are employed by a selectable interleaver (π) to enable turbo encoding of any possible block size from 40 to 8192 bits. In using these 4 base ARP interleaves (π), the value of P is chosen to be a fixed prime, i.e. 1021. In this way, the multiply P operation in the ARP interleaving becomes a mere scaling, which saves hardware area and power.

Only 4 different dithering cycles, C, and 4 different periodic function pairs (α(x), β(x)) are used. These are provided as follows:

1. Block size 40˜R₁: C=2 and using (α₂(x), β₂(x));

2. Block size R₁+1˜R₂: C=4 and using (α₄(x), β₄(x));

3. Block size R₂+1˜R₃: C=8 and using (α₈(x), β₈(x)); and

4. Block size R₃+1˜8192: C=10 and using (α₁₀(x), β₁₀(x).

In one embodiment, the values of R₁=100, R₂=1500, and R₃=5000 are chosen. Other values may be employed based on design choice.

In general, given any information block (i.e., input bits arranged into an information block) of block size L, one can find its corresponding region among the set of 4 base ARP interleaves (i.e., interleave (π1), interleave (π2), interleave (π3), or interleave (π4)) and its dithering cycle C.

The ARP interleaves, the largest number of the dummy bits which may need to be added, and the possible parallel degrees are listed in the following table (where [ ] is the ceiling function, i.e., the ratio rounded up the nearest integer).

					maximal
		Interleave			dummy
Block size L	C	size N	ARP	Parallel degree	bits
40~R1	2	2 * [L/2]	{1021 * x + θ2 + 2 * [α2(x mod	1, 2 (and 3, . . ., 2v	1
			2) * 1021 + β2(x mod 2)]}mod N	if 2v|N, v > 1)
R1 + 1~R2	4	4 * [L/4]	{1021 * x + θ4 + 4 * [α4(x mod	1, 2, 3, 4 (and	3
			4) * 1021 + β4(x mod 4)]} mod N	5, . . ., 4v if
				4v|N, v > 1)
R2 + 1~R3	8	8 * [L/8]	{1021 * x + θ8 + 8 * [α8(x mod	1, 2, 3, 4, 5, 6, 7, 8	7
			8) * 1021 + β8(x mod 8)]} mod N	(and 9, . . ., 8v if
				8v|N, v > 1)
R3 + 1~8192	10	10 * [L/10]	{1021 * x + θ10 + 10 * [α10(x mod	1, 2, 3, 4, 5, 6, 7, 8,	9
			10) * 1021 + β10(x mod 10)]}	9, 10 (and 11, . . .,
			mod N	10v if
				10v|N, v > 1)

One embodiment of the interleave parameters (which can be modified or changed based on design choice) are given in the following table.

			Interleave	αC(0), αC(1), . . .,
L	C	θ	size N	αC(C − 1),	βC(0), βC(1), . . ., βC(C − 1),
40~100	2	0	2 * [L/2]	1, 1	18, 17
101~1500	4	7	4 * [L/4]	0, 1, 0, 1	246, 149, 210, 9
1501~5000	8	0	8 * [L/8]	1, 1, 0, 1, 0, 0, 0, 0	327, 222, 159, 168, 54, 376, 204, 465
5000~8192	10	0	10 * [L/10]	1, 1, 1, 0, 1, 0, 1,	360, 278, 127, 486, 322, 4, 325, 273, 288, 206
				0, 1, 0

FIG. 5 and FIG. 6 illustrate other embodiments of a communication system.

Referring to the communication system 500 of FIG. 5, the communication system 500 includes a communication device 510 that is coupled to another device 590 via a communication channel 599. The communication device 510 includes an encoder 520 that includes a processing module 530 and a memory 540, module and/or device capable to store a plurality of interleaves, any one of which can be selected and employed by the turbo encoder 520 for us in performing turbo encoding.

The other communication device 590 to which the communication device 510 is coupled via the communication channel 599 can be a wireless communication device 592, wireless communication device 594, a storage media 594 (e.g., such as within the context of a hard disk drive (HDD)), or any other type of device that is capable to receive and/or transmit signals. In some embodiments, the communication channel 599 is a bi-directional communication channel that is operable to perform transmission of a first signal during a first time and receiving of a second signal during a second time. If desired, full duplex communication may also be employed, in which each of the communication device 510 and the device 590 can be transmitted and/or receiving from one another simultaneously.

The communication device 510 includes the turbo decoder 520, a processing module 530, and the memory 540. The processing module 530 can be coupled to the memory 540 so that the memory is operable to store operational instructions that enable to the processing module 530 to perform certain functions.

Generally speaking, the processing module 530 is operable to perform providing to and selection of an appropriate interleave for use by the turbo encoder 520 when encoding an information block.

It is also noted that the processing module 530 can be implemented strictly as circuitry. Alternatively, the processing module 530 can be implemented strictly in software such as can be employed within a digital signal processor (DSP) or similar type device. In even another embodiment, the processing module 530 can be implemented as a combination of hardware and software as well without departing from the scope and spirit of the invention.

In even other embodiments, the processing module 530 can be implemented using a shared processing device, individual processing devices, or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on operational instructions. The processing module 530 can be coupled to the memory 540 that is operable to store operational instructions that enable to processing module 530 to perform the appropriate contention-free memory mapping between the turbo decoder 520 and the memory 540.

Such a memory 540 may be a single memory device or a plurality of memory devices. Such a memory 540 may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that stores digital information. Note that when the processing module 530 implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory storing the corresponding operational instructions is embedded with the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry.

Referring to the communication system 600 of FIG. 6, this embodiment is somewhat analogous to the previous embodiment. The communication system 600 includes a communication device 610 that can be coupled to another device via a communication channel 699. The communication device 610 includes a turbo decoder 620 that is itself composed of a plurality of turbo decoders 621-622. The communication device 610 also includes a memory 640 that is itself composed of a plurality of memories 641-642. A processing module 630 is operable to appropriate memory management during iterative decoding processing of a turbo coded signal that is received via the communication channel 699. In one embodiment, the processing module 630 is operable to perform contention-free memory mapping between the plurality of turbo decoders 621-622 and the plurality of memories 641-642 in some embodiments during iterative decoding processing of a turbo coded signal that is received via the communication channel 699.

FIG. 7 illustrates an embodiment of a turbo encoding method 700 that employs selectable interleaving. As shown in a block 710, the method 700 involves selectively adding dummy bits, if needed, to an information block based on information block size. Then, as shown in a block 720, the method 700 involves turbo encoding information block (including any added dummy bits) employing selectable interleaving that is selected based on the information block size. If desired in some embodiments, the method 700 involves selecting the selectable interleaving from a plurality of ARP (almost regular permutation) interleaves, as shown in a block 722.

The method continues, as shown in a block 730, by performing turbo encoding information block (including any added dummy bits) employing selectable interleaving that is selected based on the information block size thereby generating an encoded block.

In some embodiments, the method 700 can also include turbo decoding the encoded block, as shown in a block 740. This turbo decoding can be performed using parallel decoding processing, as shown in a block 742 if desired.

FIG. 8, FIG. 9, FIG. 10, and FIG. 11 illustrate performance diagrams of 7 different block sized turbo codes as simulated with Rel.6 interleaves and the novel ARP interleaves provided herein. The code rate is ⅓ and the communication channel is an Additive White Gaussian Noise (AWGN) communication channel.

Referring to diagram 800 of FIG. 8, performance of a turbo code employing a block size L=99 and a proposed, novel ARP having a dithering cycle C=2 is compared to performance of a turbo code employing a block size L=99 according the conventions of Rel.6. Also, performance of a turbo code employing a block size L=52 and a proposed, novel ARP having a dithering cycle C=2 is compared to performance of a turbo code employing a block size L=52 according the conventions of Rel.6.

Referring to diagram 900 of FIG. 9, performance of a turbo code employing a block size L=902 and a proposed, novel ARP having a dithering cycle C=4 is compared to performance of a turbo code employing a block size L=902 according the conventions of Rel.6. Also, performance of a turbo code employing a block size L=319 and a proposed, novel ARP having a dithering cycle C=4 is compared to performance of a turbo code employing a block size L=319 according the conventions of Rel.6.

Referring to diagram 1000 of FIG. 10, performance of a turbo code employing a block size L=3760 and a proposed, novel ARP having a dithering cycle C=8 is compared to performance of a turbo code employing a block size L=3760 according the conventions of Rel.6. Also, performance of a turbo code employing a block size L=1965 and a proposed, novel ARP having a dithering cycle C=8 is compared to performance of a turbo code employing a block size L=1965 according the conventions of Rel.6.

Referring to diagram 1100 of FIG. 11, performance of a turbo code employing a block size L=6144 and a proposed, novel ARP having a dithering cycle C=10 is shown.

The present invention has also been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claimed invention.

The present invention has been described above with the aid of functional building blocks illustrating the performance of certain significant functions. The boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality. To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claimed invention.

One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.

Moreover, although described in detail for purposes of clarity and understanding by way of the aforementioned embodiments, the present invention is not limited to such embodiments. It will be obvious to one of average skill in the art that various changes and modifications may be practiced within the spirit and scope of the invention, as limited only by the scope of the appended claims.

REFERENCES

[1] C. Berrou, Y. Saouter, C. Douillard, S. Kerouédan, and M. Jézéquel, “Designing good permutations for turbo codes: towards a single model,” 2004 IEEE International Conference on Communications (ICC), Vol.: 1, pp: 341-345, 20-24 Jun. 2004.

[2] 3GPP TS 25.212 V6.8.0 (2006-06).

[3] Proposed way forward on turbo interleaver (tc_info_sizes_test_mot_nov14.txt), 3GPP TSG RAN WG1 #47 R1-063564.

Claims

1. A turbo encoder having selectable ARP (almost regular permutation) interleaving, the turbo encoder comprising: a first constituent encoder that is operable to encode an information block thereby generating a first encoded plurality of bits;a selectable ARP interleaver that is operable to employ one selected ARP interleave of a plurality of ARP interleaves to interleave the information block, wherein the one selected ARP interleave is selected based on a size of the information block; anda second constituent encoder that is operable to encode the interleaved information block thereby generating a second encoded plurality of bits; and wherein:bits that are alternatively selected from the first encoded plurality of bits and the second encoded plurality of bits form an encoded block;the plurality of ARP interleaves includes 10 or fewer ARP interleaves;the turbo encoder is operable to encode any information block whose size is within a predetermined range having a first information block size as a lower bound of the predetermined range and a second information block size as an upper bound of the predetermined range; andthe predetermined range is divided into a plurality of regions such that each region of the plurality of regions corresponds to one ARP interleave of the plurality of ARP interleaves.

2. The turbo encoder of claim 1, wherein: the selectable ARP interleaver is operable to generate the one selected ARP interleave of the plurality of ARP interleaves in real time using a closed formula solution.

3. The turbo encoder of claim 1, wherein: the plurality of interleaves includes no more than 4 interleaves; andthe information block includes any number of bits between 40 and 8192, inclusive.

4. The turbo encoder of claim 1, further comprising: a dummy bit module that is selectively operable to modify the information block by adding a dummy bit to the information block based on the size of the information block.

5. The turbo encoder of claim 1, further comprising: a dummy bit module that is selectively operable to modify the information block by adding a dummy bit to the information block based on the size of the information block; and wherein:a number of dummy bits that are added to the information block is one less than a dithering cycle of the one selected ARP interleave of the plurality of ARP interleaves.

6. The turbo encoder of claim 1, wherein: each ARP interleave of the plurality of ARP interleaves can be generated using a same scalar coefficient, P, that is relative prime to the information block, L, such that ARP interleave is defined as follows: i=π(j)=jP+θ+A(j mod C)P+B(j mod C)mod L; θ is a constant value;A(x) and B(x) are integer function defined on {0,1, . . . ,C −1}; andC is a divider of L.

7. The turbo encoder of claim 1, further comprising: a turbo decoder, that includes a plurality of parallel arranged turbo decoders, that is operable to decode the encoded block; and wherein:based on the size of the information block, the turbo decoder employs a selected number of turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block.

8. The turbo encoder of claim 1, further comprising: a turbo decoder, that includes a plurality of parallel arranged turbo decoders, that is operable to decode the encoded block; and wherein:when the information block includes any number of bits between 40 and 100, inclusive, the turbo decoder employs no more than 2 turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block;when the information block includes any number of bits between 101 and 1500, inclusive, the turbo decoder employs no more than 4 turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block;when the information block includes any number of bits between 1501 and 5000, inclusive, the turbo decoder employs no more than 8 turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block; andwhen the information block includes any number of bits between 5001 and 8192, inclusive, the turbo decoder employs no more than 10 turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block.

9. The turbo encoder of claim 1, wherein: the turbo encoder is implemented within a wireless personal communication device.

10. The turbo encoder of claim 1, wherein: the turbo encoder is implemented within a communication device; andthe communication device is implemented within a wireless communication system.

11. A turbo encoder having selectable ARP (almost regular permutation) interleaving, the turbo encoder comprising: a dummy bit module that is selectively operable to modify an information block by adding a dummy bit to the information block based on the size of the information block thereby generating a modified information block;a first constituent encoder that is operable to encode the modified information block thereby generating a first encoded plurality of bits;a selectable ARP interleaver that is operable to: select one ARP interleave from a plurality of ARP interleaves based on a size of the information block;generate the one selected ARP interleave of the plurality of ARP interleaves in real time using a closed formula solution; andemploy the one selected ARP interleave of a plurality of ARP interleaves to interleave the modified information block; anda second constituent encoder that is operable to encode the interleaved, modified information block thereby generating a second encoded plurality of bits; and wherein:bits that are alternatively selected from the first encoded plurality of bits and the second encoded plurality of bits form an encoded block;the plurality of ARP interleaves includes 10 or fewer ARP interleaves;the turbo encoder is operable to encode any information block whose size is within a predetermined range having a first information block size as a lower bound of the predetermined range and a second information block size as an upper bound of the predetermined range; andthe predetermined range is divided into a plurality of regions such that each region of the plurality of regions corresponds to one ARP interleave of the plurality of ARP interleaves.

12. The turbo encoder of claim 11, wherein: a number of dummy bits that are added to the information block is one less than a dithering cycle of the one selected ARP interleave of the plurality of ARP interleaves.

13. The turbo encoder of claim 11, wherein: each ARP interleave of the plurality of ARP interleaves can be generated using a same scalar coefficient, P, that is relative prime to the information block, L, such that ARP interleave is defined as follows: i=π(j)=jP+θ+A(j mod C)P+B(j mod C)mod L; θ is a constant value;A(x) and B(x) are integer function defined on {0,1, . . . ,C−1}; andC is a divider of L.

14. The turbo encoder of claim 11, wherein: the information block includes 8192 or fewer bits; andno more than 9 dummy bits are added to the information block.

15. The turbo encoder of claim 11, further comprising: a turbo decoder, that includes a plurality of parallel arranged turbo decoders, that is operable to decode the encoded block; and wherein:based on the size of the information block, the turbo decoder employs a selected number of turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block.

16. The turbo encoder of claim 11, further comprising: a turbo decoder, that includes a plurality of parallel arranged turbo decoders, that is operable to decode the encoded block; and wherein:when the information block includes any number of bits between 40 and 100, inclusive, the turbo decoder employs no more than 2 turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block;when the information block includes any number of bits between 101 and 1500, inclusive, the turbo decoder employs no more than 4 turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block;when the information block includes any number of bits between 1501 and 5000, inclusive, the turbo decoder employs no more than 8 turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block; andwhen the information block includes any number of bits between 5001 and 8192, inclusive, the turbo decoder employs no more than 10 turbo decoders from the plurality of parallel arranged turbo decoders to decode the encoded block.

17. The turbo encoder of claim 11, wherein: the turbo encoder is implemented within a communication device; andthe communication device is implemented within a wireless communication system.

18. A method for turbo encoding at least one information bit using selectable ARP (almost regular permutation) interleaving, the method comprising: selectively modifying an information block by adding a dummy bit to the information block based on the size of the information block thereby generating a modified information block;employing a first constituent encoder to encode the modified information block thereby generating a first encoded plurality of bits;selecting one ARP interleave of a plurality of ARP interleaves based on a size of the information block, wherein the plurality of ARP interleaves includes 10 or fewer ARP interleaves;interleaving the modified information block using the one selected ARP interleave of the plurality of ARP interleaves;employing a second constituent encoder to encode the interleaved, modified information block thereby generating a second encoded plurality of bits; andalternatively selecting bits from the first encoded plurality of bits and the second encoded plurality of bits to form an encoded block; and wherein:the method is operable to encode any information block whose size is within a predetermined range having a first information block size as a lower bound of the predetermined range and a second information block size as an upper bound of the predetermined range; andthe predetermined range is divided into a plurality of regions such that each region of the plurality of regions corresponds to one ARP interleave of the plurality of ARP interleaves.

19. The method of claim 18, further comprising: modifying the encoded block to a form that comports with a communication channel of the wireless communication system; andafter the turbo coded block has undergone any appropriate modification to comport with the communication channel, launching the modified encoded block into the communication channel from the communication device.

20. The method of claim 18, wherein: the method is performed within a turbo encoder;the turbo encoder is implemented within a communication device;the communication device is implemented within a wireless communication system;the communication device is operable to modify the encoded block to a form that comports with a communication channel of the wireless communication system; andafter undergoing any appropriate modification to comport with the communication channel, the modified encoded block is launched into the communication channel from the communication device.