Patent Grant
8065587
1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to communication systems employing turbo coding.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that has been of significant interest lately is a communication system that employs iterative error correction codes. One type of communication system that has received interest in recent years has been one which employs turbo codes (one type of iterative error correcting code). Communications systems with iterative codes are often able to achieve lower bit error rates (BER) than alternative codes for a given signal to noise ratio (SNR).
A continual and primary directive in this area of development has been to try continually to lower the SNR required to achieve a given BER within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular SNR, that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.
The use of turbo codes providing such relatively lower error rates, while operating at relatively low data throughput rates, has largely been in the context of communication systems having a large degree of noise within the communication channel and where substantially error free communication is held at the highest premium. Some of the earliest application arenas for turbo coding were space related where accurate (i.e., ideally error free) communication is often deemed an essential design criterion. The direction of development then moved towards developing terrestrial-applicable and consumer-related applications. Still, based on the heritage of space related application, the focus of effort in the turbo coding environment then continued to be achieving relatively lower error floors, and not specifically towards reaching higher throughput.
More recently, focus in the art has been towards developing turbo coding, and variants thereof, that are operable to support higher amounts of throughput while still preserving the relatively low error floors offered within the turbo code context.
In fact, as the throughput requirement in communication systems increases, parallel turbo decoding, which employs a plurality of processors and a plurality of memory banks, become necessary. Many of the current systems support a wide range of codeword sizes. Thus, efficiency and flexibility in parallel turbo decoder design is of critical importance.
Generally speaking, within the context of communication systems that employ turbo codes, there is a first communication device at one end of a communication channel with encoder capability and second communication device at the other end of the communication channel with decoder capability. In many instances, one or both of these two communication devices includes encoder and decoder capability (e.g., within a bi-directional communication system).
The present invention is directed to apparatus and methods of operation that are further described in the following Brief Description of the Several Views of the Drawings, the Detailed Description of the Invention, and the claims. Other features and advantages of the present invention will become apparent from the following detailed description of the invention made with reference to the accompanying drawings.
Many communication systems incorporate the use of a turbo code. When performing decoding of turbo coded signals, there are a variety of means to do so. One means of decoding turbo coded signals is to perform parallel decoding such that a number of turbo decoders are arranged in parallel. In addition, such a parallel decoding approach often involves a number of memories that are also arranged in parallel.
However, there is a challenge to ensure that there are no read and write conflicts between the various turbo decoders and the various memories when performing this parallel decoding approach. When the conflicts during memory access are avoided, then that operation is referred to as contention-free.
While there are many potential applications that can employ turbo codes, means are presented herein that can be applied to the 3GPP channel code to support an arbitrary number of information bits. Some examples of the number of bits that can be supported using the various aspects of the invention presented herein are 40 to 5114 for WCDMA and HSDPA and more for LTE.
Additional information regarding the UTRA-UTRAN Long Term Evolution (LTE) and 3GPP System Architecture Evolution (SAE) can be found at the following Internet web site:
www.3gpp.org
Within the channel coding system in 3GPP LTE, there is a need and desire to supply and provide for a wide range of block sizes (i.e., turbo code block lengths). Furthermore, turbo decoding of this system generally needs to be implemented using a parallel decoding arrangement because of the very high data throughput and large block size desired. The parallel decoding requires the contention-free memory accessing (i.e., any one turbo decoder (of a group of parallel arranged turbo decoders) accesses only memory (of a group of parallel arranged memories) at any given time). Turbo coding was suggested for 3GPP LTE channel coding. For this coding system, the algebraic interleave referred to as the “almost regular permutation (ARP)” in reference [1] is considered as one of the candidates.
Within the context of channel coding systems in 3GPP LTE, the 3GPP Rel.6 employs turbo code interleaves that need 500 different interleaves. In addition, the prior art approach to comporting with Rel.6 has generally been to dedicate hardware to implement all of these different interleaves. This has proven to be very space consuming and cost inefficient. Moreover, in order to carry on parallel turbo decoding, the prior art approaches generally employ many dummy bits that are necessarily required when using the above mentioned interleaves according to the prior art approaches. By employing so many different interleaves in these approaches, there is necessarily a requirement for more hardware and memory.
The goal of digital communications systems is to transmit digital data from one location, or subsystem, to another either error free or with an acceptably low error rate. As shown in
A novel approach is presented herein by which significantly reduced complexity ARP (almost regular permutation) interleaves are employed. In some embodiments, as few as 4 different interleaves can be employed while still accommodating all possible block sizes of turbo codes. Some of these benefits of this novel approach include significant reduction in hardware and complexity that is provided by employing a straightforward multiplication/scaling (i.e., with respect to the variable number P in normal ARP interleaves) becomes, and the storage of the interleave parameters is inherently very small. For example, instead of about 108 parameters required to be stored for Rel.6 interleaves as cited in reference, [2], only 52 parameters are required using the novel approach presented herein. Moreover, the approach presented herein is much easier to implement, in that, a closed formula solution is provided for the interleaves, and this is much easier to implement than the approach presented by the Rel.6 interleaves.
In addition, this novel approach provides for flexible granularity with respect to the information block size that can be generated. The novel interleaves presented herein are suitable for all possible block size, and in only some instances is there any need at all to add a very small number of dummy bits. Many instances require no dummy bits at all. This is especially useful for parallel decoding since the pruning technique suggested in Rel.6 is not suitable for parallel decoding.
The performance of the interleaves presented herein are also better than or almost equal to those of Rel.6 interleaves (i.e., see at least
Referring to
Many of the embodiments presented herein employ various embodiments of the ARP (almost regular permutation) interleaves. An ARP (almost regular permutation) of information block size L=CW (i.e. C is a divider of L) introduced in reference [1] is defined by
i=π(j)=jP+θ+A(j mod C)P+B(j mod C)mod L
where P is relative prime to L, θ is a constant and A(x) and B(x) are integer function defined on {0,1, . . . ,C−1}. To insure the function defined the function is a permutation (i.e. one to one and on to), in [1] A(x) and B(x) are further restricted to
A(i)P+B(i)=C[α(i)P+β(i)], i=0, . . . , C−1
where α and β are integer functions. In this document, we call C the dithering cycle of the ARP.
Some problems with respect to parallel decoding of turbo codes is generated by the prior art approaches to perform the interleaving for the Rel. 6. In order to carry on degree m parallel decoding, a contention-free memory map, which maps the values output from the m parallel processors to the different memory banks, is needed. On the other hand, 3GPP LTE turbo coding has to support any block size from 40 up to 8192 or more. With the number of interleaves (about 500 interleaves in 3GPP TS 25.212 (V6.8.0, called Rel.6) [2]), the pruning technique is introduced which involves adding what is typically a significant number of dummy bits to the information block when the information block does not correspond to a given interleave size; these dummy bits are then pruned away from the output of the interleaved data block. However, this pruning technique causes problems on the contention-free map since the map is defined on the original (i.e., pre-pruned) interleave size. Therefore, pruning technique may be too difficult to implement efficiently. That means the dummy bits have to be sent to and launching into the communication channel. However, if the interleave is not chosen carefully, then the adding of dummy bits may cause a significant rate loss. For example, using Rel.6 interleave for a block size 2304 (listed in the simulation blocks for [3]) 216 (i.e., 9.3% of the total information block size) dummy bits need to be added.
It is noted that the number of interleaves within the selectable interleaver (π) 230 can be any desired number, and in some embodiments, the number of interleaves within the selectable interleaver (π) 230 includes 10 or fewer interleaves. The turbo encoder 200 is operable to encode any information block whose size is within a predetermined range (e.g., between block size “a” and block size “b”, where “a” and “b” are integer values and upper and lower bounds of the predetermined range, respectively. The predetermined range is divided into a plurality of regions such that each region of the plurality of regions (e.g., k regions) corresponds to one interleave of the plurality of interleaves. In other words, a first region employs a first interleave of the plurality of interleaves; a second region employs a second interleave of the plurality of interleaves. There is a one-to-one correspondence between each region and only one corresponding interleave of the plurality of interleaves.
The outputs from the top (shown as T) and bottom (shown as B) paths are provided to a multiplexor (MUX) 340, whose selection is provided by a clock signal that is clocked at ½ the rate at which the input bits of the information block 301 are provided to the top and bottom paths. This way, the output of the MUX 340 alternatively selects the outputs from the top (shown as T) and bottom (shown as B) paths.
In some embodiment, these output encoded bits are then provided to a puncturing module 350. In certain embodiments, no puncturing is performed on the bits output from the MUX 340; they are all simply passed as output from the MUX 340. However, in other embodiments, puncturing is selectively performed to effectuate any number of criteria, including accommodating a particular code rate, a particular modulation type, among other considerations. A variety of encoded symbols 360 may then be then generated according to the outputs from the top and bottom paths; the bottom path being an interleaved path (i.e., as performed by one of the interleaves of the selectable interleaver (π) 330). It is noted that the selectable interleaver (π) 330 can also be implemented to change its operation as a function of time; for example, the selectable interleaver (π) 330 can employ the first interleave (π1) 331 during a first time or when encoding a first information block, and the selectable interleaver (π) 330 can employ the second interleave (π2) 332 during a second time, and so on.
These encoded symbols 360 of the encoded block may then be passed to a symbol mapper where the symbols are mapped according to the appropriate modulation (constellation and mapping).
It is noted that the selectable interleaver (π) 330 within the
As with the previous embodiment, it is noted that the number of interleaves within the selectable interleaver (π) 330 can be any desired number, and in some embodiments, the number of interleaves within the selectable interleaver (π) 330 includes 10 or fewer interleaves. The turbo encoder 300 is operable to encode any information block whose size is within a predetermined range (e.g., between block size “a” and block size “b”, where “a” and “b” are integer values and upper and lower bounds of the predetermined range, respectively. The predetermined range is divided into a plurality of regions such that each region of the plurality of regions (e.g., k regions) corresponds to one interleave of the plurality of interleaves. In other words, a first region employs a first interleave of the plurality of interleaves; a second region employs a second interleave of the plurality of interleaves. There is a one-to-one correspondence between each region and only one corresponding interleave of the plurality of interleaves.
For example, depending on the information block size desired to be turbo encoded, an appropriate interleave (π) is selected and employed. In addition, based on the interleave (π) that is selected and employed, other operational parameters are then selected as well.
Looking at this embodiment 400, a first interleave (π1) 410 is operable to assist in the turbo encoding of block sizes from L1 to L2, as shown by reference numeral 411. A dithering cycle of C1, as shown by reference numeral 412, is also associated with the first interleave (π1) 410. The size of the first interleave (π1) is N1, as shown by reference numeral 413. The ARP itself that is employed for the first interleave (π1) 410 employs certain periodic function pairs (α1, β1) and offset (θ1), as shown by reference numeral 414. The first interleave (π1) 410 also provides a particular parallel degree (pd1) as shown by reference numeral 415. Also, the first interleave (π1) 410 will add, at most, a maximal number of dummy bits, as shown by reference numeral 416, which is a function of the information block size being turbo encoded. Each of a second interleave (π2) 420, a third interleave (π3) 430, and up to an nth interleave (πn) can also be associated with and govern similar operational parameters.
In one embodiment, a set of 4 base ARP interleaves are employed by a selectable interleaver (π) to enable turbo encoding of any possible block size from 40 to 8192 bits. In using these 4 base ARP interleaves (π), the value of P is chosen to be a fixed prime, i.e. 1021. In this way, the multiply P operation in the ARP interleaving becomes a mere scaling, which saves hardware area and power.
Only 4 different dithering cycles, C, and 4 different periodic function pairs (α(x), β(x)) are used. These are provided as follows:
1. Block size 40˜R1: C=2 and using (α2(x), β2(x));
2. Block size R1+1˜R2: C=4 and using (α4(x), β4(x));
3. Block size R2+1˜R3: C=8 and using (α8(x), β8(x)); and
4. Block size R3+1˜8192: C=10 and using (α10(x), β10(x).
In one embodiment, the values of R1=100, R2=1500, and R3=5000 are chosen. Other values may be employed based on design choice.
In general, given any information block (i.e., input bits arranged into an information block) of block size L, one can find its corresponding region among the set of 4 base ARP interleaves (i.e., interleave (π1), interleave (π2), interleave (π3), or interleave (π4)) and its dithering cycle C.
The ARP interleaves, the largest number of the dummy bits which may need to be added, and the possible parallel degrees are listed in the following table (where [ ] is the ceiling function, i.e., the ratio rounded up the nearest integer).
One embodiment of the interleave parameters (which can be modified or changed based on design choice) are given in the following table.
Referring to the communication system 500 of
The other communication device 590 to which the communication device 510 is coupled via the communication channel 599 can be a wireless communication device 592, wireless communication device 594, a storage media 594 (e.g., such as within the context of a hard disk drive (HDD)), or any other type of device that is capable to receive and/or transmit signals. In some embodiments, the communication channel 599 is a bi-directional communication channel that is operable to perform transmission of a first signal during a first time and receiving of a second signal during a second time. If desired, full duplex communication may also be employed, in which each of the communication device 510 and the device 590 can be transmitted and/or receiving from one another simultaneously.
The communication device 510 includes the turbo decoder 520, a processing module 530, and the memory 540. The processing module 530 can be coupled to the memory 540 so that the memory is operable to store operational instructions that enable to the processing module 530 to perform certain functions.
Generally speaking, the processing module 530 is operable to perform providing to and selection of an appropriate interleave for use by the turbo encoder 520 when encoding an information block.
It is also noted that the processing module 530 can be implemented strictly as circuitry. Alternatively, the processing module 530 can be implemented strictly in software such as can be employed within a digital signal processor (DSP) or similar type device. In even another embodiment, the processing module 530 can be implemented as a combination of hardware and software as well without departing from the scope and spirit of the invention.
In even other embodiments, the processing module 530 can be implemented using a shared processing device, individual processing devices, or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on operational instructions. The processing module 530 can be coupled to the memory 540 that is operable to store operational instructions that enable to processing module 530 to perform the appropriate contention-free memory mapping between the turbo decoder 520 and the memory 540.
Such a memory 540 may be a single memory device or a plurality of memory devices. Such a memory 540 may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that stores digital information. Note that when the processing module 530 implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory storing the corresponding operational instructions is embedded with the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry.
Referring to the communication system 600 of
The method continues, as shown in a block 730, by performing turbo encoding information block (including any added dummy bits) employing selectable interleaving that is selected based on the information block size thereby generating an encoded block.
In some embodiments, the method 700 can also include turbo decoding the encoded block, as shown in a block 740. This turbo decoding can be performed using parallel decoding processing, as shown in a block 742 if desired.
Referring to diagram 800 of
Referring to diagram 900 of
Referring to diagram 1000 of
Referring to diagram 1100 of
The present invention has also been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claimed invention.
The present invention has been described above with the aid of functional building blocks illustrating the performance of certain significant functions. The boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality. To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claimed invention.
One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.
Moreover, although described in detail for purposes of clarity and understanding by way of the aforementioned embodiments, the present invention is not limited to such embodiments. It will be obvious to one of average skill in the art that various changes and modifications may be practiced within the spirit and scope of the invention, as limited only by the scope of the appended claims.
[1] C. Berrou, Y. Saouter, C. Douillard, S. Kerouédan, and M. Jézéquel, “Designing good permutations for turbo codes: towards a single model,” 2004 IEEE International Conference on Communications (ICC), Vol.: 1, pp: 341-345, 20-24 Jun. 2004.
[2] 3GPP TS 25.212 V6.8.0 (2006-06).
[3] Proposed way forward on turbo interleaver (tc_info_sizes_test_mot_nov14.txt), 3GPP TSG RAN WG1 #47 R1-063564.
The present U.S. Patent Application claims priority pursuant to 35 U.S.C. §119(e) to the following U.S. Provisional Patent Applications which are hereby incorporated herein by reference in their entirety and made part of the present U.S. Patent Application for all purposes: 1. U.S. Provisional Application Ser. No. 60/850,492, entitled “General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes,” filed Oct. 10, 2006. 2. U.S. Provisional Application Ser. No. 60/872,367, entitled “Turbo decoder employing ARP (almost regular permutation) interleave and inverse thereof as de-interleave,” filed Dec. 1, 2006. 3. U.S. Provisional Application Ser. No. 60/872,716, entitled “Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors,” filed Dec. 4, 2006. 4. U.S. Provisional Application Ser. No. 60/861,832, entitled “Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size,” filed Nov. 29, 2006. 5. U.S. Provisional Application Ser. No. 60/879,301, entitled “Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves,” filed Jan. 8, 2007. The following U.S. Patent Applications are hereby incorporated herein by reference in their entirety and made part of the present U.S. Patent Application for all purposes: 1. U.S. application Ser. No. 11/704,068, entitled “General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes,” filed Feb. 8, 2007, pending. 2. U.S. application Ser. No. 11/657,819, entitled “Turbo decoder employing ARP (almost regular permutation) interleave and inverse thereof as de-interleave,” filed Jan. 25, 2007, pending. 3. U.S. application Ser. No. 11/811,014, entitled “Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors,” filed concurrently on Jun. 7, 2007, now issued as U.S. Pat. No. 7,827,473 B2 on Nov. 2, 2010. 4. U.S. application Ser. No. 11/810,989, entitled “Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves,” filed concurrently on Jun. 7, 2007, now issued as U.S. Pat. No. 7,831,894 B2 on Nov. 9, 2010.
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| Number | Date | Country | |
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| 20080086674 A1 | Apr 2008 | US |
| Number | Date | Country | |
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| 60850492 | Oct 2006 | US | |
| 60861832 | Nov 2006 | US | |
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| 60879301 | Jan 2007 | US |
