Claims
- 1. A stacked capacitor, dynamic random access memory, (DRAM), device structure, in a P type region of a semiconductor substrate comprising:
- thick field oxide regions in semiconductor substrate;
- polysilicon gate structures, comprised of a top layer of phosphosilicate glass, containing between about 2 to 6 weight percent P.sub.2 O.sub.5, overlying a thin layer of silicon oxide, which overlies an N type, insitu doped polysilicon layer, and with said polysilicon gate structures, located between said thick field oxide regions;
- insulator spacers located on the sides of said polysilicon structures;
- N type source and drain regions, in said P type region of said semiconductor substrate, located between a thick field oxide region and a polysilicon gate structure, and an N type source and drain region located between said polysilicon gate structures;
- a stacked capacitor structure, comprised of; a storage node electrode of polysilicon, a thin dielectric layer on said storage node electrode, and a capacitor plate on said thin dielectric layer, with capacitor plate comprised of a bottom layer of amorphous silicon, with a smooth top surface topography, between about 300 to 700 Angstroms in thickness, and an overlying polysilicon layer, between about 750 to 1250 Angstroms in thickness, contacting N type source and drain region, located between said thick field oxide region and said polysilicon gate structure, and with said stacked capacitor structure overlapping said thick field oxide region, and overlapping said phosphosilicate glass layer, of said polysilicon gate structure;
- a bit line structure, comprised of an underlying polysilicon layer, and an overlying tungsten silicide layer, contacting N type source and drain region, located between polysilicon gate structures;
- a N type region of said semiconductor substrate, separated from said P type region of said semiconductor substrate by a field oxide region, and comprised of a polysilicon gate structure, and P type source and drain regions; and
- a two part metal contact structure, comprised of wide, top layer of aluminum - copper, overlying a narrower tungsten stud, with the tungsten contact stud contacting said P type source and drain region, of said N type region of said semiconductor substrate.
Parent Case Info
This application is a continuation of Ser. No. 08/663,444, filed Jun. 13, 1996, now abandoned.
US Referenced Citations (10)
Non-Patent Literature Citations (1)
Entry |
Sze, S. M., Semiconductor Devices: Physics and Technology, John Wiley and Sons, pp. 360-361, 1985. |
Continuations (1)
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Number |
Date |
Country |
Parent |
663444 |
Jun 1996 |
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