Claims
- 1. A memory cell comprising:
- a transistor including a gate and first and second diffusion regions;
- a trench capacitor formed in a substrate, wherein the trench capacitor includes a dielectric collar formed within a first well region of the substrate in an upper portion of a trench, a buried diffusion region formed in a second well region below the first well region in the substrate surrounding a lower portion of the trench capacitor, a node diffusion region formed above the collar that electrically connects the transistor and the capacitor;
- a third diffusion region formed in the first well region without extending into the second well region, the third diffuision region being formed in the substrate and having a peak dopant concentration region adjacent to the collar wherein the collar has a thickness of between about 15 nm to about 20 nm, the third diffusion region comprising a dopant concentration sufficient to increase a gate threshold voltage of a parasitic transistor formed between the buried diffusion region and the node diffusion, so as to reduce leakage to less than or equal to 1 f amps.
- 2. The memory cell as recited in claim 1, wherein the third diffusion region further comprises dopants having a conductivity opposite of the buried diffusion region and the node diffusion.
- 3. The memory cell as recited in claim 1, wherein the third diffusion region comprises p-type dopants.
- 4. The memory cell as recited in claim 3, wherein the dopants are Boron having a concentration of between about 5.times.10.sup.17 to 2.times.10.sup.18 cm.sup.-3.
- 5. The memory cell as recited in claim 1, wherein the third diffusion region surrounds the trench forming an annular ring about the collar.
Parent Case Info
This is a divisional, of application Ser. No. 08/940,237 filed Sep. 30, 1997.
US Referenced Citations (11)
Foreign Referenced Citations (2)
Number |
Date |
Country |
362152156 |
Jul 1987 |
JPX |
364027258 |
Jan 1989 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Nesbit et al.; A 0.6 micrometer 256Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST); IEEE, IEDM, pp. 627-630, 1993. |
Divisions (1)
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Number |
Date |
Country |
Parent |
940237 |
Sep 1997 |
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