A signal generator, or function generator, is an apparatus that generates repeating waveform signals. Often signal generators have several built in types of waveform signals that they are able to generate. One of these types of signals is usually a ramp, or saw tooth, waveform.
Ramp waveform signal generators 4, 6 generate ramp waveform signals.
The ramp waveform signals Ramp 1, Ramp 2 are offset synchronized such that the linear development segment 14 of the second ramp waveform signal, Ramp 2, begins before the linear development segment 14 of the first ramp waveform signal, Ramp 1, ends and the linear development segment 14 of the first ramp waveform signal, Ramp 1, begins before the linear development segment 14 of the second ramp waveform signal, Ramp 2, ends. The offset synchronization of first and second ramp waveform signals, Ramp 1 and Ramp 2, may be further defined so that the upper 16 and lower 20 transition segments and the return segment 18 of the first ramp waveform signal, Ramp 1, occurs during the linear development segment 14 of the second ramp waveform signal, Ramp 2, and the upper 16 and lower 20 transition segments and the return segment 18 of the second ramp waveform signal, Ramp 2, occurs during the linear development segment 14 of the first ramp waveform signal, Ramp 1.
Sampler 8 is any means for sampling each ramp waveform signal Ramp 1, Ramp 2, during its linear development segment 14 to generate a reduced transition time ramp waveform signal.
Timing signal generator 10 is any apparatus or system configured to generate timing signals, Timing 1 and Timing 2. The timing signals, Timing 1 and Timing 2, are synchronized to have states opposite to one another (see
Clock 22 is any combination of hardware and executable code configured to generate a clock signal (see
Signal synchronizer 12 is any apparatus or system configured to synchronize the ramp waveform signals, Ramp 1 and Ramp 2, to the timing signals, Timing 1 and Timing 2. In one embodiment, the signal synchronizer includes constant voltage signal generators 26, 28 comparators 30, 32, 34, 36, and phase locked loops 38, 40, 42, 44.
Constant voltage signal generators 26, 28 generate constant voltage signals, DC1 and DC2, offset in amplitude from one another (see
The comparators are any combination of hardware and executable code configured to compare the ramp waveform signals, Ramp 1 and Ramp 2, to the constant voltage signals, DC1 and DC2, to produce result signals. When the ramp waveform signal, Ramp 1, is higher than the constant voltage signal DC1, the comparator 30, produces a high signal, otherwise it produces a low signal. When ramp signal, Ramp 1, is greater than constant voltage signal, DC2, comparator 32 produces a high signal, otherwise it produces a low signal. When ramp signal, Ramp 2, is higher than constant voltage signal, DC1, comparator 34 produces a high signal, otherwise it produces a low signal. When ramp signal, Ramp 2, is greater than constant voltage signal, DC2, comparator 36 produces a high signal, otherwise it produces a low signal.
The details of phase locked loops are well known and will not be discussed in this disclosure. The phase locked loops 38, 40, 42, 44 are any apparatus or system configured to control the synchronization and timing of ramp signal generators 4, 6. In one embodiment, phase locked loop 38 is configured to control the repetition frequency and phase of ramp signal, Ramp 1, such that each positive transition of the result signal CMP1H of comparator 30 occurs in time alignment with a positive transition of the timing signal, Timing 1. Phase locked loop 42 is configured to control the repetition frequency and phase of ramp signal, Ramp 2, such that each positive transition of the result signal CMP2H of comparator 34 occurs in time alignment with a positive transition of the timing signal, Timing 2. Phase locked loop 40 is configured to control the rate of change, or slope, of the linear development segment 14 of ramp signal, Ramp 1, such that each positive transition of the result signal CMP1L of comparator 32 occurs in time alignment with a positive transition of the timing signal Timing 2. Phase locked loop 44 is configured to control the rate of change, or slope, of the linear development segment of ramp signal, Ramp 2, such that each positive transition of the result signal CMP2L of comparator 36 occurs in time alignment with a positive transition of the timing signal, Timing 1.
In one embodiment, timing signals, Timing 1 and Timing 2, are generated 46. In one embodiment, timing signals, Timing 1 and Timing 2, are generated 46 by generating 48 a clock signal and deriving 50 the timing signals, Timing 1 and Timing 2, from the clock signal.
Ramp waveform signals, Ramp 1 and Ramp 2, are generated 52. Each ramp waveform signal Ramp 1 and Ramp 2, has a repeating sequence including a linear development segment 14, an upper transition segment 16, a return segment 18, and a lower transition segment 20. The ramp waveform signals, Ramp 1 and Ramp 2, are offset synchronized such that the linear development segment 14 of each ramp waveform signal begins before the linear development segment 14 of the other ramp waveform signal ends.
In one embodiment, the ramp waveform signals, Ramp 1 and Ramp 2, are synchronized to the timing signals, Timing 1 and Timing 2. In one embodiment, synchronizing the ramp signals, Ramp 1 and Ramp 2 to the timing signals timing 1 and Timing 2 includes generating constant voltage signals, DC1 and DC2, offset in amplitude from one another. Ramp waveform signals, Ramp 1 and Ramp 2, are compared to the constant voltage signals, DC1 and DC2, to produce result signals. When ramp waveform signal, Ramp 1, is higher than constant voltage signal, DC1, the first result signal, CMP1H, is high, otherwise it is low. When ramp waveform signal, Ramp 1, is greater than constant voltage signal, DC2, the second result signal, CMP1L, is high, otherwise it is low. When ramp waveform signal, Ramp 2, is higher than constant voltage signal, DC1, the third result signal, CMP2H, is high, otherwise it is low. When ramp waveform signal, Ramp 2, is greater than constant voltage signal, DC2, the fourth result signal, CMP2L, is high, otherwise it is low.
A repetition frequency and phase of ramp waveform signal, Ramp 1, is controlled such that each positive transition of the second result signal, CMP1L, occurs in time alignment with a positive transition of timing signal, Timing 1. A repetition frequency and phase of ramp waveform signal, Ramp 2, is controlled such that each positive transition of the fourth result signal, CMP2L, occurs in time alignment with a positive transition of timing signal, Timing 2. A rate of change, or slope, of the linear development segment 14 of ramp waveform signal, Ramp 1, is controlled such that each positive transition of the first result signal, CMP1H, occurs in time alignment with a positive transition of timing signal, Timing 2. A rate of change, or slope, of the linear development segment 14 of ramp waveform signal, Ramp 2, is controlled such that each positive transition of the third result signal, CMP2H, occurs in time alignment with a positive transition of timing signal, Timing 1.
Each ramp waveform signal, Ramp 1 and Ramp 2, is sampled 56 during its linear development segment 14 to generate a reduced transition time ramp waveform signal, Ramp Output.
The foregoing description is only illustrative of the invention. Various alternatives, modifications, and variances can be devised by those skilled in the art without departing from the invention. Accordingly, the present invention embraces all such alternatives, modifications, and variances that fall within the scope of the described invention.